Revision History
Revised Contents
1.
1.
2.
1.
2.
3.
4.
1.
Preliminary
In part 3: Modify Dpi 112 to 117.
In part 6: Delete command 70h.
In part 14: Add packing.
In part 5-1): Modify pin out list.
In part 7-5): Modify reference circuit.
In part 8: Modify typical operating sequence.
Rev.
1.0
Issued Date
Sep.10.2015
1.1
Oct.15.2015
1.2
Nov.03.2015
/
TECHNICAL SPECIFICATION
CONTENTS
ITEM
Cover
Revision History
Contents
Application
Features
Mechanical Specifications
Mechanical Drawing of EPD module
Input/Output Terminals
Command Table
Electrical Characteristics
Typical Operating Sequence
Optical Characteristics
Handling, Safety and Environment Requirements
Reliability test
Point and line standard
Packing
NO.
-
-
-
1
2
3
4
5
6
7
8
9
10
11
12
13
PAGE
1
2
3
4
4
4
5
6
8
27
33
37
39
40
42
43
/
1. Over View
The display is a TFT active matrix electrophoretic display, with interface and a reference system design. The 2.7” active area contains 264
176 pixels, and has 1-bit white/black full display capabilities. An integrated circuit contains gate buffer, source buffer, interface, timing
control logic, oscillator, DC-DC, SRAM, LUT, VCOM, and border are supplied with each panel.
2. Features
• High contrast
• High reflectance
• Ultra wide viewing angle
• Ultra low power consumption
• Pure reflective mode
• Bi-stable
• Commercial temperature range
• Landscape, portrait mode
• Antiglare hard-coated front-surface
• Low current deep sleep mode
• On chip display RAM
• Waveform stored in On-chip OTP
• Serial peripheral interface available
• On-chip oscillator
• On-chip booster and regulator control for generating VCOM, Gate and source driving voltage
• I2C Signal Master Interface to read external temperature sensor
• Available in COG package IC thickness 280um
3. Mechanical Specifications
Parameter
Screen Size
Display Resolution
Active Area
Pixel Pitch
Pixel Configuration
Outline Dimension
Weight
Specifications
2.7
264(H)×176(V)
57.288(H)×38.192(V)
0.217×0.217
Square
70.42(H)×45.8(V) ×0.98(D)
6.080.5
Unit
Inch
Pixel
mm
mm
mm
g
Remark
Dpi: 117
/
4. Mechanical Drawing of EPD module
D
T
L
,
.
O
C
s
c
i
n
o
r
t
c
e
l
E
e
r
a
h
s
e
v
a
W
r
e
p
a
P
-
e
h
c
n
i
7
.
2
/
5. Input/Output Terminals
5-1) Pin out List
Pin #
Type
Single
Description
Remark
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
GDR
RESE
VSLR
VSL
TSCL
TSDA
BS
BUSY_N
RST_N
DC
CSB
SCL
SDA
VDDIO
VDD
VSS
VDD
VOTP
VSH
VGH
VSHR
VGL
O
P
P
P
O
I/O
I
O
I
I
I
I
I/O
P
P
P
P
P
P
P
P
P
O
VCOM
No connection and do not connect with other NC pins
Keep Open
Note 5-5
Note 5-4
Note 5-3
Note 5-2
Note 5-1
This pin is N-MOS gate control
Current Sense Input for the Control Loop
Negative source voltage for Red
Negative source voltage
I2C clock for external temperature sensor
I2C data for external temperature sensor
Input interface setting
This pin indicates the driver status
Reset
Serial communication Command / Data input
Serial communication chip Select
Serial communication clock input
Serial communication date input
I/O voltage supply
Digital/Analog power
Digital ground
Voltage input & output
OTP Program power
Positive Source voltage
Positive gate voltage
Positive Source voltage for Red
Negative gate voltage
VCOM output
Note 5-1: This pin (CSB) is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CSB is
pulled Low.
Note 5-2: This pin (DC) is Data/Command control pin connecting to the MCU. When the pin is pulled HIGH, the data will be interpreted as
/
data. When the pin is pulled Low, the data will be interpreted as command.
Note 5-3: This pin (RST_N) is reset signal input. The Reset is active Low.
Note 5-4: This pin (BUSY_N) is BUSY_N state output pin. When BUSY_N is low, the operation of chip should not be interrupted and any
commands should not be issued to the module. The driver IC will put BUSY_N pin low when the driver IC is working such as:
- Outputting display waveform; or
- Programming with OTP
- Communicating with digital temperature sensor
Note 5-5: This pin (BS) is for 3-line SPI or 4-line SPI selection. When it is “Low”, 4-line SPI is selected. When it is “High”, 3-line SPI (9 bits
SPI) is selected. Please refer to below Table.
Table: Bus interface selection
BS
L
H
MPU Interface
4-lines serial peripheral interface (SPI)
3-lines serial peripheral interface (SPI) – 9 bits SPI
/
6. Command Table
W/R: 0: Write cycle 1: Read cycle
# Command
1
Panel
Setting(PSR)
2
3
4
5
6
7
Power setting
(PWR)
Power OFF(POF)
Power
OFF
Sequence Setting
(PFS)
Power ON(PON)
Power
Measure (PMES)
ON
Booster Soft Start
(BTST)
8 Deep Sleep
9
Data Start
Transmission 1
(DTM1)
10 Data Stop(DSP)
11 Display Refresh
(DRF)
Partial Data Start
transmission
1(PDTM1)
12
C/D: 0: Command 1: Data
D7~D0: -: Don’t care #: Valid Data
0
Default
00h
W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
0
0
1
#
0
-
-
-
-
-
0
0
-
0
0
0
#
#
-
0
1
0
#
0
#
0
0
#
#
0
-
-
-
-
-
0
0
-
0
0
0
#
#
-
0
0
0
#
0
-
0
0
#
#
0
-
-
#
#
#
0
0
#
0
0
0
#
#
#
0
1
0
#
0
-
0
0
#
#
0
-
-
#
#
#
0
0
#
0
0
0
#
#
#
0
0
1
#
1
-
1
1
#
#
0
-
-
#
#
#
0
0
-
0
0
0
#
#
#
0
0
0
#
0
-
0
0
#
#
0
-
#
#
#
#
0
0
-
1
1
1
#
#
#
1
1
0
#
0
-
0
1
#
#
0
#
#
#
#
#
1
1
-
0
0
1
#
#
#
1
0
0
#
0
-
1
0
#
#
1
#
#
#
#
#
0
1
-
0
1
0
#
#
#
1
1
0
#
1
-
0
0
#
ES[1],RES[0],LUT_EN,BWR, UD,SHL,
SHD_N,RST_N
07h
01h
VDS_EN, VDG_EN
03h
VCOM_HV,VGHL_LV[1],VGHL_LV[0] 20h
26h
VDH[5:0]
26h
VDL[5:0]
VDHR[5:0]
03h
02h
03h
T_VDS_OFF[1:0]
BT_PHA[7:0]
BT_PHB[7:0]
BT_PHC[5:0]
Data_flag
00h
04h
05h
06h
03h
00h
26h
07h
A5h
10h
00h
11h
00h
12h
14h
00h
/