ADS1263(Ads1262).pdf

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1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Device Comparison

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Timing Requirements: Serial Interface

7.7 Switching Characteristics: Serial Interface

7.8 Typical Characteristics

8 Parameter Measurement Information

8.1 Offset Temperature Drift Measurement

8.2 Gain Temperature Drift Measurement

8.3 Common-Mode Rejection Ratio Measurement

8.4 Power-Supply Rejection Ratio Measurement

8.5 Crosstalk Measurement (ADS1263)

8.6 Reference-Voltage Temperature-Drift Measurement

8.7 Reference-Voltage Thermal-Hysteresis Measurement

8.8 Noise Performance

9 Detailed Description

9.1 Overview

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Multifunction Analog Inputs

9.3.2 Analog Input Description

9.3.2.1 ESD Diode

9.3.2.2 Input Multiplexer

9.3.3 Sensor Bias

9.3.4 Temperature Sensor

9.3.5 Power-Supply Monitor

9.3.6 PGA

9.3.7 PGA Voltage Overrange Monitors

9.3.7.1 PGA Differential Output Monitor

9.3.7.2 PGA Absolute Output-Voltage Monitor

9.3.8 ADC Reference Voltage

9.3.8.1 Internal Reference

9.3.8.2 External Reference

9.3.8.3 Power-Supply Reference

9.3.8.4 Low-Reference Monitor

9.3.8.5 Sensor-Excitation Current Sources (IDAC1 and IDAC2)

9.3.8.6 Level-Shift Voltage

9.3.9 ADC1 Modulator

9.3.10 Digital Filter

9.3.10.1 Sinc Filter Mode

9.3.10.2 FIR Filter

9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection

9.3.11 General-Purpose Input/Output (GPIO)

9.3.12 Test DAC (TDAC)

9.3.13 ADC2 (ADS1263)

9.3.13.1 ADC2 Inputs

9.3.13.2 ADC2 PGA

9.3.13.3 ADC2 Reference

9.3.13.4 ADC2 Modulator

9.3.13.5 ADC2 Digital Filter

9.4 Device Functional Modes

9.4.1 Conversion Control

9.4.1.1 Continuous Conversion Mode

9.4.1.2 Pulse Conversion Mode

9.4.1.3 ADC2 Conversion Control (ADS1263)

9.4.2 Conversion Latency

9.4.3 Programmable Time Delay

9.4.4 Serial Interface

9.4.4.1 Chip Select (CS)

9.4.4.2 Serial Clock (SCLK)

9.4.4.3 Data Input (DIN)

9.4.4.4 Data Output/Data Ready (DOUT/DRDY)

9.4.4.5 Serial Interface Autoreset

9.4.5 Data Ready Pin (DRDY)

9.4.6 Conversion Data Software Polling

9.4.7 Read Conversion Data

9.4.7.1 Read Data Direct (ADC1 Only)

9.4.7.2 Read Data by Command

9.4.7.3 Data-Byte Sequence

9.4.8 ADC Clock Modes

9.4.8.1 Internal Oscillator

9.4.8.2 External Clock

9.4.8.3 Crystal Oscillator

9.4.9 Calibration

9.4.9.1 Offset and Full-Scale Calibration

9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)

9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)

9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)

9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)

9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)

9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)

9.4.9.8 Calibration Command Procedure

9.4.9.9 User Calibration Procedure

9.4.10 Reset

9.4.10.1 Power-On Reset (POR)

9.4.10.2 RESET/PWDN Pin

9.4.10.3 Reset by Command

9.4.11 Power-Down Mode

9.4.12 Chop Mode

9.5 Programming

9.5.1 NOP Command

9.5.2 RESET Command

9.5.3 START1, STOP1, START2, STOP2 Commands

9.5.4 RDATA1, RDATA2 Commands

9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands

9.5.6 RREG Command

9.5.7 WREG Command

9.6 Register Maps

9.6.1 Device Identification Register (address = 00h) [reset = x]

9.6.2 Power Register (address = 01h) [reset = 11h]

9.6.3 Interface Register (address = 02h) [reset = 05h]

9.6.4 Mode0 Register (address = 03h) [reset = 00h]

9.6.5 Mode1 Register (address = 04h) [reset = 80h]

9.6.6 Mode2 Register (address = 05h) [reset = 04h]

9.6.7 Input Multiplexer Register (address = 06h) [reset = 01h]

9.6.8 Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]

9.6.9 Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]

9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]

9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]

9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]

9.6.13 TDACP Control Register (address = 10h) [reset = 00h]

9.6.14 TDACN Control Register (address = 11h) [reset = 00h]

9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]

9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]

9.6.17 GPIO Data Register (address = 14h) [reset = 00h]

9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]

9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]

9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]

9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]

10 Application and Implementation

10.1 Application Information

10.1.1 Isolated (or Floated) Inputs

10.1.2 Single-Ended Measurements

10.1.3 Differential Measurements

10.1.4 Input Range

10.1.5 Input Filtering

10.1.5.1 Aliasing

10.1.6 Input Overload

10.1.7 Unused Inputs and Outputs

10.1.8 Voltage Reference

10.1.9 Serial Interface Connections

10.2 Typical Applications

10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation

10.2.1.1 Design Requirements

10.2.1.2 Detailed Design Procedure

10.2.1.3 Application Curve

10.3 Dos and Don'ts

10.4 Initialization Setup

11 Power-Supply Recommendations

11.1 Power-Supply Decoupling

11.2 Analog Power-Supply Clamp

11.3 Power-Supply Sequencing

12 Layout

12.1 Layout Guidelines

12.2 Layout Example

13 Device and Documentation Support

13.1 Related Links

13.2 Community Resources

13.3 Trademarks

13.4 Electrostatic Discharge Caution

13.5 Glossary

14 Mechanical, Packaging, and Orderable Information

ADS126x 32-Bit, Precision, 38-kSPS, Analog-to-Digital Converter (ADC) with Programmable Gain Amplifier (PGA) and Voltage Reference ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 1 Features 1• Precision, 32-bit, ΔΣ ADC • Auxiliary 24-Bit, ΔΣ ADC (ADS1263) • Data Rates: 2.5 SPS to 38400 SPS • Differential Input, CMOS PGA • 11 Multifunction Analog Inputs • High-Accuracy Architecture • – Offset Drift: 1 nV/°C – Gain Drift: 0.5 ppm/°C – Noise: 7 nVRMS (2.5 SPS, Gain = 32) – Linearity: 3 ppm 2.5-V Internal Voltage Reference – Temperature Drift: 2 ppm/°C 50-Hz and 60-Hz Rejection Internal Fault Monitors Internal ADC Test Signal 8 General-Purpose Input/Outputs • • Single-Cycle Settled Conversions • Dual Sensor Excitation Current Sources • • • 2 Applications • High-Resolution PLCs • Temperature, Pressure Measurement • Weigh Scales and Strain-Gauge Digitizers • Panel Meters, Chart Recorders • Analytical Instrumentation reference, and internal 3 Description The ADS1262 and ADS1263 are low-noise, low-drift, 38.4-kSPS, delta-sigma (ΔΣ) ADCs with an integrated PGA, fault monitors. The ADS1263 integrates an auxiliary, 24-bit, ΔΣ ADC intended for background measurements. The sensor- ready ADCs provide complete, high-accuracy, one- chip measurement solutions for the most-demanding including weigh scales, strain- sensor applications, gauge sensors, thermocouples, and resistance temperature devices (RTD). The ADCs are comprised of a low-noise, CMOS PGA (gains 1 to 32), a ΔΣ modulator, followed by a programmable digital filter. The flexible analog front- end (AFE) incorporates two sensor-excitation current sources suitable for direct RTD measurement. A single-cycle settling digital filter maximizes multiple- input conversion throughput, while providing 130-dB rejection of 50-Hz and 60-Hz line cycle interference. The ADS1262 and ADS1263 are pin and functional compatible. These devices are available in a 28-pin TSSOP package and are fully specified over the –40°C to +125°C temperature range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADS1262 ADS1263 (1) For all available packages, see the package option addendum 9.70 mm × 4.40 mm TSSOP (28) at the end of the data sheet. Temperature Compensated Bridge Measurement ADC Conversion Noise 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Time (s)ADC Output (2V)012345678910-0.25-0.2-0.15-0.1-0.0500.050.10.150.20.25D017Input Range = H78 mVData Rate = 20 SPSNoise = 0.16 2VP-P 32-Bit ûADCPGAInputMuxDigitalFilterSerialInterfaceandControlCSDOUT/DRDYSCLKDRDYSTARTClockMuxXTAL2XTAL1/CLKINREFOUTRef AlarmSignal AlarmBufAIN0AIN1AIN2AINCOMGPIOLevel ShiftTemp SensorADS1262ADS1263+5 VDVDDDGNDRef Mux2.5-V RefAIN3AIN4AIN5AIN6AIN7AIN8AIN9PGAADS1263 OnlyDigitalFilterDual Sensor ExcitationTest VInternalOscillator 24-Bit ûADCRESET/PWDNDINAVSSAVDD+ExcExcSig+SigSen+SenSensor TestPGAPt 100Bridge+3.3 VProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &Community

ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 www.ti.com Table of Contents 1 Features.................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison ............................................... 4 6 Pin Configuration and Functions ......................... 4 7 Specifications......................................................... 6 7.1 Absolute Maximum Ratings ...................................... 6 7.2 ESD Ratings.............................................................. 6 7.3 Recommended Operating Conditions....................... 7 7.4 Thermal Information.................................................. 7 7.5 Electrical Characteristics........................................... 8 7.6 Timing Requirements: Serial Interface.................... 11 7.7 Switching Characteristics: Serial Interface.............. 12 7.8 Typical Characteristics............................................ 13 8 Parameter Measurement Information ................ 24 8.1 Offset Temperature Drift Measurement .................. 24 8.2 Gain Temperature Drift Measurement .................... 24 8.3 Common-Mode Rejection Ratio Measurement....... 24 8.4 Power-Supply Rejection Ratio Measurement ......... 24 8.5 Crosstalk Measurement (ADS1263) ....................... 25 8.6 Reference-Voltage Temperature-Drift Measurement ........................................................... 25 8.7 Reference-Voltage Thermal-Hysteresis Measurement ........................................................... 25 8.8 Noise Performance ................................................. 26 9 Detailed Description ............................................ 30 9.1 Overview ................................................................. 30 9.2 Functional Block Diagram ....................................... 31 9.3 Feature Description................................................. 32 9.4 Device Functional Modes....................................... 61 9.5 Programming.......................................................... 85 9.6 Register Maps......................................................... 88 10 Application and Implementation...................... 106 10.1 Application Information........................................ 107 10.2 Typical Applications ............................................ 114 10.3 Dos and Don'ts.................................................... 119 10.4 Initialization Setup............................................... 120 11 Power-Supply Recommendations ................... 122 11.1 Power-Supply Decoupling................................... 122 11.2 Analog Power-Supply Clamp .............................. 123 11.3 Power-Supply Sequencing.................................. 123 12 Layout................................................................. 124 12.1 Layout Guidelines ............................................... 124 12.2 Layout Example .................................................. 125 13 Device and Documentation Support ............... 126 13.1 Related Links ...................................................... 126 13.2 Community Resources........................................ 126 13.3 Trademarks ......................................................... 126 13.4 Electrostatic Discharge Caution.......................... 126 13.5 Glossary .............................................................. 126 14 Mechanical, Packaging, and Orderable Information ......................................................... 126 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2015) to Revision B Page • Changed ADS1263 from product preview to production data, and added text and specifications throughout data sheet to include the ADS1263 and ADC2 .............................................................................................................................. 1 • Changed text throughout data sheet for clarity ...................................................................................................................... 1 • Added condition line to Absolute Maximum Ratings table ..................................................................................................... 6 • Added Crosstalk section to Electrical Characteristics table ................................................................................................... 9 • Added Figure 32 ................................................................................................................................................................... 17 • Added Figure 36 ................................................................................................................................................................... 18 • Changed legend in Figure 45 ............................................................................................................................................... 19 • Added missing gain term in FSR definition of Equation 8.................................................................................................... 26 • Changed text in fourth paragraph of Noise Performance section to clarify conditions to achieve maximum ENOB........... 26 • Changed bit names from PGAH and PGAL to PGAH_ALM and PGAL_ALM, respectively, in PGA Absolute Output- Voltage Monitor section ........................................................................................................................................................ 40 • Changed Figure 77 to show correct name of bit 4 ............................................................................................................... 41 • Changed RMUX to RMUXP in second paragraph of ADC Reference Voltage section ....................................................... 41 • Changed text in last paragraph of ADC Reference Voltage section to show correct name of bit 4 .................................... 41 • Changed text in External Reference section to clarify external reference inputs, polarity reversal switch, reference input current, and external reference buffer ......................................................................................................................... 42 • Changed text in Power-Supply Reference section to clarify use of power-supply reference in critical applications ........... 42 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263

www.ti.com ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 Revision History (continued) • Changed text in last paragraph of Sensor-Excitation Current Sources (IDAC1 and IDAC2) section to clarify settling time in IDAC rotation mode .................................................................................................................................................. 44 • Added ADC1 Modulator section ........................................................................................................................................... 45 • Changed text in General-Purpose Input/Output (GPIO) section regarding GPIO data readback when programmed as an output.......................................................................................................................................................................... 52 • Changed Figure 92............................................................................................................................................................... 52 • Changed TSIGP and TSIGN to TDACP and TDACN, respectively, in the last paragraph of the Test DAC (TDAC) section .................................................................................................................................................................................. 54 • Changed text in Test DAC (TDAC) section allowing for any common-mode value instead of 0 V...................................... 54 • Added note (1) to Figure 95 ................................................................................................................................................ 57 • Changed th(DRSP) value of 16 from max to min...................................................................................................................... 61 • Added stop-start sequence text to restart conversions in Continuous Conversion Mode section ....................................... 61 • Deleted software polling text from Data Ready (DRDY) section.......................................................................................... 67 • Added Conversion Data Software Polling section................................................................................................................ 67 • Added text to clarify data reset at conversion restart ........................................................................................................... 68 • Added text to Read Data Direct (ADC1) section to clarify conversion restart...................................................................... 68 • Changed Figure 108 to show complete list of CRC bit settings........................................................................................... 68 • Changed text in Read Data by Command section to clarify software polling ...................................................................... 69 • Changed Figure 109 to show complete list of CRC bit settings........................................................................................... 69 • Added text to Offset Calibration Registers section regarding offset calibration register disabled in chop mode................. 76 • Added new step 1 to Calibration Command Procedure section........................................................................................... 79 • Added text to WREG Command section regarding conversion restart ................................................................................ 87 • Changed text in 2nd paragraph of Register Map section..................................................................................................... 88 • Changed Group Update column of Table 38 ...................................................................................................................... 88 • Added software polling to Figure 159................................................................................................................................. 120 Changes from Original (February 2015) to Revision A Page • Changed ADS1262 from product preview to production data................................................................................................ 1 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADS1262 ADS1263

ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 5 Device Comparison www.ti.com PRODUCT ADS1262 ADS1263 INPUTS 11 11 AUXILIARY 24-BIT ADC No Yes 6 Pin Configuration and Functions PW Package 28-Pin TSSOP Top View (Not To Scale) 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 AIN8AIN9AINCOMCAPPAIN7AIN6AIN5AIN4CAPNAVDDAVSSREFOUTSTARTCSSCLKDINDOUT/DRDYDRDYAIN3AIN2AIN1AIN0RESET/PWDNDVDDDGNDBYPASSXTAL1/CLKINXTAL212345678910111213142827262524232221201918171615

www.ti.com ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 PIN NAME AIN8 AIN9 AINCOM CAPP CAPN AVDD AVSS REFOUT START CS SCLK DIN DOUT/DRDY DRDY I/O Analog input/output Analog input/output Analog input/output Analog output Analog output Analog Analog Analog Output Digital Input Digital Input Digital Input Digital Input Digital output Digital output XTAL1/CLKIN Digital Input XTAL2 BYPASS DGND DVDD Digital Input Analog Output Digital Digital RESET/PWDN Digital input AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Pin Functions DESCRIPTION Analog input 8, IDAC1, IDAC2, GPIO5 Analog input 9, IDAC1, IDAC2, GPIO6 Analog input common, IDAC1, IDAC2, GPIO7, VBIAS PGA output P: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN PGA output N: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN Positive analog power supply Negative analog power supply Internal reference voltage output, connect 1-µF capacitor to AVSS Start conversion control Serial interface chip select (active low) Serial interface shift clock Serial interface data input Serial interface data output and data ready indicator (active low) Data ready indicator (active low) 1) Internal oscillator: Connect to DGND 2) External clock: Connect clock input 3) Crystal oscillator: Connect to crystal and crystal load capacitor 1) Internal oscillator: No connection (float) 2) External clock: No connection (float) 3) Crystal oscillator: Connect to crystal and crystal load capacitor 2-V sub-regulator external bypass; connect 1-µF capacitor to DGND Digital ground Digital power supply Reset (active low); hold low to power down the ADC Analog input 0, REFP1, IDAC1, IDAC2 Analog input 1, REFN1, IDAC1, IDAC2 Analog input 2 ,REFP2, IDAC1, IDAC2 Analog input 3, REFN2, IDAC1, IDAC2, GPIO0 Analog input 4, REFP3, IDAC1, IDAC2, GPIO1 Analog input 5, REFN3, IDAC1, IDAC2, GPIO2 Analog input 6, IDAC1, IDAC2, GPIO3, TDACP Analog input 7, IDAC1, IDAC2, GPIO4, TDACN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADS1262 ADS1263

ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Voltage Current Temperature AVDD to AVSS AVSS to DGND DVDD to DGND Analog input Digital input Input current(2) Junction, TJ Storage, Tstg www.ti.com MIN –0.3 –3 –0.3 MAX 7 0.3 7 VAVSS – 0.3 VAVDD + 0.3 VDGND – 0.3 VDVDD + 0.3 –10 –50 -60 10 150 150 UNIT V V V V V mA °C °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds VAVDD + 0.3 V or is below VAVSS – 0.3 V, or if the digital input voltage exceeds VDVDD + 0.3 V or is below VDGND – 0.3 V. (2) 7.2 ESD Ratings V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged-device model (CDM), per JEDEC specification JESD22-C101(2) VALUE ±2000 ±500 UNIT V (1) (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263

www.ti.com 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 NOM 5 MIN 4.75 –2.6 2.7 –VREF / Gain See Equation 12 VAVSS – 0.1 –VREF / Gain VAVSS – 0.1 See Equation 15 MAX UNIT 5.25 0 5.25 VREF / Gain VAVDD + 0.1 VREF / Gain VAVDD + 0.1 VAVDD – VAVSS + 0.2 VREFP – 0.9 VAVDD + 0.1 V V V V V V V V V V V V VAVDD to VAVSS VAVSS to VDGND VDVDD to VDGND PGA enabled PGA bypassed Gain = 1, 2 and 4 Gain = 8 to 128 VREF = VREFP – VREFN POWER SUPPLY Analog power supply Digital power supply ADC1 ANALOG INPUTS FSR Full-scale differential input voltage range(1) VINP,VINN Absolute input voltage(2) ADC2 ANALOG INPUTS (ADS1263) Full-scale differential input voltage range Absolute input voltage VOLTAGE REFERENCE INPUTS VREF VREFN VREFP CLOCK INPUT Differential reference voltage Negative reference voltage Positive reference voltage fCLK External clock frequency External clock duty cycle External crystal frequency GENERAL-PURPOSE INPUT/OUTPUT (GPIO) Input voltage DIGITAL INPUTS (other than GPIO) Input voltage 0.9 VAVSS – 0.1 VREFN + 0.9 1 30% 1 VAVSS VDGND 7.3728 7.3728 8 MHz 70% 8 MHz VAVDD VDVDD V V °C TEMPERATURE TA (1) FSR is the ideal full-scale differential input voltage range, excluding noise, offset and gain errors. For ADC1, the maximum FSR is Operating ambient temperature 125 –40 achieved with VREF = 5 V and the PGA bypassed. If the PGA is enabled and VREF = 5 V, the FSR is limited by the PGA input range. For ADC2, if VREF = 5 V and gains = 8 to 128 then FSR is limited by the PGA input range. (2) VINP, VINN = Absolute Input Voltage. VIN = Differential Input Voltage = VINP – VINN. 7.4 Thermal Information THERMAL METRIC(1) ADS126x PW (TSSOP) 28 PINS UNIT RθJA RθJC(top) RθJB ψJT ψJB RθJC(bot) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance °C/W °C/W °C/W °C/W °C/W °C/W 65.2 13.6 23.6 0.5 23.1 N/A report, SPRA953. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS1262 ADS1263

ADS1262, ADS1263 SBAS661B –FEBRUARY 2015–REVISED JULY 2015 www.ti.com 7.5 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted). TYP TEST CONDITIONS PARAMETER MIN MAX UNIT ADC1 ANALOG INPUTS Absolute input current Differential input current Differential input impedance Channel-to-channel crosstalk Gain = 32 PGA bypassed Gain = 32 PGA bypassed, VIN = 5 V PGA enabled PGA bypassed DC, VAVSS ≤ VINX ≤ VAVDD ADC1 PERFORMANCE DR INL VOS PGA gain Resolution Data rate Noise performance Integral nonlinearity Offset voltage Offset voltage drift GE Gain error NMRR CMRR Gain drift Normal-mode rejection ratio(2) Common-mode rejection ratio(3) PSRR Power-supply rejection ratio(4) ADC2 ANALOG INPUTS (ADS1263) Absolute input current Differential input current ADC2 PERFORMANCE (ADS1263) Gain Resolution Data rate Noise performance Integral nonlinearity Offset voltage Offset voltage drift Gain error Gain drift Normal-mode rejection ratio DR INL VOS GE NMRR Gain = 1 to 32, PGA bypassed TA = 25°C Chop mode off Chop mode on After calibration(1) Chop mode off Chop mode on TA = 25°C, gain = 1 to 32 After calibration(1) Gain = 1 to 32, and PGA bypassed fIN = 60 Hz, data rate = 20 SPS fIN = 60 Hz, data rate = 400 SPS AVDD and AVSS DVDD Gain = 16 Gain = 16 Gain = 1 to 64 Gain = 128 TA = 25°C, gain = 1 to 128 Gain = 1 to 128 TA = 25°C, gain = 1 to 128 Gain = 1 to 128 4 ppm/°C nA nA nA nA GΩ MΩ µV/V V/V Bits SPS ppm µV µV nV/°C nV/°C ppm dB dB dB dB nA nA V/V Bits SPS ppm ppm µV nV/°C ppm ppm/°C dB dB dB 2 150 0.1 150 1 40 0.5 1, 2, 4, 8, 16, 32 32 2.5 See Table 1 3 350 / Gain ±0.1 / Gain Noise / 4 38400 12 800 / Gain ±0.5 / Gain 30 / Gain + 10 100 / Gain + 50 5 ±300 1 ±50 Noise / 4 0.5 See Table 11 130 120 90 120 100 80 80 2 0.5 1, 2, 4, 8, 16, 32, 64, 128 24 10, 100, 400, 800 20 30 ±500 200 ±3000 5 See Table 3 4 7 ±150 30 ±500 1 See Table 15 110 90 90 CMRR Common-mode rejection ratio PSRR Power-supply rejection ratio fIN = 60 Hz, DR = 10 SPS fIN = 60 Hz, DR = 400 SPS, gain = 8 AVDD and AVSS 75 75 (1) Offset and gain calibration accuracy on the order of ADC conversion noise/4. Conversion noise depends on data rate and PGA gain. (2) Normal-mode rejection ratio depends on the digital filter setting. (3) Common-mode rejection ratio is specified at date rate 20 SPS and 400 SPS. (4) Power-supply rejection ratio is specified at dc. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263

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