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ATmega328P数据手册(ATmega328P_datasheet_Complete).pdf
Features
1. Pin Configurations
1.1 Pin Descriptions
1.1.1 VCC
1.1.2 GND
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
1.1.4 Port C (PC5:0)
1.1.5 PC6/RESET
1.1.6 Port D (PD7:0)
1.1.7 AVCC
1.1.8 AREF
1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)
2. Overview
2.1 Block Diagram
2.2 Comparison Between Processors
3. Resources
4. Data Retention
5. About Code Examples
6. Capacitive Touch Sensing
7. AVR CPU Core
7.1 Overview
7.2 ALU – Arithmetic Logic Unit
7.3 Status Register
7.3.1 SREG – AVR Status Register
7.4 General Purpose Register File
7.4.1 The X-register, Y-register, and Z-register
7.5 Stack Pointer
7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
7.6 Instruction Execution Timing
7.7 Reset and Interrupt Handling
7.7.1 Interrupt Response Time
8. AVR Memories
8.1 Overview
8.2 In-System Reprogrammable Flash Program Memory
8.3 SRAM Data Memory
8.3.1 Data Memory Access Times
8.4 EEPROM Data Memory
8.4.1 EEPROM Read/Write Access
8.4.2 Preventing EEPROM Corruption
8.5 I/O Memory
8.5.1 General Purpose I/O Registers
8.6 Register Description
8.6.1 EEARH and EEARL – The EEPROM Address Register
8.6.2 EEDR – The EEPROM Data Register
8.6.3 EECR – The EEPROM Control Register
8.6.4 GPIOR2 – General Purpose I/O Register 2
8.6.5 GPIOR1 – General Purpose I/O Register 1
8.6.6 GPIOR0 – General Purpose I/O Register 0
9. System Clock and Clock Options
9.1 Clock Systems and their Distribution
9.1.1 CPU Clock – clkCPU
9.1.2 I/O Clock – clkI/O
9.1.3 Flash Clock – clkFLASH
9.1.4 Asynchronous Timer Clock – clkASY
9.1.5 ADC Clock – clkADC
9.2 Clock Sources
9.2.1 Default Clock Source
9.2.2 Clock Startup Sequence
9.3 Low Power Crystal Oscillator
9.4 Full Swing Crystal Oscillator
9.5 Low Frequency Crystal Oscillator
9.6 Calibrated Internal RC Oscillator
9.7 128kHz Internal Oscillator
9.8 External Clock
9.9 Clock Output Buffer
9.10 Timer/Counter Oscillator
9.11 System Clock Prescaler
9.12 Register Description
9.12.1 OSCCAL – Oscillator Calibration Register
9.12.2 CLKPR – Clock Prescale Register
10. Power Management and Sleep Modes
10.1 Sleep Modes
10.2 BOD Disable(1)
10.3 Idle Mode
10.4 ADC Noise Reduction Mode
10.5 Power-down Mode
10.6 Power-save Mode
10.7 Standby Mode
10.8 Extended Standby Mode
10.9 Power Reduction Register
10.10 Minimizing Power Consumption
10.10.1 Analog to Digital Converter
10.10.2 Analog Comparator
10.10.3 Brown-out Detector
10.10.4 Internal Voltage Reference
10.10.5 Watchdog Timer
10.10.6 Port Pins
10.10.7 On-chip Debug System
10.11 Register Description
10.11.1 SMCR – Sleep Mode Control Register
10.11.2 MCUCR – MCU Control Register
10.11.3 PRR – Power Reduction Register
11. System Control and Reset
11.1 Resetting the AVR
11.2 Reset Sources
11.3 Power-on Reset
11.4 External Reset
11.5 Brown-out Detection
11.6 Watchdog System Reset
11.7 Internal Voltage Reference
11.7.1 Voltage Reference Enable Signals and Start-up Time
11.8 Watchdog Timer
11.8.1 Features
11.8.2 Overview
11.9 Register Description
11.9.1 MCUSR – MCU Status Register
11.9.2 WDTCSR – Watchdog Timer Control Register
12. Interrupts
12.1 Interrupt Vectors in ATmega48A and ATmega48PA
12.2 Interrupt Vectors in ATmega88A and ATmega88PA
12.3 Interrupt Vectors in ATmega168A and ATmega168PA
12.4 Interrupt Vectors in ATmega328 and ATmega328P
12.5 Register Description
12.5.1 Moving Interrupts Between Application and Boot Space, ATmega88A/88PA, ATmega168A/168PA and ATmega328/328P
13. External Interrupts
13.1 Pin Change Interrupt Timing
13.2 Register Description
13.2.1 EICRA – External Interrupt Control Register A
13.2.2 EIMSK – External Interrupt Mask Register
13.2.3 EIFR – External Interrupt Flag Register
13.2.4 PCICR – Pin Change Interrupt Control Register
13.2.5 PCIFR – Pin Change Interrupt Flag Register
13.2.6 PCMSK2 – Pin Change Mask Register 2
13.2.7 PCMSK1 – Pin Change Mask Register 1
13.2.8 PCMSK0 – Pin Change Mask Register 0
14. I/O-Ports
14.1 Overview
14.2 Ports as General Digital I/O
14.2.1 Configuring the Pin
14.2.2 Toggling the Pin
14.2.3 Switching Between Input and Output
14.2.4 Reading the Pin Value
14.2.5 Digital Input Enable and Sleep Modes
14.2.6 Unconnected Pins
14.3 Alternate Port Functions
14.3.1 Alternate Functions of Port B
14.3.2 Alternate Functions of Port C
14.3.3 Alternate Functions of Port D
14.4 Register Description
14.4.1 MCUCR – MCU Control Register
14.4.2 PORTB – The Port B Data Register
14.4.3 DDRB – The Port B Data Direction Register
14.4.4 PINB – The Port B Input Pins Address(1)
14.4.5 PORTC – The Port C Data Register
14.4.6 DDRC – The Port C Data Direction Register
14.4.7 PINC – The Port C Input Pins Address(1)
14.4.8 PORTD – The Port D Data Register
14.4.9 DDRD – The Port D Data Direction Register
14.4.10 PIND – The Port D Input Pins Address(1)
15. 8-bit Timer/Counter0 with PWM
15.1 Features
15.2 Overview
15.2.1 Definitions
15.2.2 Registers
15.3 Timer/Counter Clock Sources
15.4 Counter Unit
15.5 Output Compare Unit
15.5.1 Force Output Compare
15.5.2 Compare Match Blocking by TCNT0 Write
15.5.3 Using the Output Compare Unit
15.6 Compare Match Output Unit
15.6.1 Compare Output Mode and Waveform Generation
15.7 Modes of Operation
15.7.1 Normal Mode
15.7.2 Clear Timer on Compare Match (CTC) Mode
15.7.3 Fast PWM Mode
15.7.4 Phase Correct PWM Mode
15.8 Timer/Counter Timing Diagrams
15.9 Register Description
15.9.1 TCCR0A – Timer/Counter Control Register A
15.9.2 TCCR0B – Timer/Counter Control Register B
15.9.3 TCNT0 – Timer/Counter Register
15.9.4 OCR0A – Output Compare Register A
15.9.5 OCR0B – Output Compare Register B
15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
16. 16-bit Timer/Counter1 with PWM
16.1 Features
16.2 Overview
16.2.1 Registers
16.2.2 Definitions
16.3 Accessing 16-bit Registers
16.3.1 Reusing the Temporary High Byte Register
16.4 Timer/Counter Clock Sources
16.5 Counter Unit
16.6 Input Capture Unit
16.6.1 Input Capture Trigger Source
16.6.2 Noise Canceler
16.6.3 Using the Input Capture Unit
16.7 Output Compare Units
16.7.1 Force Output Compare
16.7.2 Compare Match Blocking by TCNT1 Write
16.7.3 Using the Output Compare Unit
16.8 Compare Match Output Unit
16.8.1 Compare Output Mode and Waveform Generation
16.9 Modes of Operation
16.9.1 Normal Mode
16.9.2 Clear Timer on Compare Match (CTC) Mode
16.9.3 Fast PWM Mode
16.9.4 Phase Correct PWM Mode
16.9.5 Phase and Frequency Correct PWM Mode
16.10 Timer/Counter Timing Diagrams
16.11 Register Description
16.11.1 TCCR1A – Timer/Counter1 Control Register A
16.11.2 TCCR1B – Timer/Counter1 Control Register B
16.11.3 TCCR1C – Timer/Counter1 Control Register C
16.11.4 TCNT1H and TCNT1L – Timer/Counter1
16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
16.11.7 ICR1H and ICR1L – Input Capture Register 1
16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
17. Timer/Counter0 and Timer/Counter1 Prescalers
17.1 Internal Clock Source
17.2 Prescaler Reset
17.3 External Clock Source
17.4 Register Description
17.4.1 GTCCR – General Timer/Counter Control Register
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1 Features
18.2 Overview
18.2.1 Registers
18.2.2 Definitions
18.3 Timer/Counter Clock Sources
18.4 Counter Unit
18.5 Output Compare Unit
18.5.1 Force Output Compare
18.5.2 Compare Match Blocking by TCNT2 Write
18.5.3 Using the Output Compare Unit
18.6 Compare Match Output Unit
18.6.1 Compare Output Mode and Waveform Generation
18.7 Modes of Operation
18.7.1 Normal Mode
18.7.2 Clear Timer on Compare Match (CTC) Mode
18.7.3 Fast PWM Mode
18.7.4 Phase Correct PWM Mode
18.8 Timer/Counter Timing Diagrams
18.9 Asynchronous Operation of Timer/Counter2
18.10 Timer/Counter Prescaler
18.11 Register Description
18.11.1 TCCR2A – Timer/Counter Control Register A
18.11.2 TCCR2B – Timer/Counter Control Register B
18.11.3 TCNT2 – Timer/Counter Register
18.11.4 OCR2A – Output Compare Register A
18.11.5 OCR2B – Output Compare Register B
18.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register
18.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register
18.11.8 ASSR – Asynchronous Status Register
18.11.9 GTCCR – General Timer/Counter Control Register
19. SPI – Serial Peripheral Interface
19.1 Features
19.2 Overview
19.3 SS Pin Functionality
19.3.1 Slave Mode
19.3.2 Master Mode
19.4 Data Modes
19.5 Register Description
19.5.1 SPCR – SPI Control Register
19.5.2 SPSR – SPI Status Register
19.5.3 SPDR – SPI Data Register
20. USART0
20.1 Features
20.2 Overview
20.3 Clock Generation
20.3.1 Internal Clock Generation – The Baud Rate Generator
20.3.2 Double Speed Operation (U2Xn)
20.3.3 External Clock
20.3.4 Synchronous Clock Operation
20.4 Frame Formats
20.4.1 Parity Bit Calculation
20.5 USART Initialization
20.6 Data Transmission – The USART Transmitter
20.6.1 Sending Frames with 5 to 8 Data Bit
20.6.2 Sending Frames with 9 Data Bit
20.6.3 Transmitter Flags and Interrupts
20.6.4 Parity Generator
20.6.5 Disabling the Transmitter
20.7 Data Reception – The USART Receiver
20.7.1 Receiving Frames with 5 to 8 Data Bits
20.7.2 Receiving Frames with 9 Data Bits
20.7.3 Receive Compete Flag and Interrupt
20.7.4 Receiver Error Flags
20.7.5 Parity Checker
20.7.6 Disabling the Receiver
20.7.7 Flushing the Receive Buffer
20.8 Asynchronous Data Reception
20.8.1 Asynchronous Clock Recovery
20.8.2 Asynchronous Data Recovery
20.8.3 Asynchronous Operational Range
20.9 Multi-processor Communication Mode
20.9.1 Using MPCMn
20.10 Examples of Baud Rate Setting
20.11 Register Description
20.11.1 UDRn – USART I/O Data Register n
20.11.2 UCSRnA – USART Control and Status Register n A
20.11.3 UCSRnB – USART Control and Status Register n B
20.11.4 UCSRnC – USART Control and Status Register n C
20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers
21. USART in SPI Mode
21.1 Features
21.2 Overview
21.3 Clock Generation
21.4 SPI Data Modes and Timing
21.5 Frame Formats
21.5.1 USART MSPIM Initialization
21.6 Data Transfer
21.6.1 Transmitter and Receiver Flags and Interrupts
21.6.2 Disabling the Transmitter or Receiver
21.7 AVR USART MSPIM vs. AVR SPI
21.8 Register Description
21.8.1 UDRn – USART MSPIM I/O Data Register
21.8.2 UCSRnA – USART MSPIM Control and Status Register n A
21.8.3 UCSRnB – USART MSPIM Control and Status Register n B
21.8.4 UCSRnC – USART MSPIM Control and Status Register n C
21.8.5 USART MSPIM Baud Rate Registers – UBRRnL and UBRRnH
22. 2-wire Serial Interface
22.1 Features
22.2 2-wire Serial Interface Bus Definition
22.2.1 TWI Terminology
22.2.2 Electrical Interconnection
22.3 Data Transfer and Frame Format
22.3.1 Transferring Bits
22.3.2 START and STOP Conditions
22.3.3 Address Packet Format
22.3.4 Data Packet Format
22.3.5 Combining Address and Data Packets into a Transmission
22.4 Multi-master Bus Systems, Arbitration and Synchronization
22.5 Overview of the TWI Module
22.5.1 SCL and SDA Pins
22.5.2 Bit Rate Generator Unit
22.5.3 Bus Interface Unit
22.5.4 Address Match Unit
22.5.5 Control Unit
22.6 Using the TWI
22.7 Transmission Modes
22.7.1 Master Transmitter Mode
22.7.2 Master Receiver Mode
22.7.3 Slave Receiver Mode
22.7.4 Slave Transmitter Mode
22.7.5 Miscellaneous States
22.7.6 Combining Several TWI Modes
22.8 Multi-master Systems and Arbitration
22.9 Register Description
22.9.1 TWBR – TWI Bit Rate Register
22.9.2 TWCR – TWI Control Register
22.9.3 TWSR – TWI Status Register
22.9.4 TWDR – TWI Data Register
22.9.5 TWAR – TWI (Slave) Address Register
22.9.6 TWAMR – TWI (Slave) Address Mask Register
23. Analog Comparator
23.1 Overview
23.2 Analog Comparator Multiplexed Input
23.3 Register Description
23.3.1 ADCSRB – ADC Control and Status Register B
23.3.2 ACSR – Analog Comparator Control and Status Register
23.3.3 DIDR1 – Digital Input Disable Register 1
24. Analog-to-Digital Converter
24.1 Features
24.2 Overview
24.3 Starting a Conversion
24.4 Prescaling and Conversion Timing
24.5 Changing Channel or Reference Selection
24.5.1 ADC Input Channels
24.5.2 ADC Voltage Reference
24.6 ADC Noise Canceler
24.6.1 Analog Input Circuitry
24.6.2 Analog Noise Canceling Techniques
24.6.3 ADC Accuracy Definitions
24.7 ADC Conversion Result
24.8 Temperature Measurement
24.9 Register Description
24.9.1 ADMUX – ADC Multiplexer Selection Register
24.9.2 ADCSRA – ADC Control and Status Register A
24.9.3 ADCL and ADCH – The ADC Data Register
24.9.4 ADCSRB – ADC Control and Status Register B
24.9.5 DIDR0 – Digital Input Disable Register 0
25. debugWIRE On-chip Debug System
25.1 Features
25.2 Overview
25.3 Physical Interface
25.4 Software Break Points
25.5 Limitations of debugWIRE
25.6 Register Description
25.6.1 DWDR – debugWire Data Register
26. Self-Programming the Flash, ATmega 48A/48PA
26.1 Overview
26.1.1 Performing Page Erase by SPM
26.1.2 Filling the Temporary Buffer (Page Loading)
26.1.3 Performing a Page Write
26.2 Addressing the Flash During Self-Programming
26.2.1 EEPROM Write Prevents Writing to SPMCSR
26.2.2 Reading the Fuse and Lock Bits from Software
26.2.3 Preventing Flash Corruption
26.2.4 Programming Time for Flash when Using SPM
26.2.5 Simple Assembly Code Example for a Boot Loader
26.3 Register Description
26.3.1 SPMCSR – Store Program Memory Control and Status Register
27. Boot Loader Support – Read-While-Write Self-Programming
27.1 Features
27.2 Overview
27.3 Application and Boot Loader Flash Sections
27.3.1 Application Section
27.3.2 BLS – Boot Loader Section
27.4 Read-While-Write and No Read-While-Write Flash Sections
27.4.1 RWW – Read-While-Write Section
27.4.2 NRWW – No Read-While-Write Section
27.5 Boot Loader Lock Bits
27.6 Entering the Boot Loader Program
27.7 Addressing the Flash During Self-Programming
27.8 Self-Programming the Flash
27.8.1 Performing Page Erase by SPM
27.8.2 Filling the Temporary Buffer (Page Loading)
27.8.3 Performing a Page Write
27.8.4 Using the SPM Interrupt
27.8.5 Consideration While Updating BLS
27.8.6 Prevent Reading the RWW Section During Self-Programming
27.8.7 Setting the Boot Loader Lock Bits by SPM
27.8.8 EEPROM Write Prevents Writing to SPMCSR
27.8.9 Reading the Fuse and Lock Bits from Software
27.8.10 Reading the Signature Row from Software
27.8.11 Preventing Flash Corruption
27.8.12 Programming Time for Flash when Using SPM
27.8.13 Simple Assembly Code Example for a Boot Loader
27.8.14 ATmega88A and ATmega88PA Boot Loader Parameters
27.8.15 ATmega168A and ATmega168PA Boot Loader Parameters
27.8.16 ATmega328 and ATmega328P Boot Loader Parameters
27.9 Register Description
27.9.1 SPMCSR – Store Program Memory Control and Status Register
28. Memory Programming
28.1 Program And Data Memory Lock Bits
28.2 Fuse Bits
28.2.1 Latching of Fuses
28.3 Signature Bytes
28.4 Calibration Byte
28.5 Page Size
28.6 Parallel Programming Parameters, Pin Mapping, and Commands
28.6.1 Signal Names
28.7 Parallel Programming
28.7.1 Enter Programming Mode
28.7.2 Considerations for Efficient Programming
28.7.3 Chip Erase
28.7.4 Programming the Flash
28.7.5 Programming the EEPROM
28.7.6 Reading the Flash
28.7.7 Reading the EEPROM
28.7.8 Programming the Fuse Low Bits
28.7.9 Programming the Fuse High Bits
28.7.10 Programming the Extended Fuse Bits
28.7.11 Programming the Lock Bits
28.7.12 Reading the Fuse and Lock Bits
28.7.13 Reading the Signature Bytes
28.7.14 Reading the Calibration Byte
28.7.15 Parallel Programming Characteristics
28.8 Serial Downloading
28.8.1 Serial Programming Pin Mapping
28.8.2 Serial Programming Algorithm
28.8.3 Serial Programming Instruction set
28.8.4 SPI Serial Programming Characteristics
29. Electrical Characteristics – (TA = -40°C to 85°C)
29.1 Absolute Maximum Ratings*
29.2 DC Characteristics
29.2.1 ATmega48A DC Characteristics
29.2.2 ATmega48PA DC Characteristics – Current Consumption
29.2.3 ATmega88A DC Characteristics
29.2.4 ATmega88PA DC Characteristics
29.2.5 ATmega168A DC Characteristics
29.2.6 ATmega168PA DC Characteristics
29.2.7 ATmega328 DC Characteristics
29.2.8 ATmega328P DC Characteristics
29.3 Speed Grades
29.4 Clock Characteristics
29.4.1 Calibrated Internal RC Oscillator Accuracy
29.4.2 External Clock Drive Waveforms
29.4.3 External Clock Drive
29.5 System and Reset Characteristics
29.6 SPI Timing Characteristics
29.7 Two-wire Serial Interface Characteristics
29.8 ADC Characteristics
29.9 Parallel Programming Characteristics
30. Electrical Characteristics (TA = -40°C to 105°C)
30.1 Absolute Maximum Ratings*
30.2 DC Characteristics
30.2.1 ATmega48PA DC Characteristics – Current Consumption
30.2.2 ATmega88PA DC Characteristics – Current Consumption
30.2.3 ATmega168PA DC Characteristics – Current Consumption
30.2.4 ATmega328P DC Characteristics – Current Consumption
31. Typical Characteristics – (TA = -40°C to 85°C)
31.1 ATmega48A Typical Characteristics
31.1.1 Active Supply Current
31.1.2 Idle Supply Current
31.1.3 ATmega48A: Supply Current of IO Modules
31.1.4 Power-down Supply Current
31.1.5 Power-save Supply Current
31.1.6 Standby Supply Current
31.1.7 Pin Pull-Up
31.1.8 Pin Driver Strength
31.1.9 Pin Threshold and Hysteresis
31.1.10 BOD Threshold
31.1.11 Internal Oscillator Speed
31.1.12 Current Consumption of Peripheral Units
31.1.13 Current Consumption in Reset and Reset Pulsewidth
31.2 ATmega48PA Typical Characteristics
31.2.1 Active Supply Current
31.2.2 Idle Supply Current
31.2.3 ATmega48PA: Supply Current of IO Modules
31.2.4 Power-down Supply Current
31.2.5 Power-save Supply Current
31.2.6 Standby Supply Current
31.2.7 Pin Pull-Up
31.2.8 Pin Driver Strength
31.2.9 Pin Threshold and Hysteresis
31.2.10 BOD Threshold
31.2.11 Internal Oscillator Speed
31.2.12 Current Consumption of Peripheral Units
31.2.13 Current Consumption in Reset and Reset Pulsewidth
31.3 ATmega88A Typical Characteristics
31.3.1 Active Supply Current
31.3.2 Idle Supply Current
31.3.3 ATmega88A: Supply Current of IO Modules
31.3.4 Power-down Supply Current
31.3.5 Power-save Supply Current
31.3.6 Standby Supply Current
31.3.7 Pin Pull-Up
31.3.8 Pin Driver Strength
31.3.9 Pin Threshold and Hysteresis
31.3.10 BOD Threshold
31.3.11 Internal Oscillator Speed
31.3.12 Current Consumption of Peripheral Units
31.3.13 Current Consumption in Reset and Reset Pulsewidth
31.4 ATmega88PA Typical Characteristics
31.4.1 Active Supply Current
31.4.2 Idle Supply Current
31.4.3 ATmega88PA: Supply Current of IO Modules
31.4.4 Power-down Supply Current
31.4.5 Power-save Supply Current
31.4.6 Standby Supply Current
31.4.7 Pin Pull-Up
31.4.8 Pin Driver Strength
31.4.9 Pin Threshold and Hysteresis
31.4.10 BOD Threshold
31.4.11 Internal Oscillator Speed
31.4.12 Current Consumption of Peripheral Units
31.4.13 Current Consumption in Reset and Reset Pulsewidth
31.5 ATmega168A Typical Characteristics
31.5.1 Active Supply Current
31.5.2 Idle Supply Current
31.5.3 ATmega168A Supply Current of IO Modules
31.5.4 Power-down Supply Current
31.5.5 Power-save Supply Current
31.5.6 Standby Supply Current
31.5.7 Pin Pull-Up
31.5.8 Pin Driver Strength
31.5.9 Pin Threshold and Hysteresis
31.5.10 BOD Threshold
31.5.11 Internal Oscillator Speed
31.5.12 Current Consumption of Peripheral Units
31.5.13 Current Consumption in Reset and Reset Pulsewidth
31.6 ATmega168PA Typical Characteristics
31.6.1 Active Supply Current
31.6.2 Idle Supply Current
31.6.3 ATmega168PA Supply Current of IO Modules
31.6.4 Power-down Supply Current
31.6.5 Power-save Supply Current
31.6.6 Standby Supply Current
31.6.7 Pin Pull-Up
31.6.8 Pin Driver Strength
31.6.9 Pin Threshold and Hysteresis
31.6.10 BOD Threshold
31.6.11 Internal Oscillator Speed
31.6.12 Current Consumption of Peripheral Units
31.6.13 Current Consumption in Reset and Reset Pulsewidth
31.7 ATmega328 Typical Characteristics
31.7.1 Active Supply Current
31.7.2 Idle Supply Current
31.7.3 ATmega328 Supply Current of IO Modules
31.7.4 Power-down Supply Current
31.7.5 Power-save Supply Current
31.7.6 Standby Supply Current
31.7.7 Pin Pull-Up
31.7.8 Pin Driver Strength
31.7.9 Pin Threshold and Hysteresis
31.7.10 BOD Threshold
31.7.11 Internal Oscillator Speed
31.7.12 Current Consumption of Peripheral Units
31.7.13 Current Consumption in Reset and Reset Pulsewidth
31.8 ATmega328P Typical Characteristics
31.8.1 Active Supply Current
31.8.2 Idle Supply Current
31.8.3 ATmega328P Supply Current of IO Modules
31.8.4 Power-down Supply Current
31.8.5 Power-save Supply Current
31.8.6 Standby Supply Current
31.8.7 Pin Pull-Up
31.8.8 Pin Driver Strength
31.8.9 Pin Threshold and Hysteresis
31.8.10 BOD Threshold
31.8.11 Internal Oscillator Speed
31.8.12 Current Consumption of Peripheral Units
31.8.13 Current Consumption in Reset and Reset Pulsewidth
32. ATmega48PA Typical Characteristics – (TA = -40°C to 105°C)
32.1 Active Supply Current
32.2 Idle Supply Current
32.3 Power-down Supply Current
32.4 Standby Supply Current
32.5 Pin Pull-Up
32.6 Pin Driver Strength
32.7 Pin Threshold and Hysteresis
32.8 BOD Threshold
32.9 Internal Oscillator Speed
32.10 Current Consumption of Peripheral Units
32.11 Current Consumption in Reset and Reset Pulsewidth
33. ATmega88PA Typical Characteristics – (TA = -40°C to 105°C)
33.1 Active Supply Current
33.2 Idle Supply Current
33.3 Power-down Supply Current
33.4 Power-save Supply Current
33.5 Pin Pull-Up
33.6 Pin Driver Strength
33.7 Pin Threshold and Hysteresis
33.8 BOD Threshold
33.9 Internal Oscillator Speed
33.10 Current Consumption of Peripheral Units
33.11 Current Consumption in Reset and Reset Pulsewidth
34. ATmega168PA Typical Characteristics – (TA = -40°C to 105°C)
34.1 Active Supply Current
34.2 Idle Supply Current
34.3 Power-down Supply Current
34.4 Power-save Supply Current
34.5 Standby Supply Current
34.6 Pin Pull-Up
34.7 Pin Driver Strength
34.8 Pin Threshold and Hysteresis
34.9 BOD Threshold
34.10 Internal Oscillator Speed
34.11 Current Consumption of Peripheral Units
34.12 Current Consumption in Reset and Reset Pulsewidth
35. ATmega328P Typical Characteristics – (TA = -40°C to 105°C)
35.1 ATmega328P Active Supply Current
35.2 Idle Supply Current
35.3 Power-down Supply Current
35.4 Power-save Supply Current
35.5 Standby Supply Current
35.6 Pin Pull-Up
35.7 Pin Driver Strength
35.8 Pin Threshold and Hysteresis
35.9 BOD Threshold
35.10 Internal Oscillator Speed
35.11 Current Consumption of Peripheral Units
35.12 Current Consumption in Reset and Reset Pulsewidth
36. Register Summary
37. Instruction Set Summary
38. Ordering Information
38.1 ATmega48A
38.2 ATmega48PA
38.3 ATmega88A
38.4 ATmega88PA
38.5 ATmega168A
38.6 ATmega168PA
38.7 ATmega328
38.8 ATmega328P
39. Packaging Information
39.1 32A
39.2 32CC1
39.3 28M1
39.4 32M1-A
39.5 28P3
40. Errata
40.1 Errata ATmega48A
40.1.1 Rev. D
40.2 Errata ATmega48PA
40.2.1 Rev. A
40.2.2 Rev. D
40.3 Errata ATmega88A
40.3.1 Rev. F
40.4 Errata ATmega88PA
40.4.1 Rev. F
40.4.2 Rev. A
40.5 Errata ATmega168A
40.5.1 Rev. E
40.6 Errata ATmega168PA
40.6.1 Rev E
40.7 Errata ATmega328
40.7.1 Rev D
40.7.2 Rev C
40.7.3 Rev B
40.7.4 Rev A
40.8 Errata ATmega328P
40.8.1 Rev D
40.8.2 Rev C
40.8.3 Rev B
40.8.4 Rev A
41. Datasheet Revision History
41.1 Rev. 8271I – 10/2014
41.2 Rev. 8271H – 08/2014
41.3 Rev. 8271G – 02/2013
41.4 Rev. 8271F – 08/2012
41.5 Rev. 8271E – 07/2012
41.6 Rev. 8271D – 05/11
41.7 Rev. 8271C – 08/10
41.8 Rev. 8271B – 04/10
41.9 Rev. 8271A – 12/09
ATmega48A/PA/88A/PA/168A/PA/328/P
ATMEL 8-BIT MICROCONTROLLER WITH 4/8/16/32KBYTES
IN-SYSTEM PROGRAMMABLE FLASH
DATASHEET
Features
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture
131 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
̶ Up to 20 MIPS Throughput at 20MHz
̶ On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
4/8/16/32KBytes of In-System Self-Programmable Flash program memory
256/512/512/1KBytes EEPROM
512/1K/1K/2KBytes Internal SRAM
̶ Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
̶ Data retention: 20 years at 85C/100 years at 25C(1)
̶ Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
̶ Programming Lock for Software Security
Atmel® QTouch® library support
̶ Capacitive touch buttons, sliders and wheels
̶ QTouch and QMatrix® acquisition
̶ Up to 64 sense channels
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
̶ One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Six PWM Channels
8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
6-channel 10-bit ADC in PDIP Package
Temperature Measurement
̶ Programmable Serial USART
̶ Master/Slave SPI Serial Interface
̶ Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
̶ Programmable Watchdog Timer with Separate On-chip Oscillator
̶ On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
Special Microcontroller Features
̶ Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
̶ External and Internal Interrupt Sources
̶ Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
23 Programmable I/O Lines
28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
1.8 - 5.5V
Temperature Range:
-40C to 85C
Speed Grade:
0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25C
̶ Active Mode: 0.2mA
̶ Power-down Mode: 0.1µA
̶ Power-save Mode: 0.75µA (Including 32kHz RTC)
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
2
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̶
̶
̶
̶
̶
1.
Pin Configurations
Figure 1-1.
Pinout ATmega48A/PA/88A/PA/168A/PA/328/P
32 TQFP Top View
28 PDIP
I
/
)
3
1
T
N
C
P
L
C
S
5
C
D
A
/
(
I
)
4
1
T
N
C
P
T
E
S
E
R
/
(
I
)
7
1
T
N
C
P
D
X
T
(
/
I
)
6
1
T
N
C
P
D
X
R
/
(
I
/
)
2
1
T
N
C
P
A
D
S
4
C
D
A
/
(
I
)
1
1
T
N
C
P
3
C
D
A
/
(
I
)
0
1
T
N
C
P
2
C
D
A
/
(
1
D
P
0
D
P
6
C
P
5
C
P
4
C
P
3
C
P
2
C
P
I
)
8
1
T
N
C
P
0
T
N
/
I
(
2
D
P
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
1
2
3
4
5
6
7
8
2
3
1
3
0
3
9
2
8
2
7
2
6
2
5
2
0
9 1
1
1
2
1
3
1
4
1
5
1
6
1
24
23
22
21
20
19
18
17
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
5
D
P
6
D
P
7
D
P
I
/
)
1
N
A
3
2
T
N
C
P
I
(
/
)
1
T
B
0
C
O
1
2
T
N
C
P
I
/
(
I
/
)
0
N
A
A
0
C
O
2
2
T
N
C
P
I
/
(
4
B
P
)
I
/
O
S
M
4
T
N
C
P
I
(
1
B
P
)
2
B
P
)
/
A
1
C
O
1
T
N
C
P
I
(
/
B
1
C
O
S
S
2
T
N
C
P
I
/
(
0
B
P
)
1
P
C
I
/
/
O
K
L
C
0
T
N
C
P
I
(
3
B
P
)
I
/
S
O
M
A
2
C
O
3
T
N
C
P
I
/
(
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
28 MLF Top View
32 MLF Top View
I
/
)
3
1
T
N
C
P
L
C
S
5
C
D
A
/
I
)
4
1
T
N
C
P
T
E
S
E
R
/
I
)
6
1
T
N
C
P
D
X
R
/
I
/
)
2
1
T
N
C
P
A
D
S
4
C
D
A
/
I
)
1
1
T
N
C
P
3
C
D
A
/
(
0
D
P
(
6
C
P
(
5
C
P
(
4
C
P
(
3
C
P
I
)
8
1
T
N
C
P
0
T
N
/
I
(
2
D
P
I
)
7
1
T
N
C
P
D
X
T
(
/
1
D
P
I
/
)
3
1
T
N
C
P
L
C
S
5
C
D
A
/
I
)
4
1
T
N
C
P
T
E
S
E
R
/
I
)
6
1
T
N
C
P
D
X
R
/
I
/
)
2
1
T
N
C
P
A
D
S
4
C
D
A
/
I
)
1
1
T
N
C
P
3
C
D
A
/
I
)
0
1
T
N
C
P
2
C
D
A
/
(
0
D
P
(
6
C
P
(
5
C
P
(
4
C
P
(
3
C
P
(
2
C
P
I
)
8
1
T
N
C
P
0
T
N
/
I
(
2
D
P
I
)
7
1
T
N
C
P
D
X
T
(
/
1
D
P
8
2
7
2
6
2
5
2
4
2
3
2
2
2
2
3
1
3
0
3
9
2
8
2
7
2
6
2
5
2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
1
2
3
4
5
6
7
21
20
19
18
17
16
15
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
1
2
3
4
5
6
7
8
0
8 9 1
1
1
2
1
3
1
4
1
24
23
22
21
20
19
18
17
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
NOTE: Bottom pad should be soldered to ground.
6
D
P
7
D
P
I
/
)
1
N
A
3
2
T
N
C
P
I
(
I
/
)
0
N
A
A
0
C
O
2
2
T
N
C
P
I
/
(
0
B
P
)
1
P
C
I
/
/
O
K
L
C
0
T
N
C
P
I
(
1
B
P
2
B
P
)
/
A
1
C
O
1
T
N
C
P
I
(
)
/
B
1
C
O
S
S
2
T
N
C
P
I
/
(
4
B
P
)
I
/
O
S
M
4
T
N
C
P
I
(
3
B
P
)
I
/
S
O
M
A
2
C
O
3
T
N
C
P
I
/
(
NOTE: Bottom pad should be soldered to ground.
5
D
P
/
)
1
T
B
0
C
O
1
2
T
N
C
P
I
/
(
Table 1-1.
32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA
1
PD2
PD3
GND
VDD
PB6
PB7
2
PD1
PD4
GND
VDD
PD6
PD5
3
PC6
PD0
PB0
PD7
4
PC4
PC5
PB2
PB1
5
PC2
PC3
ADC7
AREF
AVDD
PB3
A
B
C
D
E
F
0
9 1
1
1
2
1
3
1
4
1
5
1
6
1
6
D
P
I
/
)
0
N
A
A
0
C
O
2
2
T
N
C
P
I
/
(
4
B
P
)
I
/
O
S
M
4
T
N
C
P
I
(
3
B
P
)
I
/
S
O
M
A
2
C
O
3
T
N
C
P
I
/
(
7
D
P
I
/
)
1
N
A
3
2
T
N
C
P
I
(
0
B
P
)
1
P
C
I
/
/
O
K
L
C
0
T
N
C
P
I
1
B
P
2
B
P
)
/
A
1
C
O
1
T
N
C
P
I
(
)
/
B
1
C
O
S
S
2
T
N
C
P
I
/
(
(
6
PC1
PC0
GND
ADC6
PB5
PB4
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
3
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3
1.1.4
1.1.5
1.1.6
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier
and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the
Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 82 and ”System
Clock and Clock Options” on page 27.
Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than
the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is
given in Table 29-11 on page 305. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 85.|
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 88.
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
4
1.1.7 AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to
VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
Note that PC6...4 use digital supply voltage, VCC.
1.1.8 AREF
AREF is the analog reference pin for the A/D Converter.
1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
5
2.
Overview
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
D
N
G
C
C
V
Power
Supervision
POR / BOD &
RESET
debugWIRE
PROGRAM
LOGIC
Flash
SRAM
CPU
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
8bit T/C 0
16bit T/C 1
A/D Conv.
2
S
U
B
A
T
A
D
8bit T/C 2
Analog
Comp.
Internal
Bandgap
6
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
AVCC
AREF
GND
RESET
XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
6
The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-System
Programmable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes
SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial
Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a
programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is
running while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
Atmel® offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into
AVR® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for
unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop
and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional
non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program
can use any interface to download the application program in the Application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-
While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit
Emulators, and Evaluation kits.
2.2
Comparison Between Processors
The ATmega48A/PA/88A/PA/168A/PA/328/P differ only in memory sizes, boot loader support, and interrupt
vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices.
Memory Size Summary
Table 2-1.
Device
ATmega48A
ATmega48PA
ATmega88A
ATmega88PA
ATmega168A
ATmega168PA
ATmega328
ATmega328P
Flash
4KBytes
4KBytes
8KBytes
8KBytes
16KBytes
16KBytes
32KBytes
32KBytes
EEPROM
256Bytes
256Bytes
512Bytes
512Bytes
512Bytes
512Bytes
1KBytes
1KBytes
RAM
512Bytes
512Bytes
1KBytes
1KBytes
1KBytes
1KBytes
2KBytes
2KBytes
Interrupt Vector Size
1 instruction word/vector
1 instruction word/vector
1 instruction word/vector
1 instruction word/vector
2 instruction words/vector
2 instruction words/vector
2 instruction words/vector
2 instruction words/vector
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
7
3.
4.
5.
6.
ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism.
There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega
48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can
execute from the entire Flash
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note:
1.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85°C or 100 years at 25°C.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware that not
all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler
dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
Capacitive Touch Sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most
Atmel AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel QMatrix®
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing APIs to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch
Library User Guide - also available for download from Atmel website.
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271I-AVR- ATmega-Datasheet_10/2014
8
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