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STM32F10xxx闪存编程参考手册（英文）.pdf
Table 1. Applicable products
1 Overview
1.1 Features
1.2 Flash module organization
Table 2. Flash module organization (low-density devices)
Table 3. Flash module organization (medium-density devices)
Table 4. Flash module organization (high-density devices)
Table 5. Flash module organization (connectivity line devices)
2 Reading/programming the embedded Flash memory
2.1 Introduction
2.2 Read operation
2.2.1 Instruction fetch
2.2.2 D-Code interface
2.2.3 Flash access controller
2.3 Flash program and erase controller (FPEC)
2.3.1 Key values
2.3.2 Unlocking the Flash memory
2.3.3 Main Flash memory programming
Figure 1. Programming procedure
2.3.4 Flash memory erase
Figure 2. Flash memory Page Erase procedure
Figure 3. Flash memory Mass Erase procedure
2.3.5 Option byte programming
2.4 Protections
2.4.1 Read protection
Table 6. Flash memory protection status
2.4.2 Write protection
2.4.3 Option byte block write protection
2.5 Option byte description
Table 7. Option byte format
Table 8. Option byte organization
Table 9. Description of the option bytes
Note: Only bits [16:18] are used, bits [23:19]: 0x1F are not used.
3 Register descriptions
Table 10. Abbreviations
3.1 Flash access control register (FLASH_ACR)
3.2 FPEC key register (FLASH_KEYR)
3.3 Flash OPTKEY register (FLASH_OPTKEYR)
3.4 Flash status register (FLASH_SR)
Note: EOP is asserted at the end of each successful program or erase operation
Note: The STRT bit in the FLASH_CR register should be reset before starting a programming operation.
3.5 Flash control register (FLASH_CR)
3.6 Flash address register (FLASH_AR)
Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is set.
3.7 Option byte register (FLASH_OBR)
Note: This bit is read-only.
Note: This bit is read-only.
3.8 Write protection register (FLASH_WRPR)
Note: These bits are read-only.
3.9 Flash register map
Table 11. Flash interface - register map and reset values
4 Revision history
Table 12. Document revision history
PM0075
Programming manual
STM32F10xxx Flash memory microcontrollers
Introduction
This programming manual describes how to program the Flash memory of STM32F101xx,
STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx microcontrollers. For
convenience, these will be referred to as STM32F10xxx in the rest of this document unless
otherwise specified.
The STM32F10xxx embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out Flash memory operations (Program/Erase).
Program/Erase operations can be performed over the whole product voltage range.
Read/Write protections and option bytes are also implemented.
Table 1 lists the microcontrollers and evaluation tool concerned by this programming
manual.
Table 1.
Applicable products
Type
Microcontrollers
Applicable products
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and
STM32F107xx microcontrollers
Evaluation tool
STM3210C-EVAL evaluation board
August 2012
Doc ID 17863 Rev 2
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Contents
Contents
PM0075
1
2
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reading/programming the embedded Flash memory . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1
2.2.2
D-Code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3
Flash access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash program and erase controller (FPEC) . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1
Key values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlocking the Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2
Main Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3
2.3.4
Flash memory erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5
Option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.1
Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.2
2.4.3
Option byte block write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
2.3
2.5
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . 23
3.1
FPEC key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2
Flash OPTKEY register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . . . 24
3.3
3.4
Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5
3.6
Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7
Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8 Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9
Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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PM0075
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash memory protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 17863 Rev 2
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List of figures
List of figures
PM0075
Figure 1.
Figure 2.
Figure 3.
Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory Page Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Flash memory Mass Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4/31
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PM0075
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
The Cortex-M3 core integrates two debug ports:
–
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols please refer to the Cortex M3 Technical
Reference Manual
–
Word: data/instruction of 32-bit length
Half word: data/instruction of 16-bit length
Byte: data of 8-bit length
FPEC (Flash memory program/erase controller): write operations to the main memory
and the information block are managed by an embedded Flash program/erase
controller (FPEC).
IAP (in-application programming): IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the boot loader while the
device is mounted on the user application board.
I-Code: this bus connects the Instruction bus of the Cortex-M3 core to the Flash
instruction interface. Prefetch is performed on this bus.
D-Code: this bus connects the D-Code bus (literal load and debug access) of the
Cortex-M3 to the Flash Data Interface.
Option bytes: product configuration bits stored in the Flash memory
OBL: option byte loader.
AHB: advanced high-performance bus.
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Overview
1
Overview
1.1
Features
PM0075
up to 512 Kbytes of Flash memory
Memory organization:
– Main memory block:
4 Kbits × 64 bits for low-density devices
16 Kbits × 64 bits for medium-density devices
64 Kbits × 64 bits for high-density devices
32 Kbits × 64 bits for connectivity line devices
Information block:
2306 × 64 bits for connectivity line devices
258 × 64 bits for other devices
–
Flash memory interface (FLITF) features:
Read interface with prefetch buffer (2 × 64-bit words)
Option byte Loader
Flash Program / Erase operation
Read / Write protection
Low-power mode
1.2
Flash module organization
The memory organization is based on a main memory block containing 32 pages of 1 Kbyte
(for low-density devices), 128 pages of 1 Kbyte (for medium-density devices), 128 pages of
2 Kbyte (for connectivity line devices) or 256 pages of 2 Kbyte (for high-density devices),
and an information block as shown in Table 3 and Table 4.
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PM0075
Overview
Table 2.
Flash module organization (low-density devices)
Block
Main memory
Information block
Flash memory
interface
registers
Name
Page 0
Page 1
Page 2
Page 3
Page 4
.
.
.
Base addresses
Size (bytes)
0x0800 0000 - 0x0800 03FF
0x0800 0400 - 0x0800 07FF
0x0800 0800 - 0x0800 0BFF
0x0800 0C00 - 0x0800 0FFF
0x0800 1000 - 0x0800 13FF
.
.
.
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
.
.
.
Page 31
0x0800 7C00 - 0x0800 7FFF
1 Kbyte
System memory
0x1FFF F000 - 0x1FFF F7FF
2 Kbytes
0x1FFF F800 - 0x1FFF F80F
16
0x4002 2000 - 0x4002 2003
Option Bytes
FLASH_ACR
FLASH_KEYR
0x4002 2004 - 0x4002 2007
FLASH_OPTKEYR
0x4002 2008 - 0x4002 200B
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
FLASH_OBR
0x4002 201C - 0x4002 201F
FLASH_WRPR
0x4002 2020 - 0x4002 2023
4
4
4
4
4
4
4
4
4
Table 3.
Flash module organization (medium-density devices)
Block
Main memory
Information block
Name
Page 0
Page 1
Page 2
Page 3
Page 4
.
.
.
Base addresses
Size (bytes)
0x0800 0000 - 0x0800 03FF
0x0800 0400 - 0x0800 07FF
0x0800 0800 - 0x0800 0BFF
0x0800 0C00 - 0x0800 0FFF
0x0800 1000 - 0x0800 13FF
.
.
.
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
.
.
.
Page 127
0x0801 FC00 - 0x0801 FFFF
1 Kbyte
System memory
0x1FFF F000 - 0x1FFF F7FF
2 Kbytes
Option Bytes
0x1FFF F800 - 0x1FFF F80F
16
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Overview
PM0075
Table 3.
Flash module organization (medium-density devices) (continued)
Block
Name
FLASH_ACR
FLASH_KEYR
Base addresses
Size (bytes)
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
Flash memory
interface
registers
FLASH_OPTKEYR
0x4002 2008 - 0x4002 200B
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
FLASH_OBR
0x4002 201C - 0x4002 201F
FLASH_WRPR
0x4002 2020 - 0x4002 2023
Table 4.
Flash module organization (high-density devices)
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Block
Main memory
Information block
Flash memory
interface
registers
Name
Page 0
Page 1
Page 2
Page 3
.
.
.
Base addresses
Size (bytes)
0x0800 0000 - 0x0800 07FF
2 Kbytes
0x0800 0800 - 0x0800 0FFF
2 Kbytes
0x0800 1000 - 0x0800 17FF
2 Kbytes
0x0800 1800 - 0x0800 1FFF
2 Kbytes
.
.
.
.
.
.
Page 255
0x0807 F800 - 0x0807 FFFF
2 Kbytes
System memory
0x1FFF F000 - 0x1FFF F7FF
2 Kbytes
Option Bytes
FLASH_ACR
0x1FFF F800 - 0x1FFF F80F
16
0x4002 2000 - 0x4002 2003
FLASH_KEYR
0x4002 2004 - 0x4002 2007
FLASH_OPTKEYR
0x4002 2008 - 0x4002 200B
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
FLASH_OBR
0x4002 201C - 0x4002 201F
FLASH_WRPR
0x4002 2020 - 0x4002 2023
8/31
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