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DS1302_EN(DS1302_datasheet).pdf

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    DS1302 Trickle-Charge Timekeeping Chip www.maxim-ic.com FEATURES § Real-Time Clock Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 § 31 x 8 RAM for Scratchpad Data Storage § Serial I/O for Minimum Pin Count § 2.0V to 5.5V Full Operation § Uses Less than 300nA at 2.0V § Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock or RAM Data § 8-Pin DIP or Optional 8-Pin SO for Surface Mount § Simple 3-Wire Interface § TTL-Compatible (VCC = 5V) § Optional Industrial Temperature Range: -40°C to +85°C § DS1202 Compatible § Underwriters Laboratory (UL) Recognized ORDERING INFORMATION PART DS1302 DS1302N DS1302S DS1302SN DS1302Z DS1302Z+ DS1302ZN DS1302ZN+ DS1302S-16 DS1302SN-16 TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 0°C to +70°C -40°C to +85°C TOP MARK PIN-PACKAGE DS1302 8 PDIP DS1302* 8 PDIP DS1302S 8 SO (200 mils) DS1302S* 8 SO DS1302Z 8 SO (150 mils) + DS1302Z 8 SO (150 mils) DS1302ZN 8 SO 8 SO + DS1302ZN 16 SO (300 mils) DS1302S16 16 SO (300 mils) DS1302SN16 PIN CONFIGURATIONS TOP VIEW VCC2 X1 X2 GND 1 2 3 4 2 0 3 1 S D 8 7 6 5 VCC1 SCLK I/O CE DIP (300 mils) VCC2 X1 X2 GND 1 2 3 4 / Z S 2 0 3 1 S D 8 7 6 5 VCC1 SCLK I/O CE SO (200 mils/150 mils) VCC2 N.C X1 N.C. X2 N.C. N.C. GND S 2 0 3 1 S D 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 VCC1 N.C. SCLK N.C. I/O N.C. N.C. CE SO (300 mils) *An N in the lower right-hand corner of the top mark denotes an industrial part. + = lead-free device. DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 13 REV: 072204
    DS1302 Trickle-Charge Timekeeping Chip Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1mW. The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory. OPERATION Figure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock, and RAM. TYPICAL OPERATING CIRCUIT Figure 1. Block Diagram CE I/O SCLK DS1302 V CC2 X1 X2 V CC1 GND VCC CPU VCC X1 X2 OSCILLATOR COUNTDOWN AND CHAIN 1Hz REAL-TIME CLOCK 31 x 8 RAM POWER CONTROL DS1302 INPUT SHIFT REGISTERS COMMAND AND CONTROL LOGIC v CC1 v CC 2 GND I/O SCLK CE 2 of 13
    400 350 ) 300 ICC1T vs. VCC1T TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3V, TA = +25°C, unless otherwise noted.) PIN DESCRIPTION A n ( T N E R R U C Y L P P U S VCC1 (V) 150 100 250 200 5.0 2.0 3.0 4.0 DS1302 Trickle-Charge Timekeeping Chip 30 25 20 15 10 5 2.0 ICC2T vs. VCC2T 3.0 VCC2 (V) 4.0 5.0 ) A u ( T N E R R U C Y L P P U S 8 1 2 3 4 5 6 7 8 PIN 16 NAME FUNCTION 1 3 5 8 9 12 14 16 VCC2 X1 X2 GND CE I/O SCLK VCC1 Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302. Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Ground Input. CE signal must be asserted high during a read or a write. This pin has an internal 40kW (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40kW (typ) pulldown resistor to ground. Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kW (typ) pulldown resistor to ground. Low-Power Operation in Single Supply and Battery-Operated Systems and Low- Power Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery. 2, 4, 6, 7, 10, 11, 13, 15 — N.C. No Connection 3 of 13
    DS1302 Trickle-Charge Timekeeping Chip OSCILLATOR CIRCUIT The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 2 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 3 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information. Table 1. Crystal Specifications* PARAMETER SYMBOL MIN Nominal Frequency Series Resistance Load Capacitance fO ESR CL TYP 32.768 6 MAX 45 UNITS kHz kW pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. CRYSTAL RTC CHAIN C L 1 C L 2 X1 X2 RTC REGISTERS COUNTDOWN Figure 2. Oscillator Circuit Showing Internal Bias Network Figure 3. Typical PC Board Layout for Crystal LOCAL GROUND PLANE (LAYER 2) CRYSTAL X1 X2 NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT- HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE. GND 4 of 13
    DS1302 Trickle-Charge Timekeeping Chip COMMAND BYTE Figure 4 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). Figure 4. Address/Command Byte 7 1 6 RAM C K 5 A4 4 A3 3 A2 2 A1 1 A0 0 RD W R CE AND CLOCK CONTROL Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 5 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state. DATA INPUT Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. DATA OUTPUT Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri- stated upon each rising edge of SCLK. Data is output starting with bit 0. BURST MODE Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. CLOCK/CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 2 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. 5 of 13
    DS1302 Trickle-Charge Timekeeping Chip The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed. CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined. WRITE-PROTECT BIT Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device. TRICKLE-CHARGE REGISTER This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between VCC2 and VCC1. The resistor selected by the resistor select (RS) bits is as follows: RS BITS RESISTOR 00 01 10 11 None R1 R2 R3 TYPICAL VALUE None 2kW 4kW 8kW If RS is 00, the trickle charger is disabled independently of TCS. Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would therefore be calculated as follows: IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kW ≈ 2.2mA As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current decreases. 6 of 13
    DS1302 Trickle-Charge Timekeeping Chip CLOCK/CALENDAR BURST MODE The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0. If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. RAM The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0. REGISTER SUMMARY A register data format summary is shown in Table 2. CRYSTAL SELECTION A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6pF. For more information on crystal selection and crystal layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. Figure 5. Data Transfer Summary NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SINGLE-BYTE WRITE SINGLE-BYTE READ A1 A2 A3 A4 R/C R/W A0 A1 R/W A0 D0 A2 A3 A4 R/C 1 SCLK CE 1 CE SCLK I/O I/O 7 of 13
    DS1302 Trickle-Charge Timekeeping Chip BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Seconds Minutes Hour Date Month Year Day 0 RS 0 RS 0 0 DS 0 DS RANGE 00–59 00–59 1–12/0–23 1–31 1–12 1–7 00–99 — — 00-FFh 00-FFh 00-FFh . . . 00-FFh CH Table 2. Register Address/Definition RTC READ WRITE BIT 7 BIT 6 BIT 5 81h 83h 85h 87h 89h 8Bh 8Dh 8Fh 91h 10 Date 0 0 10 Year 0 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 10 Seconds 10 Minutes AM/PM Hour 10 WP TCS 0 0 0 0 0 0 0 0 12/24 0 0 10 Month TCS TCS TCS CLOCK BURST BEh BFh RAM C1h C3h C5h . . . C0h C2h C4h . . . FCh FDh RAM BURST FEh FFh Figure 6. Programmable Trickle Charger TRICKLE CHARGE REGISTER (90h write, 91h read) Bit 7 TCS3 Bit 6 TCS2 Bit 5 TCS1 Bit 4 TCS0 Bit 3 DS1 Bit 2 DS0 Bit 1 Bit 0 ROUT1 ROUT0 TCS0-3 = TRICKLE CHARGER SELECT DS0-1 = DIODE SELECT ROUT0-1 = RESISTOR SELECT 1 0F 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER 1 OF 2 SELECT 1 OF 3 SELECT VCC2 VCC1 R1 2K W R2 4k W R3 8k W 8 of 13
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