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SX1302 datasheet(DS_SX1302_V1.0).pdf
Table of Contents
List of Figures
List of Tables
1. Introduction
1.1 RF Front End Interface
1.2 Power Distribution
1.3 Clocking
1.4 Detection Engine and Modems
1.5 Digital Interface and Control
1.6 Application Programming Interface
1.7 Application Information
2. Pin Connections
2.1 Pinout
2.2 Package View
3. Specifications
3.1 ESD Notice
3.2 Absolute Minimum and Maximum Ratings
3.3 Operating Range
3.4 Electrical Specifications
3.5 Digital I/O Specifications
3.6 Example Reference Design Performance
4. RF Front End Interface
5. Power Distribution
6. Clocking
7. Detection Engine - Modems
8. Digital Interface and Control
8.1 Host SPI Interface
8.1.1 HOST SPI Timings
8.1.2 SPI Timings
9. Application Programming Interface
9.1 Globally Unique EUI
10. Application Information
10.1 Geographical Designs
10.2 Reference Block Diagram
10.3 Reference Design Layout
11. Packaging Information
11.1 Package Outline Drawing
11.2 Package Marking
11.3 Land Pattern
11.4 Reflow Profiles
11.5 Tape and Reel Specification
11.6 Thermal Impedance
Glossary
SX1302
LoRa Gateway Baseband
Transceiver
Figure A: Block Diagram
General Description
The SX1302 is a new generation of baseband LoRa® chip for
gateways. It excels in reducing current consumption,
simplifies the thermal design of gateways, and reduces the
Bill Of Materials costs, yet it is capable of handling a higher
amount of traffic than preceding devices.
The high-speed baseband digital engines are clocked from
a single 32 MHz clock source, and the chip embeds the
capability to support SF5 and SF6 unlike previous
generations. To absorb the additional traffic that the radio
will be able to detect, more modems are now collaborating.
8 of them have been added to specifically handle the
high-speed SF5 and SF6 packets, whilst the 8 others are still
taking care of the SF7-SF12 traffic. The architecture has
been reworked to reduce power consumption very
significantly; it makes it easier to embed the SX1302 in
highly-integrated environments where power dissipation
might be a challenge.
The SX1302 is also serialized in production, with a globally
unique 64-bit number.
Key Features
•
•
LoRaWAN, Class A/B/C, all regions
125 kHz LoRa reception with:
•
•
•
125 /250 / 500 kHz LoRa® demodulator
(G)FSK demodulator
8 x 8 channels LoRa® packet detectors
8 x SF5-SF12 LoRa® demodulators
8 x SF5-SF10 LoRa® demodulators
•
•
• Direct interface to Semtech transceivers
•
•
SX1255, SX1257 and SX1250
Single 32 MHz clock
Ordering Information
Part Number
Delivery
Order Quantity
SX1302IMLTRT
Tape and Reel
3000
QFN68 Package, operating range from -40 to +85°C
Pb-free, Halogen free, RoHS/WEEE compliant product
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
1 of 31
Revision History
Version
ECO
Date
Modifications
Rev 1.0
ECO-047283
June 2019
First Release
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
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Table of Contents
General Description.............................................................................................................................................1
Key Features...........................................................................................................................................................1
Ordering Information .........................................................................................................................................1
Revision History ....................................................................................................................................................2
List of Figures ........................................................................................................................................................5
List of Tables .........................................................................................................................................................6
1. Introduction.......................................................................................................................................................7
1.1 RF Front End Interface ......................................................................................................................7
1.2 Power Distribution .............................................................................................................................7
1.3 Clocking .................................................................................................................................................7
1.4 Detection Engine and Modems ....................................................................................................7
1.5 Digital Interface and Control ..........................................................................................................7
1.6 Application Programming Interface ............................................................................................7
1.7 Application Information ...................................................................................................................7
2. Pin Connections ...............................................................................................................................................8
2.1 Pinout .....................................................................................................................................................8
2.2 Package View .................................................................................................................................... 11
3. Specifications ................................................................................................................................................. 12
3.1 ESD Notice .......................................................................................................................................... 12
3.2 Absolute Minimum and Maximum Ratings ........................................................................... 13
3.3 Operating Range .............................................................................................................................. 13
3.4 Electrical Specifications ................................................................................................................. 13
3.5 Digital I/O Specifications ............................................................................................................... 14
3.6 Example Reference Design Performance ............................................................................... 14
4. RF Front End Interface................................................................................................................................. 16
5. Power Distribution ....................................................................................................................................... 18
6. Clocking ........................................................................................................................................................... 19
7. Detection Engine - Modems..................................................................................................................... 20
8. Digital Interface and Control.................................................................................................................... 21
8.1 Host SPI Interface ............................................................................................................................. 21
8.1.1 HOST SPI Timings ................................................................................................................ 21
8.1.2 SPI Timings............................................................................................................................. 22
9. Application Programming Interface...................................................................................................... 23
9.1 Globally Unique EUI ........................................................................................................................ 23
10. Application Information .......................................................................................................................... 24
10.1 Geographical Designs ................................................................................................................. 24
10.2 Reference Block Diagram ........................................................................................................... 24
10.3 Reference Design Layout ........................................................................................................... 25
11. Packaging Information............................................................................................................................. 26
11.1 Package Outline Drawing .......................................................................................................... 26
11.2 Package Marking ........................................................................................................................... 27
11.3 Land Pattern ................................................................................................................................... 27
11.4 Reflow Profiles ................................................................................................................................ 28
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
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11.5 Tape and Reel Specification ...................................................................................................... 28
11.6 Thermal Impedance ..................................................................................................................... 28
Glossary ................................................................................................................................................................ 29
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
4 of 31
List of Figures
Figure 2-1: Pin Locations, Top View........................................................................................................... 11
Figure 4-1: Receive Interconnection ......................................................................................................... 16
Figure 4-2: Transmit Interconnection ....................................................................................................... 16
Figure 8-1: SPI Timing Diagram................................................................................................................... 21
Figure 10-1: Application Design Block Diagram ................................................................................... 24
Figure 10-2: Reference Design PCB Layout............................................................................................. 25
Figure 11-1: QFN 7x7 Package Outline Drawing................................................................................... 26
Figure 11-2: SX1302 Package Marking ..................................................................................................... 27
Figure 11-3: QFN 7x7mm Land Pattern.................................................................................................... 27
Figure 11-4: Tape and Reel Specification ................................................................................................ 28
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
5 of 31
List of Tables
Table 2-1: Pinout.................................................................................................................................................. 8
Table 3-1: ESD and Latch-Up Notice.......................................................................................................... 12
Table 3-2: Minimum and Maximum Ratings .......................................................................................... 13
Table 3-3: Operating Range.......................................................................................................................... 13
Table 3-4: Performances ................................................................................................................................ 13
Table 3-5: Digital I/O Specifications........................................................................................................... 14
Table 3-6: Reference Design Performance.............................................................................................. 14
Table 4-1: Semtech RF Front-end Summary........................................................................................... 17
Table 5-1: Current Consumption................................................................................................................ 18
Table 8-1: SPI Timing Requirements.......................................................................................................... 22
Table 11-1: Tape and Reel Specification .................................................................................................. 28
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
6 of 31
1. Introduction
The SX1302 is a digital baseband engine, capable of detecting and demodulating large amounts of LoRa® packets expected
in the IOT networks.
1.1 RF Front End Interface
The SX1302 is intended to be used with various RF Front End chips (RF to IQ), such as Semtech’s SX1255/57. Details on the
interface and compatibility is available on Section 4. "RF Front End Interface" on page 16 .
1.2 Power Distribution
The SX1302 is supplied on two different domains, 1.2 V for the core of the baseband processing, and 3 to 3.6V for the host
and RF interface. For details, see Section 5. "Power Distribution" on page 18 .
1.3 Clocking
SX1302 clocking is achieved from a single clock source. Details are found in Section 6. "Clocking" on page 19 .
1.4 Detection Engine and Modems
The SX1302 can detect at any time, any packet in a combination of 8 different spreading factors (SF5 to SF12) and 10
channels, and demodulate up to 16 packets at any time. Details on the modems and their assignment are found in
Section 7. "Detection Engine - Modems" on page 20 .
1.5 Digital Interface and Control
The SPI interface of the SX1302 to its host controller is detailed in Section 8. "Digital Interface and Control" on page 21 .
1.6 Application Programming Interface
An example API is made available as source code with the HAL library and the Packet Forwarder example software. Details
are available in Section 9. "Application Programming Interface" on page 23 .
1.7 Application Information
Semtech has designed, validated, and released multiple reference design with the SX1302. The performance tabulated in
this document is obtained on the said reference design. Details of the Core Cell reference design are posted in Section 10.
"Application Information" on page 24 .
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
7 of 31
2. Pin Connections
2.1 Pinout
Table 2-1: Pinout
Pin
Number
Pin Name
Direction
Description
SX1250
SX1255/57
(0)
GND
HOST_CSN
Power
Input
Ground
External HOST SPI CSN pin
HOST_MISO
Output
External HOST SPI MISO pin
HOST_MOSI
HOST_SCK
VCC_CORE
GND
RESET
PPS
GND
Input
Input
Power
Power
Input
Input
Power
External HOST SPI MOSI pin
External HOST SPI SCK pin
Core supply
Ground
Asynchronous Reset Input
PPS input from GPS
Ground
RADIO_CTRL[0]
Output
Radio A Enable LDO
RADIO_CTRL[1]
Output
Radio A Enable LNA and control switch
RADIO_CTRL[2]
Output
Radio A Enable PA and control switch
RADIO_CTRL[3]
Output
Radio A Reset
NRESET
RESET
VCC_IO
GND
Power
Power
IO supply
Ground
RADIO_CTRL[4]
Output
Radio A PA gain_0
RADIO_CTRL[5]
Output
Radio A PA gain_1
RADIO_B_CSN
Output
Radio B SPI CSN pin
RADIO_B_MOSI
Output
Radio B SPI MOSI pin
SP_VALID
Input
Stream synchronization for FPGA
RADIO_B_SCK
Output
Radio B SPI SCK pin
RADIO_CTRL[6]
Output
Radio B Enable LDO
VCC_CORE
Power
Core supply
NSS
MOSI
SCK
NSS
MOSI
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SX1302
Datasheet
DS.SX1302.W.APP
Rev 1.0
June 2019
www.semtech.com
8 of 31
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