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SDD1327数据手册(SSD1327).pdf
1 GENERAL DESCRIPTION
2 FEATURES
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 DIE PAD FLOORPLAN
6 PIN ARRANGEMENT
7 PIN DESCRIPTIONS
8 FUNCTIONAL BLOCK DESCRIPTIONS
8.1 MCU Interface selection
8.1.1 MCU Parallel 6800-series Interface
8.1.2 MCU Parallel 8080-series Interface
8.1.3 MCU Serial Interface (4-wire SPI)
8.1.4 MCU Serial Interface (3-wire SPI)
8.1.5 MCU I2C Interface
8.1.5.1 I2C-bus Write data
8.1.5.2 Write mode for I2C
8.2 Segment Drivers/Common Drivers
8.3 Oscillator Circuit and Display Time Generator
8.4 Command Decoder and Command Interface
8.5 Reset Circuit
8.6 SEG/COM Driving Block
8.7 Graphic Display Data RAM (GDDRAM)
8.8 Gray Scale Decoder
8.9 Power ON and OFF sequence
8.10 VDD Regulator
9 Command Table
9.1 Data Read / Write
10 COMMAND DESCRIPTIONS
10.1 Fundamental command description
10.1.1 Set Column Address (15h)
10.1.2 Set Row Address (75h)
10.1.3 Set Contrast Current (81h)
10.1.4 NOP (84h ~ 86h)
10.1.5 Set Re-map (A0h)
10.1.6 Set Display Start Line (A1h)
10.1.7 Set Display Offset (A2h)
10.1.8 Set Display Mode (A4h ~ A7h)
10.1.9 Set Multiplex Ratio (A8h)
10.1.10 Function selection A (ABh)
10.1.11 Set Display ON/OFF (AEh / AFh)
10.1.12 Set Phase Length (B1h)
10.1.13 NOP (B2h)
10.1.14 Set Front Clock Divider / Oscillator Frequency (B3h)
10.1.15 Set GPIO (B5h)
10.1.16 Set Second Pre-charge period (B6h)
10.1.17 Set Gray Scale Table (B8h)
10.1.18 Select Default Linear Gray Scale Table (B9h)
10.1.19 NOP (BBh)
10.1.20 Set Pre-charge voltage (BCh)
10.1.21 Set VCOMH Voltage (BEh)
10.1.22 Function selection B (D5h)
10.1.23 Set Command Lock (FDh)
10.2 Graphic Acceleration command description
10.2.1 Horizontal Scroll Setup (26h/27h)
10.2.2 Deactivate Scroll (2Eh)
10.2.3 Activate Scroll (2Fh)
11 MAXIMUM RATINGS
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION EXAMPLES
15 PACKAGE INFORMATION
15.1 SSD1327Z Die Tray Information
15.2 SSD1327UR1 detail dimension
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1327
128 x 128, 16 Gray Scale Dot Matrix
OLED/PLED Segment/Common Driver with Controller
Advance Information
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1327
Copyright © 2008 Solomon Systech Limited
Rev 1.1
P 1/68 Dec 2008
Appendix: IC Revision history of SSD1327 Specification
Change Items
1st release
P.17 Added TR[6:0] on pin description section
P.37, 38 Added notes for commands B1h and B8h on command table
P.54 Updated the DC characteristics table
P.55 Updated the AC characteristics table
P.8, 10 Revise die thickness tolerance from ±25um to ±15um
P.11, 12 Revised the typo of LVSS to VLSS on the table of SSD1327Z Bump Die
Pad Coordinates
P.15, 39, 50 Added command D5h and corresponding information on the
command table and related section
P.49 Added display on and display off sequences
P.62 Added notes (4) and (5) on the application example of SSD1327Z
Change to Advance information
P.7 Added title “VCI and VDD range” for Table 2-1
P.35 Updated section 8.10 VDD regulator
P.37 Revised command table of “Function Selection A (ABh)”
P.49 Revised description of section 10.1.10 Function Selection A (ABh)
P.49, 50 Revised section 10.1.11 Set display ON/OFF
P.59 – 63 Updated the condition of AC characteristics from (VDD - VSS = 2.4V
to 2.6V, VCI = 3.3V) to (VCI - VSS = 1.65V to 3.5V) on Table 13-2 to Table13-6
1.1
P.38 Added a note for command B6h on command table
P.51 Revised the description of command B6h
Version
0.10
0.20
0.30
1.0
Effective Date
30-May-08
04-Sep-08
21-Nov-08
09-Dec-08
23-Dec-08
Solomon Systech
Dec 2008 P 2/68
Rev 1.1
SSD1327
CONTENT
1
2
3
4
5
6
7
8
GENERAL DESCRIPTION ....................................................................................................7
FEATURES................................................................................................................................7
ORDERING INFORMATION ................................................................................................8
BLOCK DIAGRAM..................................................................................................................9
DIE PAD FLOORPLAN.........................................................................................................10
PIN ARRANGEMENT...........................................................................................................13
PIN DESCRIPTIONS .............................................................................................................15
FUNCTIONAL BLOCK DESCRIPTIONS..........................................................................18
8.1 MCU INTERFACE SELECTION...............................................................................................................................18
8.1.1 MCU Parallel 6800-series Interface......................................................................................................18
8.1.2 MCU Parallel 8080-series Interface......................................................................................................19
8.1.3 MCU Serial Interface (4-wire SPI) ........................................................................................................20
8.1.4 MCU Serial Interface (3-wire SPI) ........................................................................................................21
8.1.5 MCU I2C Interface .................................................................................................................................22
8.1.5.1
I2C-bus Write data..................................................................................................................23
8.1.5.2 Write mode for I2C..................................................................................................................23
SEGMENT DRIVERS/COMMON DRIVERS...............................................................................................................25
8.2
OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR......................................................................................28
8.3
COMMAND DECODER AND COMMAND INTERFACE..............................................................................................29
8.4
RESET CIRCUIT....................................................................................................................................................29
8.5
SEG/COM DRIVING BLOCK................................................................................................................................29
8.6
GRAPHIC DISPLAY DATA RAM (GDDRAM)......................................................................................................30
8.7
GRAY SCALE DECODER.......................................................................................................................................33
8.8
8.9
POWER ON AND OFF SEQUENCE .........................................................................................................................34
8.10 VDD REGULATOR .................................................................................................................................................35
COMMAND TABLE ..............................................................................................................36
DATA READ / WRITE ...........................................................................................................................................41
10 COMMAND DESCRIPTIONS..............................................................................................42
10.1 FUNDAMENTAL COMMAND DESCRIPTION ............................................................................................................42
Set Column Address (15h)...................................................................................................................42
10.1.1
Set Row Address (75h) ........................................................................................................................42
10.1.2
Set Contrast Current (81h) .................................................................................................................43
10.1.3
NOP (84h ~ 86h).................................................................................................................................43
10.1.4
Set Re-map (A0h) ................................................................................................................................43
10.1.5
Set Display Start Line (A1h) ...............................................................................................................46
10.1.6
Set Display Offset (A2h)......................................................................................................................47
10.1.7
Set Display Mode (A4h ~ A7h)............................................................................................................48
10.1.8
Set Multiplex Ratio (A8h)....................................................................................................................49
10.1.9
10.1.10 Function selection A (ABh).................................................................................................................49
10.1.11
Set Display ON/OFF (AEh / AFh) ......................................................................................................49
10.1.12
Set Phase Length (B1h).......................................................................................................................50
10.1.13 NOP (B2h) ..........................................................................................................................................50
10.1.14
Set Front Clock Divider / Oscillator Frequency (B3h).......................................................................50
Set GPIO (B5h)...................................................................................................................................50
10.1.15
10.1.16
Set Second Pre-charge period (B6h)...................................................................................................51
10.1.17
Set Gray Scale Table (B8h).................................................................................................................51
10.1.18
Select Default Linear Gray Scale Table (B9h)....................................................................................51
10.1.19 NOP (BBh)..........................................................................................................................................51
10.1.20
Set Pre-charge voltage (BCh) .............................................................................................................51
9
9.1
SSD1327
Rev 1.1
P 3/68
Dec 2008
Solomon Systech
10.1.21
Set VCOMH Voltage (BEh).....................................................................................................................51
10.1.22 Function selection B (D5h).................................................................................................................52
Set Command Lock (FDh)...................................................................................................................52
10.1.23
10.2 GRAPHIC ACCELERATION COMMAND DESCRIPTION.............................................................................................53
10.2.1
Horizontal Scroll Setup (26h/27h) ......................................................................................................53
Deactivate Scroll (2Eh).......................................................................................................................54
10.2.2
Activate Scroll (2Fh)...........................................................................................................................54
10.2.3
11 MAXIMUM RATINGS ..........................................................................................................55
12 DC CHARACTERISTICS .....................................................................................................56
13 AC CHARACTERISTICS .....................................................................................................57
14 APPLICATION EXAMPLES................................................................................................63
PACKAGE INFORMATION ................................................................................................65
15
15.1 SSD1327Z DIE TRAY INFORMATION...................................................................................................................65
15.2 SSD1327UR1 DETAIL DIMENSION.......................................................................................................................67
Solomon Systech
Dec 2008 P 4/68
Rev 1.1
SSD1327
TABLES
Table 2-1 VCI and VDD range ................................................................................................................................................7
Table 3-1: Ordering Information ..........................................................................................................................................8
Table 5-1: SSD1327Z Bump Die Pad Coordinates ............................................................................................................11
Table 6-1: SSD1327UR1 Pin Assignment Table................................................................................................................14
Table 7-1 : SSD1327 Pin Description.................................................................................................................................15
Table 7-2 : Bus Interface selection .....................................................................................................................................15
Table 8-1 : MCU interface assignment under different bus interface mode.......................................................................18
Table 8-2 : Control pins of 6800 interface..........................................................................................................................18
Table 8-3 : Control pins of 8080 interface..........................................................................................................................20
Table 8-4 : Control pins of 4-wire Serial interface .............................................................................................................20
Table 8-5: Control pins of 3-wire Serial interface ..............................................................................................................21
Table 8-6 : GDDRAM address map 1 ................................................................................................................................30
Table 8-7 : GDDRAM address map 2 ................................................................................................................................31
Table 8-8 : GDDRAM address map 3 ................................................................................................................................31
Table 8-9 : GDDRAM address map 4 ................................................................................................................................32
Table 8-10 : GDDRAM address map 5 ..............................................................................................................................32
Table 9-1: Command Table ................................................................................................................................................36
Table 9-2 : Address increment table (Automatic)...............................................................................................................41
Table 11-1: Maximum Ratings...........................................................................................................................................55
Table 12-1 : DC Characteristics..........................................................................................................................................56
Table 13-1 : AC Characteristics..........................................................................................................................................57
Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics .........................................................................58
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics .........................................................................59
Table 13-4 : Serial Interface Timing Characteristics (4-wire SPI) .....................................................................................60
Table 13-5: Serial Interface Timing Characteristics (3-wire SPI) ......................................................................................61
Table 13-6: I2C Interface Timing Characteristics ...............................................................................................................62
Table 15-1: SSD1327Z Die Tray Dimensions....................................................................................................................66
SSD1327
Rev 1.1
P 5/68
Dec 2008
Solomon Systech
FIGURES
Figure 4-1: SSD1327 Block Diagram...................................................................................................................................9
Figure 5-1: SSD1327Z Die Drawing ..................................................................................................................................10
Figure 5-2: SSD1327Z alignment mark dimension ............................................................................................................10
Figure 6-1: SSD1327UR1 Pin Assignment ........................................................................................................................13
Figure 8-1 : Data read back procedure - insertion of dummy read .....................................................................................19
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode ........................................................................19
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode .........................................................................19
Figure 8-4 : Display data read back procedure - insertion of dummy read.........................................................................20
Figure 8-5 : Write procedure in 4-wire Serial interface mode ............................................................................................21
Figure 8-6: Write procedure in 3-wire Serial interface mode .............................................................................................21
Figure 8-7 : I2C-bus data format .........................................................................................................................................23
Figure 8-8 : Definition of the Start and Stop Condition......................................................................................................24
Figure 8-9 : Definition of the acknowledgement condition ................................................................................................24
Figure 8-10 : Definition of the data transfer condition .......................................................................................................24
Figure 8-11: Segment and Common Driver Block Diagram ..............................................................................................25
Figure 8-12 : Segment and Common Driver Signal Waveform..........................................................................................26
Figure 8-13 : Gray Scale Control by PWM in Segment .....................................................................................................27
Figure 8-14: Oscillator Circuit............................................................................................................................................28
Figure 8-15 : IREF Current Setting by Resistor Value..........................................................................................................30
Figure 8-16 : Relation between GDDRAM content and Gray Scale table entry (under command B9h Enable Linear Gray
Scale Table) ................................................................................................................................................................33
Figure 8-17 : The Power ON sequence...............................................................................................................................34
Figure 8-18 : The Power OFF sequence .............................................................................................................................34
Figure 8-19 VCI > 2.6V, VDD regulator enable pin connection scheme ..............................................................................35
Figure 8-20 VDD regulator disable pin connection scheme.................................................................................................35
Figure 10-1: Example of Column and Row Address Pointer Movement ...........................................................................42
Figure 10-2: Address Pointer Movement of Horizontal Address Increment Mode ............................................................43
Figure 10-3: Address Pointer Movement of Vertical Address Increment Mode ................................................................44
Figure 10-4: Output pin assignment when command A0h bit A[6]=0. ..............................................................................44
Figure 10-5 : Output pin assignment when command A0h bit A[6]=1...............................................................................45
Figure 10-6: Example of Set Display Start Line with no Remapping.................................................................................46
Figure 10-7: Example of Set Display Offset with no Remapping ......................................................................................47
Figure 10-8: Example of Normal Display...........................................................................................................................48
Figure 10-9: Example of Entire Display ON ......................................................................................................................48
Figure 10-10 : Example of Entire Display OFF..................................................................................................................48
Figure 10-11: Example of Inverse Display.........................................................................................................................48
Figure 10-12: Display ON Sequence (when initial start)....................................................................................................49
Figure 10-13: Display OFF Sequence.................................................................................................................................49
Figure 10-14: Display ON Sequence (During Sleep mode and internal VDD regulator is disabled)...................................50
Figure 10-15 : Example of Gamma correction by Gamma Look Up table setting .............................................................51
Figure 10-16 : Horizontal scroll example: Scroll RIGHT by 1 column..............................................................................53
Figure 10-17 : Horizontal scroll example: Scroll LEFT by 1 column ................................................................................53
Figure 10-18 : Horizontal scrolling setup example.............................................................................................................53
Figure 13-1 : 6800-series MCU parallel interface characteristics.......................................................................................58
Figure 13-2 : 8080-series MCU parallel interface characteristics.......................................................................................59
Figure 13-3 : Serial interface characteristics (4-wire SPI)..................................................................................................60
Figure 13-4: Serial interface characteristics (3-wire SPI)...................................................................................................61
Figure 13-5: I2C interface Timing characteristics...............................................................................................................62
Figure 14-1 : SSD1327Z application example for 8-bit 6800-parallel interface mode (Internal regulated VDD) ...............63
Figure 14-2 : SSD1327UR1 application example for 8-bit 6800-parallel interface mode (Internal regulated VDD) ..........64
Figure 15-1: SSD1327Z Die Tray Drawing........................................................................................................................65
Figure 15-2: SSD1327UR1 Detail Dimension....................................................................................................................67
Solomon Systech
Dec 2008 P 6/68
Rev 1.1
SSD1327
1 GENERAL DESCRIPTION
SSD1327 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting
diode dot-matrix graphic display system. It consists of 128 segments and 128 commons. This IC is
designed for Common Cathode type OLED/PLED panel.
SSD1327 displays data directly from its internal 128 x 128 x 4 bits Graphic Display Data RAM
(GDDRAM). Data/Commands are sent from general MCU through the hardware selectable I2C Interface,
6800-/8080-series compatible Parallel Interface or Serial Peripheral Interface.
2 FEATURES
• Resolution: 128 x 128 matrix panel
• Power supply
(Panel driving power supply)
o VCC = 8V ~ 18V
o VCI = 1.65V – 3.5V
o VDD = 1.65V – 2.6V (Core VDD power supply, details refer to Table 2-1)
Table 2-1 VCI and VDD range
VCI
1.65 V ~ 2.6V
VDD
1.65V ~ 2.6V VDD should be tied to VCI and supplied by
(MCU interface logic level & low voltage power supply)
Remark
external power source
VDD is regulated from VCI
2.4V ~ 2.6V
• For matrix display
2.6V ~ 3.5V
o VCI must be higher than or equivalent to VDD at any circumstance
o Segment maximum source current: 300uA
o Common maximum sink current: 40mA
o 256 step contrast brightness current control
• Embedded 128 x 128 x 4 bit SRAM display buffer
• 16 gray scale
• Pin selectable MCU Interfaces:
o 8-bit 6800/8080-series parallel interface
o 3 /4 wire Serial Peripheral Interface
o
I2C Interface
• Screen saving continuous scrolling function in both horizontal and vertical direction
• Programmable Frame Rate
• Programmable Multiplexing Ratio
• Row Re-mapping and Column Re-mapping
• On-Chip Oscillator
• Power On Reset (POR)
• Chip layout for COG , COF
• Wide range of operating temperature: -40°C to 85°C
SSD1327
Rev 1.1
P 7/68
Dec 2008
Solomon Systech
3 ORDERING INFORMATION
Ordering Part
Number
Table 3-1: Ordering Information
SEG COM Package Form Reference Remark
SSD1327Z
128
128
COG
Page 10
SSD1327UR1
128
80
COF
Page 13
o Min SEG pad pitch : 28um
o Min COM pad pitch : 28um
o Min I/O pad pitch : 60um
o Die thickness: 300 +/- 15um
o Output lead pitch:
0.12mm x 0.998 = 0.11976mm
o 4 SPH, 35m film
o 8-bit 80 / 68 / I2C / 4 line SPI
interfaces
Solomon Systech
Dec 2008 P 8/68
Rev 1.1
SSD1327
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