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Features • Low-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes are Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2™ Packages Description The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec- trically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8- lead TSSOP and 8-ball dBGA2 packages and is accessed via a 2-wire serial interface. Pin Configurations Pin Name Function A0 - A2 Address Inputs SDA SCL WP NC GND VCC Serial Data Serial Clock Input Write Protect No Connect Ground Power Supply 8-lead PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead TSSOP 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-ball dBGA2 VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND Bottom View 5-lead SOT23 SCL GND SDA 1 2 3 5 4 WP VCC 8-lead MAP VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND Bottom View 5-lead SOT23 Rotated (R) (1k only) SCL GND SDA 1 2 3 5 4 VCC NC 2-wire Serial EEPROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8) AT24C01A AT24C02 AT24C04 AT24C08(1) AT24C16(2) Note: 1. This device is not recom- mended for new designs. Please refer to AT24C08A. 2. This device is not recom- mended for new designs. Please refer to AT24C16A. 0180Q–SEEPR–1/04 1

In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Absolute Maximum Ratings Operating Temperature................................. -55° C to +125° C *NOTICE: Storage Temperature .................................... -65° C to +150° C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Block Diagram Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AT24C01A/02/04/08/16 0180Q–SEEPR–1/04

Pin Description AT24C01A/02/04/08/16 SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect. The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects. The AT24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects. WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status At VCC Part of the Array Protected 24C01A 24C02 24C04 24C08(1) 24C16(2) Full (1K) Array Full (2K) Array Full (4K) Array Normal Read/ Write Operation Upper Half (8K) Array At GND Normal Read/Write Operations Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A. 2. This device is not recommended for new designs. Please refer to AT24C16A. Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing. AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. 0180Q–SEEPR–1/04 3

Pin Capacitance(1) Applicable over recommended operating range from TA = 25° C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition Max CI/O CIN Note: Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. 8 6 Units Conditions pF pF VI/O = 0V VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40° C to +85° C, VCC = +1.8V to +5.5V, TAE = -40° C to +125° C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Test Condition Parameter Min Typ Max Units VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA 1. VIL min and VIH max are reference only and are not tested. 1.8 2.5 2.7 4.5 -0.6 VCC x 0.7 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 5.5 5.5 5.5 5.5 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 V V V V mA mA µA µA µA µA µA µA V V V V 4 AT24C01A/02/04/08/16 0180Q–SEEPR–1/04

AT24C01A/02/04/08/16 AC Characteristics Applicable over recommended operating range from TAI = -40° C to +85° C, TAE = -40° C to +125° C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 1.8-volt 2.5, 2.7, 5.0-volt Symbol Parameter fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time(2) Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(2) Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time(2) Inputs Fall Time(2) Stop Setup Time Data Out Hold Time Write Cycle Time Endurance(1) 5.0V, 25° C, Byte Mode Max 100 100 4.5 1.0 300 5 Min 4.7 4.0 0.1 4.7 4.0 4.7 0 200 4.7 100 1M Min 1.2 0.6 0.1 1.2 0.6 0.6 0 100 0.6 50 1M Max 400(1) Units kHz 50 0.9 0.3 300 5 µs µs ns µs µs µs µs µs ns µs ns µs ns ms Write Cycles Note: 1. The 24C01A/02/04 bearing the process letter “D” on the package (the mark is located in the lower right corner on the top side of the package), guarantees 400 kHz (2.5 – 5.0V). 2. This parameter is characterized and is not 100% tested. 0180Q–SEEPR–1/04 5

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter- nal device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2- wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. 6 AT24C01A/02/04/08/16 0180Q–SEEPR–1/04

AT24C01A/02/04/08/16 Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 0180Q–SEEPR–1/04 7

Data Validity Start and Stop Definition Output Acknowledge 8 AT24C01A/02/04/08/16 0180Q–SEEPR–1/04

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