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at89s52.pdf
Pin Configurations
Features
Description
Block Diagram
Pin Description
VCC
GND
Port 0
Port 1
Port 2
Port 3
RST
ALE/PROG
PSEN
EA/VPP
XTAL1
XTAL2
Special Function Registers
Memory Organization
Program Memory
Data Memory
Watchdog Timer (One-time Enabled with Reset-out)
Using the WDT
WDT During Power-down and Idle
UART
Timer 0 and 1
Timer 2
Capture Mode
Auto-reload (Up or Down Counter)
Baud Rate Generator
Programmable Clock Out
Interrupts
Oscillator Characteristics
Idle Mode
Power-down Mode
Program Memory Lock Bits
Programming the Flash – Parallel Mode
Programming the Flash – Serial Mode
Serial Programming Algorithm
Serial Programming Instruction Set
Programming Interface – Parallel Mode
Flash Programming and Verification Characteristics (Parallel Mode) TA = 20 C to 30 C, VCC = 4.5 t...
Flash Programming and Verification Waveforms – Serial Mode
Serial Programming Characteristics
Absolute Maximum Ratings*
DC Characteristics
AC Characteristics
External Program and Data Memory Characteristics
External Program Memory Read Cycle
External Data Memory Read Cycle
External Data Memory Write Cycle
External Clock Drive Waveforms
External Clock Drive
Serial Port Timing: Shift Register Mode Test Conditions
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Float Waveforms(1)
Ordering Information
Features
• Compatible with MCS-51® Products
8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next interrupt
or hardware reset.
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT89S52
Rev. 1919A-07/01
1
PLCC
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2
T
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1
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1
P
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2
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0
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1
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0
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1
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2
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3
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2
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6 5 4 3 2 1
4
4
3
4
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1
4
0
4
9
1
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
2
L
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9
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0
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3
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2
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1
1
A
(
4
.
2
P
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2
1
A
(
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
7
8
9
10
11
12
13
14
15
16
17
8
1
39
38
37
36
35
34
33
32
31
30
29
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
Pin Configurations
PDIP
(T2) P1.0
(T2 EX) P1.1
P1.2
P1.3
P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
TQFP
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1
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2
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3
D
A
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3
0
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4
1
P
.
3
1
P
.
2
1
P
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
4
4
3
4
2
4
1
4
0
4
9
3
8
3
7
3
6
3
5
3
4
3
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
0
2
1
2
2
2
2
L
A
T
X
1
L
A
T
X
D
N
G
D
N
G
6
.
3
P
)
R
W
(
7
.
3
P
)
D
R
(
0
.
2
P
)
8
A
(
1
.
2
P
)
9
A
(
2
.
2
P
)
0
1
A
(
3
.
2
P
)
1
1
A
(
4
.
2
P
)
2
1
A
(
2
AT89S52
AT89S52
Block Diagram
VCC
GND
P0.0 - P0.7
P2.0 - P2.7
PORT 0 DRIVERS
PORT 2 DRIVERS
RAM ADDR.
REGISTER
RAM
PORT 0
LATCH
PORT 2
LATCH
FLASH
B
REGISTER
ACC
STACK
POINTER
TMP2
TMP1
ALU
PSW
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
INSTRUCTION
REGISTER
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DUAL DPTR
WATCH
DOG
PORT 3
LATCH
PORT 1
LATCH
ISP
PORT
PROGRAM
LOGIC
OSC
PORT 3 DRIVERS
PORT 1 DRIVERS
P3.0 - P3.7
P1.0 - P1.7
3
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external
program and data memory. In this mode, P0 has internal
pullups.
Port 0 also receives the code bytes during Flash program-
ming and outputs the code bytes during program verifica-
tion. External pullups are required during program
verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port Pin
Alternate Functions
P1.0
P1.1
P1.5
P1.6
P1.7
T2 (external count input to Timer/Counter 2),
clock-out
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
MOSI (used for In-System Programming)
MISO (used for In-System Programming)
SCK (used for In-System Programming)
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
4
AT89S52
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89S52, as shown in the following table.
Port 3 also receives some control signals for Flash pro-
gramming and verification.
Port Pin
Alternate Functions
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device. This pin drives
High for 96 oscillator periods after the Watchdog times out.
The DISRTO bit in SFR AUXR (address 8EH) can be used
to disable this feature. In the default state of bit DISRTO,
the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching
the low byte of the address during accesses to external
memory. This pin is also the program pulse input (PROG)
during Flash programming.
In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data
memory.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to exter-
nal program memory.
When the AT89S52 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Table 1. AT89S52 SFR Map and Reset Values
AT89S52
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable volt-
age (VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
0F8H
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
TH2
00000000
00000000
AUXR1
XXXXXXX0
SBUF
XXXXXXXX
WDTRST
XXXXXXXX
TMOD
00000000
TL0
TL1
TH0
TH1
AUXR
00000000
00000000
00000000
00000000
XXX00XX0
P0
SP
11111111
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
0XXX0000
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
5
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit Addressable
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap-
ture mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Reset Value = 0000 0000B
Bit
TF2
7
EXF2
RCLK
TCLK
EXEN2
6
5
4
3
TR2
2
C/T2
1
CP/RL2
0
Symbol
Function
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
6
AT89S52
Table 3a. AUXR: Auxiliary Register
AUXR
Address = 8EH
Not Bit Addressable
AT89S52
Reset Value = XXX00XX0B
–
7
Bit
–
6
–
5
WDIDLE
DISRTO
4
3
–
2
–
1
DISALE
0
–
Reserved for future expansion
DISALE
Disable/Enable ALE
DISALE
Operating Mode
0
1
ALE is emitted at a constant rate of 1/6 the oscillator frequency
ALE is active only during a MOVX or MOVC instruction
DISRTO
Disable/Enable Reset out
DISRTO
0
1
Reset pin is driven High after WDT times out
Reset pin is input only
WDIDLE
Disable/Enable WDT in IDLE mode
WDIDLE
0
1
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both
internal and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0
in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data
Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.
Table 3b. AUXR1: Auxiliary Register 1
AUXR1
Address = A2H
Not Bit Addressable
Reset Value = XXXXXXX0B
–
7
Bit
–
6
–
5
–
4
–
3
–
2
–
1
DPS
0
–
DPS
Reserved for future expansion
Data Pointer Register Select
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
7
Memory Organization
MCS-51 devices have a separate address space for Pro-
gram and Data Memory. Up to 64K bytes each of external
Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are
directed to external memory.
On the AT89S52, if EA is connected to VCC, program
fetches to addresses 0000H through 1FFFH are directed to
internal memory and fetches to addresses 2000H through
FFFFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. This means that the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions which use direct
addressing access of the SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
8
AT89S52
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