AT45DB041E(AT45DB041E).pdf

发布时间：2023-11-29 发布人：admin 分类：养殖资料大小：2.48M 资料格式：pdf 举报版权申诉

第1页 / 共70页

第2页 / 共70页

第3页 / 共70页

第4页 / 共70页

第5页 / 共70页

第6页 / 共70页

第7页 / 共70页

第8页 / 共70页

Features

Description

1. Pin Configurations and Pinouts

2. Block Diagram

3. Memory Array

4. Device Operation

5. Read Commands

5.1 Continuous Array Read (Legacy Command: E8h Opcode)

5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode)

5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)

5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode)

5.5 Continuous Array Read (Low Power Mode: 01h Opcode)

5.6 Main Memory Page Read

5.7 Buffer Read

6. Program and Erase Commands

6.1 Buffer Write

6.2 Buffer to Main Memory Page Program with Built-In Erase

6.3 Buffer to Main Memory Page Program without Built-In Erase

6.4 Main Memory Page Program through Buffer with Built-In Erase

6.5 Main Memory Byte/Page Program through Buffer 1 without Built-In Erase

6.6 Read-Modify-Write

6.7 Page Erase

6.8 Block Erase

6.9 Sector Erase

6.10 Chip Erase

6.11 Program/Erase Suspend

6.12 Program/Erase Resume

7. Sector Protection

7.1 Software Sector Protection

7.1.1 Enable Sector Protection

7.1.2 Disable Sector Protection

7.2 Hardware Controlled Protection

7.3 Sector Protection Register

7.3.1 Erase Sector Protection Register

7.3.2 Program Sector Protection Register

7.3.3 Read Sector Protection Register

7.3.4 About the Sector Protection Register

8. Security Features

8.1 Sector Lockdown

8.1.1 Read Sector Lockdown Register

8.1.2 Freeze Sector Lockdown

8.2 Security Register

8.2.1 Programming the Security Register

8.2.2 Reading the Security Register

9. Additional Commands

9.1 Main Memory Page to Buffer Transfer

9.2 Main Memory Page to Buffer Compare

9.3 Auto Page Rewrite

9.4 Status Register Read

9.4.1 RDY/BUSY Bit

9.4.2 COMP Bit

9.4.3 DENSITY Bits

9.4.4 PROTECT Bit

9.4.5 PAGE SIZE Bit

9.4.6 EPE Bit

9.4.7 SLE Bit

9.4.8 PS2 Bit

9.4.9 PS1 Bit

9.4.10 The ES bit

10. Deep Power-Down

10.1 Resume from Deep Power-Down

10.2 Ultra-Deep Power-Down

10.2.1 Exit Ultra-Deep Power-Down

11. Buffer and Page Size Configuration

12. Manufacturer and Device ID Read

13. Software Reset

14. Operation Mode Summary

Group A commands consist of:

Group B commands consist of:

Group C commands consist of:

Group D commands consist of:

15. Command Tables

16. Power-On/Reset State

16.1 Power-Up/Power-Down Voltage and Timing Requirements

17. System Considerations

18. Electrical Specifications

18.1 Absolute Maximum Ratings*

18.2 DC and AC Operating Range

18.3 DC Characteristics

18.4 AC Characteristics

18.5 Program and Erase Characteristics

19. Input Test Waveforms and Measurement Levels

20. Output Test Load

21. Utilizing the RapidS Function

22. AC Waveforms

23. Write Operations

24. Read Operations

25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3

26. Auto Page Rewrite Flowchart

27. Ordering Information

27.1 Ordering Detail

27.2 Ordering Codes (Standard DataFlash Page Size)

27.3 Ordering Codes (Binary Page Size)

27.4 Ordering Codes (Reserved)

28. Packaging Information

28.1 8S1 – 8-lead JEDEC SOIC

28.2 8S2 – 8-lead EIAJ SOIC

28.3 8MA1 – 8-pad UDFN

28.4 CS4-8A – 8-ball WLCSP

29. Revision History

30. Errata

30.1 The specification for Exit Ultra Deep Power Down has been updated. The new specification for the 1.65- 3.6V range is 280 µs. The new specification for the 2.3-3.6V range is 140 µs.

AT45DB041E 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory Features  Single 1.65V - 3.6V supply  Serial Peripheral Interface (SPI) compatible  Supports SPI modes 0 and 3  Supports RapidS™ operation  Continuous read capability through entire array  Up to 85MHz  Low-power read option up to 15 MHz  Clock-to-output time (tV) of 6ns maximum  User configurable page size  256 bytes per page  264 bytes per page (default)  Page size can be factory pre-configured for 256 bytes  Two fully independent SRAM data buffers (256/264 bytes)  Allows receiving data while reprogramming the main memory array  Flexible programming options  Byte/Page Program (1 to 256/264 bytes) directly into main memory  Buffer Write  Buffer to Main Memory Page Program  Flexible erase options  Page Erase (256/264 bytes)  Block Erase (2KB)  Sector Erase (64KB)  Chip Erase (4-Mbits)  Program and Erase Suspend/Resume  Advanced hardware and software data protection features  Individual sector protection  Individual sector lockdown to make any sector permanently read-only  128-byte, One-Time Programmable (OTP) Security Register  64 bytes factory programmed with a unique identifier  64 bytes user programmable  Hardware and software controlled reset options  JEDEC Standard Manufacturer and Device ID Read  Low-power dissipation  400nA Ultra-Deep Power-Down current (typical)  3µA Deep Power-Down current (typical)  25µA Standby current (typical)  7mA Active Read current (typical @ 15 MHz))  Endurance: 100,000 program/erase cycles per page minimum  Data retention: 20 years  Complies with full industrial temperature range  Green (Pb/Halide-free/RoHS compliant) packaging options  8-lead SOIC (0.150" wide and 0.208" wide)  8-pad Ultra-thin DFN (5 x 6 x 0.6mm)  8-ball Wafer Level Chip Scale Package  Die in Wafer Form(1) Note: 1. Contact factory for availability. 8783L–DFLASH–7/2017

Description The AT45DB041E is a 1.65V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB041E also supports the RapidS serial interface for applications requiring very high speed operation. Its 4,194,304 bits of memory are organized as 2,048 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB041E also contains two SRAM buffers of 256/264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash® uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. To allow for simple in-system re-programmability, the AT45DB041E does not require high input voltages for programming. The device operates from a single 1.65V to 3.6V power supply for the erase and program and read operations. The AT45DB041E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed. 1. Pin Configurations and Pinouts Figure 1-1. Pinouts 8-lead SOIC Top View 8-pad UDFN Top View (1) (through package) SI SCK RESET CS 1 2 3 4 8 7 6 5 SO GND VCC WP SI SCK RESET CS 1 2 3 4 8 7 6 5 SO GND VCC WP (2) 8-Ball WLCSP Bottom View Pin 1 WP CS VCC RESET GND SCK SO SI Note: 1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad can be a “no connect” or connected to GND. 2. Contact info@adestotech.com for manufacturing flow and availability. AT45DB041E 8783L–DFLASH–7/2017 2

Table 1-1. Pin Configurations Symbol CS SCK SI SO WP RESET VCC GND Name and Function Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode) and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI). A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. After the WP pin goes low, the contents of the Sector Protection Register cannot be modified. If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The Enable Sector Protection command and the Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature is not utilized, then it is recommended that the RESET pin be driven high externally. Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. Ground: The ground reference for the power supply. GND should be connected to the system ground. Asserted State Type Low Input — — — Input Input Output Low Input Low Input — — Power Ground AT45DB041E 8783L–DFLASH–7/2017 3

2. Block Diagram Figure 2-1. Block Diagram WP Flash Memory Array Page (256/264 bytes) Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) SCK CS RESET VCC GND I/O Interface SI SO AT45DB041E 8783L–DFLASH–7/2017 4

3. Memory Array To provide optimal flexibility, the AT45DB041E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3-1. Memory Architecture Diagram Sector Architecture Block Architecture Page Architecture Sector 0a = 8 pages 2,048/2,112 bytes Sector 0b = 248 pages 63,488/65,472 bytes Sector 1 = 256 pages 65,536/67,584 bytes Sector 2 = 256 pages 65,536/67,584 bytes Sector 6 = 256 pages 65,536/67,584 bytes Sector 7 = 256 pages 65,536/67,584 bytes 8 Pages Block 0 Block 1 Block 2 Block 30 Block 31 Block 32 Block 33 Block 62 Block 63 Block 64 Block 65 Sector 0a b 0 r o t c e S 1 r o t c e S 2 r o t c e S 0 k c o B l 1 k c o B l Page 0 Page 1 Page 6 Page 7 Page 8 Page 9 Page 14 Page 15 Page 16 Page 17 Page 18 Block 254 Block 255 Block = 2,048/2,112 bytes Page 2,046 Page 2,047 Page = 256/264 bytes AT45DB041E 8783L–DFLASH–7/2017 5

4. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 40 through Table 15-4 on page 41. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit (MSB) first. Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM buffers. The three address bytes will be comprised of a number of dummy bits and a number of actual device address bits, with the number of dummy bits varying depending on the operation being performed and the selected device page size. Buffer addressing for the standard DataFlash page size (264 bytes) is referenced in the datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer. The main memory addressing is referenced using the terminology PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to designate a page address, and BA8 - BA0 denotes the 9 address bits required to designate a byte address within the page. Therefore, when using the standard DataFlash page size, a total of 20 address bits are used. For the “power of 2” binary page size (256 bytes), the buffer addressing is referenced in the datasheet using the conventional terminology BFA7 - BFA0 to denote the eight address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to designate a page address, and A7 - A0 denotes the eight address bits required to designate a byte address within a page. Therefore, when using the binary page size, a total of 19 address bits are used. AT45DB041E 8783L–DFLASH–7/2017 6

5. 5.1 5.2 Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each mode. Continuous Array Read (Legacy Command: E8h Opcode) By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the need for additional address sequences. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read and the last nine (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and four dummy bytes. The first 11 bits (A18 - A8) of the 19-bit address sequence specify which page of the main memory array to read and the last eight bits (A7 - A0) of the 19-bit address sequence specify the starting byte address within the page. The dummy bytes that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data buffers and leaves the contents of the buffers unchanged. Warning: This command is not recommended for new designs. Continuous Array Read (High Frequency Mode: 1Bh Opcode) This command can be used to read the main memory array sequentially at the highest possible operating clock frequency up to the maximum specified by fCAR4. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device followed by three address bytes and two dummy bytes. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A18 - A0) and two dummy bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (Serial Output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. AT45DB041E 8783L–DFLASH–7/2017 7

5.3 5.4 A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. Continuous Array Read (High Frequency Mode: 0Bh Opcode) This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum specified by fCAR1. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and one dummy byte. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A18 - A0) and one dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. Continuous Array Read (Low Frequency Mode: 03h Opcode) This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for the lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A18 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.5 Continuous Array Read (Low Power Mode: 01h Opcode) This command is ideal for applications that want to minimize power consumption and do not need to read the memory array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the main memory array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. The memory can be read at clock frequencies up to maximum specified by fCAR3. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 01h must be clocked into the device followed by three address bytes. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page AT45DB041E 8783L–DFLASH–7/2017 8

分享到：

赞收藏

资料库

AT45DB041E(AT45DB041E).pdf

相关推荐

传感器

热门标签

最新资料