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AT45DB081D(AT45DB081D).pdf
Features
1. Description
2. Pin Configurations and Pinouts
3. Block Diagram
4. Memory Array
5. Device Operation
6. Read Commands
6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz
6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
6.4 Main Memory Page Read
6.5 Buffer Read
7. Program and Erase Commands
7.1 Buffer Write
7.2 Buffer to Main Memory Page Program with Built-in Erase
7.3 Buffer to Main Memory Page Program without Built-in Erase
7.4 Page Erase
7.5 Block Erase
7.6 Sector Erase
7.7 Chip Erase
7.8 Main Memory Page Program Through Buffer
8. Sector Protection
8.1 Software Sector Protection
8.1.1 Enable Sector Protection Command
8.1.2 Disable Sector Protection Command
8.1.3 Various Aspects About Software Controlled Protection
9. Hardware Controlled Protection
9.1 Sector Protection Register
9.1.1 Erase Sector Protection Register Command
9.1.2 Program Sector Protection Register Command
9.1.3 Read Sector Protection Register Command
9.1.4 Various Aspects About the Sector Protection Register
10. Security Features
10.1 Sector Lockdown
10.1.1 Sector Lockdown Register
10.1.2 Reading the Sector Lockdown Register
10.2 Security Register
10.2.1 Programming the Security Register
10.2.2 Reading the Security Register
11. Additional Commands
11.1 Main Memory Page to Buffer Transfer
11.2 Main Memory Page to Buffer Compare
11.3 Auto Page Rewrite
11.4 Status Register Read
12. Deep Power-down
12.1 Resume from Deep Power-down
13. “Power of 2” Binary Page Size Option
13.1 Programming the Configuration Register
14. Manufacturer and Device ID Read
14.1 Manufacturer and Device ID Information
14.1.1 Byte 1 - Manufacturer ID
14.1.2 Byte 2 - Device ID (Part 1)
14.1.3 Byte 3 - Device ID (Part 2)
14.1.4 Byte 4 - Extended Device Information String Length
14.2 Operation Mode Summary
15. Command Tables
16. Power-on/Reset State
16.1 Initial Power-up/Reset Timing Restrictions
17. System Considerations
18. Electrical Specifications
19. Input Test Waveforms and Measurement Levels
20. Output Test Load
21. AC Waveforms
21.1 Waveform 1 - SPI Mode 0 Compatible (for Frequencies up to 66 MHz)
21.2 Waveform 2 - SPI Mode 3 Compatible (for Frequencies up to 66 MHz)
21.3 Waveform 3 - RapidS Mode 0 (FMAX = 66 MHz)
21.4 Waveform 4 - RapidS Mode 3 (FMAX = 66 MHz)
21.5 Utilizing the RapidS Function
21.6 Reset Timing
21.7 Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status Register Read, Manufacturer and Device ID Read)
21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read)
22. Write Operations
22.1 Buffer Write
22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
23. Read Operations
23.1 Main Memory Page Read
23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
23.3 Buffer Read
24. Detailed Bit-level Read Waveform - RapidS Serial Interface Mode 0/Mode 3
24.1 Continuous Array Read (Legacy Opcode E8H)
24.2 Continuous Array Read (Opcode 0BH)
24.3 Continuous Array Read (Low Frequency: Opcode 03H)
24.4 Main Memory Page Read (Opcode: D2H)
24.5 Buffer Read (Opcode D4H or D6H)
24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)
24.7 Read Sector Protection Register (Opcode 32H)
24.8 Read Sector Lockdown Register (Opcode 35H)
24.9 Read Security Register (Opcode 77H)
24.10 Status Register Read (Opcode D7H)
24.11 Manufacturer and Device Read (Opcode 9FH)
25. Auto Page Rewrite Flowchart
26. Ordering Information
26.1 Green Package Options (Pb/Halide-free/RoHS Compliant)
27. Packaging Information
27.1 8S1 - JEDEC SOIC
27.2 8S2 - EIAJ SOIC
27.3 8M1-A - MLF
28. Revision History
29. Errata
29.1 Chip Erase
29.1.1 Issue
29.1.2 Workaround
29.1.3 Resolution
Features
• Single 2.5V or 2.7V to 3.6V Supply
RapidS® Serial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256 Bytes per Page
– 264 Bytes per Page
Page Program Operation
– Intelligent Programming Operation
– 4,096 Pages (256/264 Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256 Bytes)
– Block Erase (2 Kbytes)
– Sector Erase (64 Kbytes)
– Chip Erase (8 Mbits)
Two SRAM Data Buffers (256/264 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7 mA Active Read Current Typical
– 25 µA Standby Current Typical
– 5 µA Deep Power Down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
8-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB081D
1. Description
The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB081D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66 MHz. Its 8,650,752 bits of memory are organized as 4,096 pages of 256 bytes or
264 bytes each. In addition to the main memory, the AT45DB081D also contains two
SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous
data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-
contained three step read-modify-write operation. Unlike conventional Flash memo-
ries that are accessed randomly with multiple address lines and a parallel interface,
3596H–DFLASH–1/08
the DataFlash uses a RapidS serial interface to sequentially access its data. The simple sequen-
tial access dramatically reduces active pin count, facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size. The device is optimized for use
in many commercial and industrial applications where high-density, low-pin count, low-voltage
and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB081D does not require high input
voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V
to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the
chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),
Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2. Pin Configurations and Pinouts
Figure 2-1. MLF Top View
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
Figure 2-2.
SOIC Top View
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
2
AT45DB081D
3596H–DFLASH–1/08
AT45DB081D
Table 2-1.
Pin Configurations
Symbol
CS
SCK
SI
SO
WP
RESET
VCC
GND
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device
will be deselected and normally be placed in the standby mode (not Deep Power-Down mode),
and the output pin (SO) will be in a high-impedance state. When the device is deselected, data
will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such as
a program or erase cycle, the device will not enter the standby mode until the completion of the
operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always
clocked out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of whether
the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle state
once the CS pin has been deasserted. The Enable Sector Protection command and Sector
Lockdown command, however, will be recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long as
a low level is present on the RESET pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
Asserted
State
Type
Low
Input
–
–
–
Input
Input
Output
Low
Input
Low
Input
–
–
Power
Ground
3596H–DFLASH–1/08
3
3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 1 (256/264 BYTES)
BUFFER 2 (256/264 BYTES)
SCK
CS
RESET
VCC
GND
I/O INTERFACE
SI
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
SECTOR 0a = 8 Pages
2,048/2,112 bytes
SECTOR 0b = 248 Pages
63,488/65,472 bytes
SECTOR 1 = 256 Pages
65,536/67,584 bytes
SECTOR 2 = 256 Pages
65,536/67,584 bytes
SECTOR 14 = 256 Pages
65,536/67,584 bytes
SECTOR 15 = 256 Pages
65,536/67,584 bytes
SECTOR 0a
b
0
R
O
T
C
E
S
1
R
O
T
C
E
S
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
8 Pages
0
K
C
O
L
B
1
K
C
O
L
B
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 510
BLOCK 511
Block = 2,048/2,112 bytes
PAGE 4,094
PAGE 4,095
Page = 256/264 bytes
4
AT45DB081D
3596H–DFLASH–1/08
5. Device Operation
AT45DB081D
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-7 on
page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main memory
address location through the SI (serial input) pin. All instructions, addresses, and data are trans-
ferred with the most significant bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the
datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA11 - PA0 and BA8 - BA0, where PA11 - PA0 denotes the 12 address bits required to desig-
nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte
address within the page.
For “Power of 2” binary page size (256 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A19 - A0, where A19 - A8 denotes the 12 address bits required to desig-
nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte
address within a page.
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and
Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for
details on the clock cycle sequences for each mode.
6.1
Continuous Array Read (Legacy Command: E8H): Up to 66 MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (264 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The
first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main mem-
ory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence specify the
starting byte address within the page. To perform a continuous read from the binary page size
(256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes
and 4 don’t care bytes. The first 12 bits (A19 - A8) of the 20-bits sequence specify which page of
the main memory array to read, and the last 8 bits (A7 - A0) of the 20-bits address sequence
specify the starting byte address within the page. The don’t care bytes that follow the address
bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
3596H–DFLASH–1/08
5
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with cross-
ing over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by
the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the
contents of the buffers unchanged.
6.2
Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a
continuous read array with the page size set to 264 bytes, the CS must first be asserted then an
opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the
main memory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence spec-
ify the starting byte address within the page. To perform a continuous read with the page size
set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address
bytes (A19 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the
SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
6.3
Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 264 bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 12 bits (PA11 - PA0) of the 21-bit address sequence
specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the
21-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 256 bytes, the opcode, 03H, must be clocked into the device
followed by three address bytes (A19 - A0). Following the address bytes, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
6
AT45DB081D
3596H–DFLASH–1/08
AT45DB081D
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
6.4 Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 4,096 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and 4 don’t care bytes. The first 12 bits (PA11 - PA0) of
the 21-bit address sequence specify the page in main memory to be read, and the last 9 bits
(BA8 - BA0) of the 21-bit address sequence specify the starting byte address within that page.
To start a page read from the binary page size (256 bytes), the opcode D2H must be
clocked into the device followed by three address bytes and 4 don’t care bytes. The first 12 bits
(A19 - A8) of the 20-bits sequence specify which page of the main memory array to read, and
the last 8 bits (A7 - A0) of the 20-bits address sequence specify the starting byte address within
the page. The don’t care bytes that follow the address bytes are sent to initialize the read opera-
tion. Following the don’t care bytes, additional pulses on SCK result in data being output on the
SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a page in main
memory is reached, the device will continue reading back at the beginning of the same page. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin
(SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the
fSCK specification. The Main Memory Page Read bypasses both data buffers and leaves the con-
tents of the buffers unchanged.
The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four
opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read
Command. The use of each opcode depends on the maximum SCK frequency that will be used
to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to
the maximum specified by fCAR1. The D1H and D3H opcode can be used for lower frequency
read operations up to the maximum specified by fCAR2.
To perform a buffer read from the standard DataFlash buffer (264 bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 15 don’t care bits and
9 buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256 bytes),
the opcode must be clocked into the device followed by three address bytes comprised of
16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one
don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low
during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
6.5
Buffer Read
3596H–DFLASH–1/08
7
7. Program and Erase Commands
7.1
Buffer Write
Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the
standard DataFlash buffer (264 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2,
must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits
and 9 buffer address bits (BFA8 - BFA0). The 9 buffer address bits specify the first byte in the
buffer to be written. To load data into the binary buffers (256 bytes each), a 1-byte opcode 84H
for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). The 8 buffer address
bits specify the first byte in the buffer to be written. After the last address byte has been clocked
into the device, data can then be clocked in on subsequent clock cycles. If the end of the data
buffer is reached, the device will wrap around back to the beginning of the buffer. Data will con-
tinue to be loaded into the buffer until a low-to-high transition is detected on the CS pin.
7.2
Buffer to Main Memory Page Program with Built-in Erase
Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte
opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the DataFlash
standard page size (264 bytes), the opcode must be followed by three address bytes consist of
3 don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to
be written and 9 don’t care bits. To perform a buffer to main memory page program with built-in
erase for the binary page size (256 bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must
be clocked into the device followed by three address bytes consisting of 4 don’t care bits
12 page address bits (A19 - A8) that specify the page in the main memory to be written and
8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the
selected page in main memory (the erased state is a logic 1) and then program the data stored
in the buffer into the specified page in main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum time of tEP. During this time,
the status register will indicate that the part is busy.
7.3
Buffer to Main Memory Page Program without Built-in Erase
A previously-erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into
the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by
three address bytes consist of 3 don’t care bits, 12 page address bits (PA11 - PA0) that specify
the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main
memory page program without built-in erase for the binary page size (256 bytes), the opcode
88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address
bytes consisting of 4 don’t care bits, 12 page address bits (A19 - A8) that specify the page in the
main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS
pin, the part will program the data stored in the buffer into the specified page in the main mem-
ory. It is necessary that the page in main memory that is being programmed has been previously
erased using one of the erase commands (Page Erase or Block Erase). The programming of the
page is internally self-timed and should take place in a maximum time of tP. During this time, the
status register will indicate that the part is busy.
8
AT45DB081D
3596H–DFLASH–1/08
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