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SSD1357(SSD1357_1.1).pdf
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1357
Advance Information
128 RGB x 128 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1357
Copyright 2019 Solomon Systech Limited
Rev 1.1
P 1/36
Apr 2019
Appendix: IC Revision history of SSD1357 Specification
Version
0.10
0.20
1.0
1.1
Change Items
1st release
P. 9-10 Updated D_SEL and IREF in Pin Description
P. 19 Updated 256 color depth description in GDDRAM
P. 22 Updated SEG/COM Drivers description
P. 26 Updated Power ON and OFF sequence description
P. 28 Updated DC Characteristic parameters
P. 29 Updated AC Characteristic parameters
P. 35 Updated application example
Updated to Advance Information
P. 20 Updated Table 6-8 Read Data bus usage under different bus width and color
depth mode
P. 21 Updated SEG/COM Driving block description
P. 22 Updated Figure 6-13 Segment and Common Driver Block Diagram
Effective Date
27-May-16
23-Sep-16
09-Dec-16
03-Apr-19
Solomon Systech
Apr 2019 P 2/36
Rev 1.1 SSD1357
CONTENTS
1 GENERAL DESCRIPTION ....................................................................................................... 6
2 FEATURES .................................................................................................................................. 6
3 ORDERING INFORMATION................................................................................................... 6
4 BLOCK DIAGRAM .................................................................................................................... 7
5 PIN DESCRIPTION .................................................................................................................... 8
6 FUNCTIONAL BLOCK DESCRIPTIONS ............................................................................ 11
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1 MCU INTERFACE SELECTION ............................................................................................................................. 11
MCU Parallel 6800-series Interface ......................................................................................................... 11
MCU Parallel 8080-series Interface ......................................................................................................... 12
MCU Serial Interface (4-wire SPI) ........................................................................................................... 13
MCU Serial Interface (3-wire SPI) ........................................................................................................... 14
MCU I2C Interface .................................................................................................................................... 15
COMMAND DECODER ......................................................................................................................................... 18
OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR .................................................................................... 18
RESET CIRCUIT .................................................................................................................................................. 19
GDDRAM ......................................................................................................................................................... 19
GDDRAM structure ................................................................................................................................... 19
Data bus to RAM mapping under different input mode ............................................................................. 20
SEG/COM DRIVING BLOCK ............................................................................................................................... 21
SEG / COM DRIVERS ........................................................................................................................................ 22
GRAY SCALE DECODER ..................................................................................................................................... 25
POWER ON AND OFF SEQUENCE ....................................................................................................................... 26
6.5.1
6.5.2
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7 MAXIMUM RATINGS ............................................................................................................. 27
8 DC CHARACTERISTICS ........................................................................................................ 28
9 AC CHARACTERISTICS ........................................................................................................ 29
10 APPLICATION EXAMPLE .................................................................................................... 35
SSD1357
Rev 1.1
P 3/36
Apr 2019
Solomon Systech
TABLES
TABLE 3-1: ORDERING INFORMATION...................................................................................................................................6
TABLE 5-1: PIN DESCRIPTION ................................................................................................................................................8
TABLE 5-2: BUS INTERFACE SELECTION ...............................................................................................................................9
TABLE 6-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ...................................................... 11
TABLE 6-2 : CONTROL PINS OF 6800 INTERFACE ................................................................................................................. 11
TABLE 6-3 : CONTROL PINS OF 8080 INTERFACE ................................................................................................................. 13
TABLE 6-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE ................................................................................................. 13
TABLE 6-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE ................................................................................................. 14
TABLE 6-6: 65K COLOR DEPTH GRAPHIC DISPLAY DATA RAM STRUCTURE ..................................................................... 19
TABLE 6-7 : WRITE DATA BUS USAGE UNDER DIFFERENT BUS WIDTH AND COLOR DEPTH MODE ........................................ 20
TABLE 6-8 : READ DATA BUS USAGE UNDER DIFFERENT BUS WIDTH AND COLOR DEPTH MODE .......................................... 20
TABLE 7-1 : MAXIMUM RATINGS ........................................................................................................................................ 27
TABLE 9-1 : AC CHARACTERISTICS .................................................................................................................................... 29
TABLE 9-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS ........................................................... 30
TABLE 9-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS ........................................................... 31
TABLE 9-4 : SERIAL INTERFACE TIMING CHARACTERISTICS (4-WIRE SPI).......................................................................... 32
TABLE 9-5 : SERIAL INTERFACE TIMING CHARACTERISTICS (3-WIRE SPI).......................................................................... 33
TABLE 9-6 : I2C INTERFACE TIMING CHARACTERISTICS ..................................................................................................... 34
Solomon Systech
Apr 2019 P 4/36
Rev 1.1 SSD1357
FIGURES
FIGURE 4-1: SSD1357 BLOCK DIAGRAM .............................................................................................................................7
FIGURE 6-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ....................................................................... 12
FIGURE 6-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE ......................................................... 12
FIGURE 6-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE ........................................................... 12
FIGURE 6-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ......................................................... 13
FIGURE 6-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE ............................................................................... 14
FIGURE 6-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE ............................................................................... 14
FIGURE 6-7 : I2C-BUS DATA FORMAT .................................................................................................................................. 16
FIGURE 6-8 : DEFINITION OF THE START AND STOP CONDITION.......................................................................................... 17
FIGURE 6-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION .................................................................................... 17
FIGURE 6-10 : DEFINITION OF THE DATA TRANSFER CONDITION ......................................................................................... 17
FIGURE 6-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR .............................................................................. 18
FIGURE 6-12 : IREF CURRENT SETTING BY RESISTOR VALUE............................................................................................... 21
FIGURE 6-13 : SEGMENT AND COMMON DRIVER BLOCK DIAGRAM .................................................................................... 22
FIGURE 6-14 : SEGMENT AND COMMON DRIVER SIGNAL WAVEFORM ................................................................................ 23
FIGURE 6-15 : GRAY SCALE CONTROL IN SEGMENT ........................................................................................................... 24
FIGURE 6-16 : RELATION BETWEEN GDDRAM CONTENT AND GRAY SCALE TABLE ENTRY FOR THREE COLORS IN 65K
COLOR MODE ............................................................................................................................................................... 25
FIGURE 6-17 : ILLUSTRATION OF RELATION BETWEEN GRAPHIC DISPLAY RAM VALUE AND GRAY SCALE CONTROL .......... 25
FIGURE 6-18 : THE POWER ON SEQUENCE .......................................................................................................................... 26
FIGURE 6-19 : THE POWER OFF SEQUENCE ........................................................................................................................ 26
FIGURE 9-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS ........................................................................ 30
FIGURE 9-2 : 8080-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS ........................................................................ 31
FIGURE 9-3 : SERIAL INTERFACE CHARACTERISTICS (4-WIRE SPI) ...................................................................................... 32
FIGURE 9-4 : SERIAL INTERFACE CHARACTERISTICS (3-WIRE SPI) ...................................................................................... 33
FIGURE 9-5 : I2C INTERFACE TIMING CHARACTERISTICS ..................................................................................................... 34
FIGURE 10-1 : SSD1357Z APPLICATION EXAMPLE FOR 16-BIT 8080-PARALLEL INTERFACE MODE ..................................... 35
SSD1357
Rev 1.1
P 5/36
Apr 2019
Solomon Systech
1 GENERAL DESCRIPTION
SSD1357 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting
diode dot-matrix graphic display. It consists of 384 segments and 128 commons output, supporting up to
128RGB x 128 dot matrix display. This IC is designed for Common Cathode type OLED/PLED panel.
SSD1357 has embedded Graphic Display Data RAM (GDDRAM). Data/Commands are sent from
general MCU through the hardware selectable 8, 16 bits 6800-/8080-series compatible Parallel Interface,
I2C Interface, or Serial Peripheral Interface. It supports 256-step contrast and 65K color control.
SSD1357 is suitable for portable applications such as wearable electronics with vivid color OLED
display.
Resolution: 128RGB x 128 dot matrix panel
o VDD = 1.65V – 3.5V
o VCC = 8.0V – 18.0V (Panel driving power supply)
(MCU interface logic level & low voltage power supply)
Segment maximum source current: 320uA
Common maximum sink current: 80mA
Pin selectable MCU Interfaces:
o 8/16 bits 6800/8080-series parallel Interface
o 3/4 wire Serial Peripheral Interface
o
I2C Interface
256 step brightness current control for the each color component plus 16 step master current
Support color depth of 256 and 65k
Support 3 individual Gamma Look Up Tables (GLUT) for R, G, B
Color Swapping Function (RGB – BGR)
Row re-mapping and Column re-mapping
Screen saving continuous scrolling function in both horizontal and vertical direction
Screen saving infinite content scrolling function
Programmable Frame Rate
Power On Reset (POR)
On-Chip Oscillator
Chip layout for COG, COF
Operating temperature range -40C to 85C
3 ORDERING INFORMATION
Table 3-1: Ordering Information
Ordering Part Number
SEG
COM
Package Form Remark
SSD1357Z
128RGB
128
COG
o Min SEG pad pitch : 27um
o Min COM pad pitch : 33.4um
o Min I/O pad pitch : 55um
o Die thickness: 250um
o Bump height: nominal 12um
Solomon Systech
Apr 2019 P 6/36
Rev 1.1 SSD1357
4 BLOCK DIAGRAM
Figure 4-1: SSD1357 Block Diagram
VBREF
VLL
VLH
D_SEL
RES#
CS#
D/C#
E(RD#)
R/W# (WR#)
BS0
BS1
BS2
D[15:0]
U
C
M
e
c
a
f
r
e
t
n
I
M
A
R
D
D
G
r
e
d
o
c
e
D
e
l
a
c
S
y
a
r
G
VDD
VCC
VSS
VLSS
VSL
T0
T1
VPP
BGGND
g
n
i
m
T
i
r
o
t
a
r
e
n
e
G
g
n
i
v
i
r
D
M
O
C
G
E
S
/
k
c
o
l
B
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o
t
a
l
l
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c
s
O
y
a
l
p
s
i
D
d
n
a
m
m
o
C
r
e
d
o
c
e
D
S
L
C
L
C
R
F
P
V
F
E
R
I
H
M
O
C
V
s
r
e
v
i
r
D
n
o
m
m
o
C
s
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e
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t
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d
d
o
(
)
n
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(
COM127
COM125
.
.
.
COM3
COM1
SC127
SB127
SA127
SC126
SB126
SA126
.
.
.
SC1
SB1
SA1
SC0
SB0
SA0
COM0
COM2
.
.
.
COM124
COM126
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
SSD1357
Rev 1.1
P 7/36
Apr 2019
Solomon Systech
5 PIN DESCRIPTION
Key:
Pin Name
VDD
VCC
Vp
T0
T1
Vpp
BGGND
VSS
VLSS
VSL
VLH
VLL
VCOMH
VBREF
O
I = Input
O =Output
I/O = Bi-directional (input/output) Pull HIGH= connect to VDD
P = Power pin
NC = Not Connected
Pull LOW= connect to Ground
Table 5-1: Pin description
Pin Type Description
P
P
P
P
P
P
P
P
P
P
P
P
P
Power supply pin for core logic operation. A capacitor should be connected between
this pin and VSS.
Power supply for panel driving voltage. This is also the most positive power voltage
supply pin.
A capacitor should be connected between this pin and VSS.
This pin is the segment pre-charge voltage reference pin.
A capacitor can be connected between this pin and VSS to improve vision
performance.
No external power supply is allowed to connect to this pin.
Reserved pin. This pin should be kept NC
Reserved pin. This pin should be kept NC
Reserved pin. It must be connected to VDD.
Reserved pin. It must be connected to VSS.
Ground pin. It must be connected to external ground.
Analog system ground pin. It must be connected to external ground.
This is segment voltage (output low level) reference pin.
This pin has to connect with resistor and diode to ground (details depends on
application).
Logic high (same voltage level as VDD) for internal connection of input and I/O pins.
No need to connect to external power source.
Logic low (same voltage level as VSS) for internal connection of input and I/O pins.
No need to connect to external ground.
COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
This is a reserved pin. It should be kept NC.
Solomon Systech
Apr 2019 P 8/36
Rev 1.1 SSD1357
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