Table 1. Device summary
1 Block diagrams
Figure 1. Device architecture block diagram
Figure 2. Digital logic
2 Pin description
Figure 3. Pin connections (bottom view)
Table 2. Pin description
3 Mechanical and electrical specifications
3.1 Mechanical characteristics
Table 3. Pressure and temperature sensor characteristics
3.2 Electrical characteristics
Table 4. Electrical characteristics
Table 5. DC characteristics
3.3 Communication interface characteristics
3.3.1 SPI - serial peripheral interface
Table 6. SPI slave timing values
Figure 4. SPI slave timing diagram
3.3.2 I2C - inter-IC control interface
Table 7. I2C slave timing values
Figure 5. I2C slave timing diagram
3.4 Absolute maximum ratings
Table 8. Absolute maximum ratings
4 Functionality
4.1 Sensing element
4.2 IC interface
4.3 Factory calibration
4.4 Interpreting pressure readings
Figure 6. Pressure readings
5 FIFO
5.1 Bypass mode
Figure 7. Bypass mode
5.2 FIFO mode
Figure 8. FIFO mode
5.3 Stream mode
Figure 9. Stream mode
5.4 Dynamic-Stream mode
Figure 10. Dynamic-Stream mode
5.5 Stream-to-FIFO mode
Figure 11. Stream-to-FIFO mode
5.6 Bypass-to-Stream mode
Figure 12. Bypass-to-Stream mode
5.7 Bypass-to-FIFO mode
Figure 13. Bypass-to-FIFO mode
5.8 Retrieving data from FIFO
6 Application hints
Figure 14. LPS22HB electrical connections (top view)
6.1 Soldering information
7 Digital interfaces
7.1 Serial interfaces
Table 9. Serial interface pin description
7.2 I2C serial interface (CS = High)
Table 10. I2C terminology
7.2.1 I2C operation
Table 11. SAD+Read/Write patterns
Table 12. Transfer when master is writing one byte to slave
Table 13. Transfer when master is writing multiple bytes to slave
Table 14. Transfer when master is receiving (reading) one byte of data from slave
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
7.3 SPI bus interface
Figure 15. Read and write protocol
7.3.1 SPI read
Figure 16. SPI read protocol
Figure 17. Multiple byte SPI read protocol (2-byte example)
7.3.2 SPI write
Figure 18. SPI write protocol
Figure 19. Multiple byte SPI write protocol (2-byte example)
7.3.3 SPI read in 3-wire mode
Figure 20. SPI read protocol in 3-wire mode
8 Register mapping
Table 16. Registers address map
9 Register description
9.1 INTERRUPT_CFG (0Bh)
Figure 21. “Threshold based” interrupt event
9.2 THS_P_L (0Ch)
9.3 THS_P_H (0Dh)
9.4 WHO_AM_I (0Fh)
9.5 CTRL_REG1 (10h)
Table 17. Output data rate bit configurations
Table 18. Low-pass filter configurations
9.6 CTRL_REG2 (11h)
9.7 CTRL_REG3 (12h)
Table 19. Interrupt configurations
Figure 22. Interrupt events on INT_DRDY pin
9.8 FIFO_CTRL (14h)
Table 20. FIFO mode selection
9.9 REF_P_XL (15h)
9.10 REF_P_L (16h)
9.11 REF_P_H (17h)
9.12 RPDS_L (18h)
9.13 RPDS_H (19h)
9.14 RES_CONF (1Ah)
9.15 INT_SOURCE (25h)
9.16 FIFO_STATUS (26h)
Table 21. FIFO_STATUS example: OVR/FSS details
9.17 STATUS (27h)
9.18 PRESS_OUT_XL (28h)
9.19 PRESS_OUT_L (29h)
9.20 PRESS_OUT_H (2Ah)
9.21 TEMP_OUT_L (2Bh)
9.22 TEMP_OUT_H (2Ch)
9.23 LPFP_RES (33h)
10 Package information
10.1 HLGA-10L package information
Figure 23. HLGA-10L (2.0 x 2.0 x 0.76 mm typ.) package outline and mechanical dimensions
11 Revision history
Table 22. Document revision history