1.Introduction
2.Features
3.Block Diagram
4.Pin Function
4.1Power Supply Pins
4.2Interface Logic Pins
4.3Driver Output Pins
4.4Test and other pins
5.Pad Arrangement
5.1Output Bump Dimension
5.2Input Bump Dimension
5.3Alignment Mark Dimension
5.4Chip Information
6 PAD CENTER COORDINATES
7.Command
7.1Public command
7.1.1no operation (00h)
7.1.2read display ID (04h)
7.1.3read display status (09h)
7.1.4read display power mode (0Ah)
7.1.5read display MADCTL (0Bh)
7.1.6read display pixel format (0Ch)
7.1.7read display image mode (0Dh)
7.1.8read display signal mode (0Eh)
7.1.9read display self-diagnostic result (0Fh)
7.1.10sleep in (10h)
7.1.11sleep out (11h)
7.1.12partial mode on (12h)
7.1.13normal mode on and partial mode off (13h)
7.1.14display inversion off (20h)
7.1.15display inversion on (21h)
7.1.16display off (28h)
7.1.17display on (29h)
7.1.18column address (2Ah)
7.1.19page address (2Bh)
7.1.20memory write (2Ch)
7.1.21partial area (30h)
7.1.22vertical scrolling (33h)
7.1.23tearing effect line off (34h)
7.1.24tearing effect line on (35h)
7.1.25MADCTL(memory data access control) (36h)
7.1.26vertical scrolling start address (37h)
7.1.27idle mode off (38h)
7.1.28idle mode on and other mode off (39h)
7.1.29pixel format (3Ah)
7.1.30write memory continue (3Ch)
7.1.31set tear scanline (44h)
7.1.32get tear scan line (45h)
7.1.33write display brightess (53h)
7.1.34read display brightess (54h)
7.1.35read idd3 (D3h)
7.1.36read display id 1 (DAh)
7.1.37read display id 2 (DBh)
7.1.38read display id 3 (DCh)
7.2Private command
7.2.1osc setting (60h)
7.2.2dvdd setting (61h)
7.2.3bias setting (62h)
7.2.4vgl setting(63h)
7.2.5vgh setting (64h)
7.2.6vsp setting (65h)
7.2.7vsn setting (66h)
7.2.8pump clock sel (67h)
7.2.9gamma ref 1 (68h)
7.2.10OTP setting (6ch)
7.2.11lvd setting (6dh)
7.2.12RGB interface control (B0h)
7.2.13frame rate (B1h)
7.2.14display pol control (B4h)
7.2.15blanking porch (B5h)
7.2.16display function (B6h)
7.2.17entry mode set (B7h)
7.2.18OTP_CTRL0 (C2h)
7.2.19OTP_CTRL1 (C3h)
7.2.20 OTP_CTRL2 (C4h)
7.2.21 OTP_CTRL3(C6h)
7.2.22 OTP_CTRL4 (C7h)
7.2.23 OTP_CTRL5(C8h)
7.2.24 OTP_CTRL8 (C9h)
7.2.25 OTP_CTRL6(CAh)
7.2.26gamma positive 1 (E0h)
7.2.27gamma positive 2 (E1h)
7.2.28gamma positive 3 (E2h)
7.2.29gamma negative 1 (E3h)
7.2.30gamma negative 2 (E4h)
7.2.31gamma negative 3 (E5h)
7.2.32SRC_CTRL1 (E6h)
7.2.33SRC_CTRL2 (E7h)
7.2.34SRC_CTRL3 (E8h)
7.2.35Charge Share (E9h)
7.2.36SRC_CTRL4 (EAh)
7.2.37Gate driver timing (ECh)
7.2.38tearing effect (F1h)
7.2.39led (F2h)
7.2.40tearing effect (F4h)
7.2.41Interface control (F6h)
7.2.42 color palette enable (FBh)
7.2.43 color palette data (FCh)
7.2.44Private access (FDh)
8.Functional description
8.1Interface
8.1.1Serial Interface
8.1.1.1Write Cycle Sequence
8.1.1.2Read Cycle Sequence
8.1.1.3Data Transfer Break and Recovery
8.1.1.4Data Transfer Pause
8.1.1.52 data lane serial interface
8.1.2Parallel Interface
8.1.2.1Write Cycle/Sequence
8.1.2.2Read Cycle/Sequence
8.1.2.3Display Module Data Transfer Break
8.1.2.4Display Module Data Transfer Pause
8.1.2.5Display Module Data Transfer Modes
8.1.2.5.1Method 1
8.1.2.5.2Method 2
8.1.3RGB Interface
8.1.3.1RGB interface Selection
8.1.3.2RGB Interface Definition
8.1.3.3RGB Interface Mode Selection
8.1.3.4RGB Interface Timing Diagram
8.2Display Data RAM
8.2.1Configuration
8.2.2Memory to Display Address Mapping
8.2.2.1Normal Display On or Partial Mode On, Vertical Scr
8.2.2.2Vertical Scroll Mode
8.2.2.3Vertical Scroll example
8.2.3MPU to memory write/read direction
8.3Display Data Format
8.3.13-wire Serial Interface
8.3.24-wire Serial Interface
8.3.32 data lane serial interface
8.3.4Parallel Interface
8.3.4.18080-Ⅰ series 8-bit Parallel Interface
8.3.4.1.116-bit/pixel
8.3.4.1.218-bit/pixel
8.3.4.28080-Ⅱ series 8-bit Parallel Interface
8.3.4.2.116-bit/pixel
8.3.4.2.218-bit/pixel
8.3.4.38080-Ⅰ series 16-Bit Parallel Interface
8.3.4.3.116-bit/pixel
8.3.4.3.2 18-bit/pixel(MDT[1:0]=”00b”)
8.3.4.3.3 18-bit/pixel(MDT[1:0]=”01b”)
8.3.4.3.4 18-bit/pixel(MDT[1:0]=”10b”)
8.3.4.3.5 18-bit/pixel (MDT[1:0]=”11b”)
8.3.4.48080-Ⅱ series 16-Bit Parallel Interface
8.3.4.4.116-bit/pixel
8.3.4.4.2 18-bit/pixel(MDT[1:0]=”00b”)
8.3.4.4.3 18-bit/pixel(MDT[1:0]=”01b”)
8.3.4.4.4 18-bit/pixel(MDT[1:0]=”10b”)
8.3.4.4.5 18-bit/pixel(MDT[1:0]=”11b”)
8.3.4.58080-Ⅰ series 9-Bit Parallel Interface
8.3.4.5.116-bit/pixel
8.3.4.5.2 18-bit/pixel(MDT[1:0]=”00b”)
8.3.4.5.3 18-bit/pixel(MDT[1:0]=”01b”)
8.3.4.68080-Ⅱ series 9-bit Parallel Interface
8.3.4.6.116-bit/pixel
8.3.4.6.2 18-bit/pixel(MDT[1:0]=”00b”)
8.3.4.6.3 18-bit/pixel(MDT[1:0]=”01b”)
8.3.4.78080-Ⅰ series 18-Bit Parallel Interface
8.3.4.7.116-bit/pixel
8.3.4.7.218-bit/pixel
8.3.4.88080-Ⅱ series 18-Bit Parallel Interface
8.3.4.8.116-bit/pixel
8.3.4.8.218-bit/pixel
8.3.4.9Read Memory Data Color Coding
8.3.4.9.18 Data Line Parallel Interface I
8.3.4.9.29 Data Line Parallel Interface I
8.3.4.9.316 Data Line Parallel Interface I
8.3.4.9.418 Data Line Parallel Interface I & II
8.3.5RGB Interface
8.3.5.116-bit RGB interface
8.3.5.218-bit RGB interface
8.3.5.36-bit RGB interface
8.4Tearing effect output line
8.4.1Tearing Effect line Modes
8.4.2Tearing Effect line Timings
8.5Power On/Off Sequence
8.5.1Power On/Off Sequence
8.5.1.1Case 1 – RESX line is held high or Unstable by MPU
8.5.1.2Case 2 – RESX line is held low by MPU at Power On
8.6Power Level Definition
8.6.1Power levels
8.6.2Power flow chart
8.78-color Display Mode
8.8Gamma Correction
8.8.1Gamma-characteristics adjustment registers
8.8.2Gamma resister stream
8.8.3Variable resister
8.8.4The grayscale levels are determined by the followi
8.9Voltage Generation
8.10Relationship about source voltage
8.11Applied Voltage to the TFT panel
8.12Reset Timing
9.Application
10.Electrical Characteristics
10.1Absolute Maximum Ratings
10.2DC Characteristic
10.3AC Characteristics
10.3.1Serial Interface Timing Characteristics (3/4-wire
10.3.2Parallel Interface Timing Characteristics(8080 ser
10.3.3RGB Interface Timing Characteristics