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INTEGRATED CIRCUITS DATA SHEET PCF8574 Remote 8-bit I/O expander for I2C-bus Product speciﬁcation Supersedes data of 2002 Jul 29 2002 Nov 22

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 8 9 10 11 12 13 13.1 13.2 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.3.3 13.4 14 15 16 17 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING DIP16 and SO16 packages SSOP20 package CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge FUNCTIONAL DESCRIPTION Addressing Interrupt output Quasi-bidirectional I/Os LIMITING VALUES HANDLING DC CHARACTERISTICS I2C-BUS TIMING CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction Through-hole mount packages Soldering by dipping or by solder wave Manual soldering Surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of IC packages for wave, reflow and dipping soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2002 Nov 22 2

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 FEATURES 1 • Operating supply voltage 2.5 to 6 V • Low standby current consumption of 10 m A maximum • I2C-bus to parallel port expander • Open-drain interrupt output • 8-bit remote I/O port for the I2C-bus • Compatible with most microcontrollers • Latched outputs with high current drive capability for directly driving LEDs • Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A) • DIP16, or space-saving SO16 or SSOP20 packages. 2 GENERAL DESCRIPTION The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus). 3 ORDERING INFORMATION The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device. The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.10. TYPE NUMBER PCF8574P; PCF8574AP PCF8574T; PCF8574AT PCF8574TS; PCF8574ATS PACKAGE DESCRIPTION plastic dual in-line package; 16 leads (300 mil) NAME DIP16 VERSION SOT38-4 SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 2002 Nov 22 3

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 4 BLOCK DIAGRAM handbook, full pagewidth 13 1 2 3 14 15 INT A0 A1 A2 SCL SDA INTERRUPT LOGIC LP FILTER PCF8574 INPUT FILTER 2 I C BUS CONTROL SHIFT REGISTER 8 BIT I/O PORT 16 8 VDD VSS POWER-ON RESET WRITE pulse READ pulse 4 5 6 7 9 10 11 12 P0 P1 P2 P3 P4 P5 P6 P7 MBD980 Fig.1 Block diagram (pin numbers apply to DIP16 and SO16 packages). 2002 Nov 22 4

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 5 PINNING 5.1 DIP16 and SO16 packages SYMBOL A0 A1 A2 P0 P1 P2 P3 VSS P4 P5 P6 P7 INT SCL SDA VDD handbook, halfpage DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 address input 0 address input 1 address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 interrupt output (active LOW) serial clock line serial data line supply voltage A0 A1 A2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8 PCF8574P PCF8574AP 16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4 handbook, halfpage A0 A1 A2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8 PCF8574T PCF8574AT 16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4 MBD979 MCE001 Fig.2 Pin configuration (DIP16). Fig.3 Pin configuration (SO16). 2002 Nov 22 5

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 5.2 SSOP20 package SYMBOL INT SCL n.c. SDA VDD A0 A1 n.c. A2 P0 P1 P2 n.c. P3 VSS P4 P5 n.c. P6 P7 handbook, halfpage DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 interrupt output (active LOW) serial clock line not connected serial data line supply voltage address input 0 address input 1 not connected address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 not connected quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 not connected quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 INT SCL n.c. SDA VDD A0 A1 n.c. A2 1 2 3 4 5 6 7 8 9 P0 10 20 P7 19 P6 18 n.c. 17 P5 16 P4 15 VSS 14 P3 13 n.c. 12 P2 11 P1 PCF8574TS PCF8574ATS MBD978 Fig.4 Pin configuration (SSOP20). 2002 Nov 22 6

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 6 CHARACTERISTICS OF THE I2C-BUS 6.2 Start and stop conditions The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 6.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.5). Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.6). 6.3 System conﬁguration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.7). handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.5 Bit transfer. MBC621 handbook, full pagewidth SDA SCL S START condition SDA SCL P STOP condition MBC622 Fig.6 Definition of start and stop conditions. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER Fig.7 System configuration. MBA605 2002 Nov 22 7

Philips Semiconductors Remote 8-bit I/O expander for I2C-bus Product speciﬁcation PCF8574 6.4 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.8). The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START condition not acknowledge acknowledge 1 2 8 9 clock pulse for acknowledgement MBC602 Fig.8 Acknowledgment on the I2C-bus. 2002 Nov 22 8

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