STM32F103x8B数据手册（英文）.pdf

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Table 1. Device summary

1 Introduction

2 Description

2.1 Device overview

Table 2. STM32F103xx medium-density device features and peripheral counts

Figure 1. STM32F103xx performance line block diagram

Figure 2. Clock tree

2.2 Full compatibility throughout the family

Table 3. STM32F103xx family

2.3 Overview

2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM

2.3.2 Embedded Flash memory

2.3.3 CRC (cyclic redundancy check) calculation unit

2.3.4 Embedded SRAM

2.3.5 Nested vectored interrupt controller (NVIC)

2.3.6 External interrupt/event controller (EXTI)

2.3.7 Clocks and startup

2.3.8 Boot modes

2.3.9 Power supply schemes

2.3.10 Power supply supervisor

2.3.11 Voltage regulator

2.3.12 Low-power modes

2.3.13 DMA

2.3.14 RTC (real-time clock) and backup registers

2.3.15 Timers and watchdogs

Table 4. Timer feature comparison

2.3.16 I²C bus

2.3.17 Universal synchronous/asynchronous receiver transmitter (USART)

2.3.18 Serial peripheral interface (SPI)

2.3.19 Controller area network (CAN)

2.3.20 Universal serial bus (USB)

2.3.21 GPIOs (general-purpose inputs/outputs)

2.3.22 ADC (analog-to-digital converter)

2.3.23 Temperature sensor

2.3.24 Serial wire JTAG debug port (SWJ-DP)

3 Pinouts and pin description

Figure 3. STM32F103xx performance line LFBGA100 ballout

Figure 4. STM32F103xx performance line LQFP100 pinout

Figure 5. STM32F103xx performance line UFBGA100 pinout

Figure 6. STM32F103xx performance line LQFP64 pinout

Figure 7. STM32F103xx performance line TFBGA64 ballout

Figure 8. STM32F103xx performance line LQFP48 pinout

Figure 9. STM32F103xx performance line UFQFPN48 pinout

Figure 10. STM32F103xx performance line VFQFPN36 pinout

Table 5. Medium-density STM32F103xx pin definitions

4 Memory mapping

Figure 11. Memory map

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

Figure 12. Pin loading conditions

Figure 13. Pin input voltage

5.1.6 Power supply scheme

Figure 14. Power supply scheme

5.1.7 Current consumption measurement

Figure 15. Current consumption measurement scheme

5.2 Absolute maximum ratings

Table 6. Voltage characteristics

Table 7. Current characteristics

Table 8. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 9. General operating conditions

5.3.2 Operating conditions at power-up / power-down

Table 10. Operating conditions at power-up / power-down

5.3.3 Embedded reset and power control block characteristics

Table 11. Embedded reset and power control block characteristics

5.3.4 Embedded reference voltage

Table 12. Embedded internal reference voltage

5.3.5 Supply current characteristics

Table 13. Maximum current consumption in Run mode, code with data processing running from Flash

Table 14. Maximum current consumption in Run mode, code with data processing running from RAM

Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled

Figure 17. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled

Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM

Table 16. Typical and maximum current consumptions in Stop and Standby modes

Figure 18. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values

Figure 19. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V

Figure 20. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V

Figure 21. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V

Table 17. Typical current consumption in Run mode, code with data processing running from Flash

Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM

Table 19. Peripheral current consumption

5.3.6 External clock source characteristics

Table 20. High-speed external user clock characteristics

Table 21. Low-speed external user clock characteristics

Figure 22. High-speed external clock source AC timing diagram

Figure 23. Low-speed external clock source AC timing diagram

Table 22. HSE 4-16 MHz oscillator characteristics

Figure 24. Typical application with an 8 MHz crystal

Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)

Figure 25. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

Table 24. HSI oscillator characteristics

Table 25. LSI oscillator characteristics

Table 26. Low-power mode wakeup timings

5.3.8 PLL characteristics

Table 27. PLL characteristics

5.3.9 Memory characteristics

Table 28. Flash memory characteristics

Table 29. Flash memory endurance and data retention

5.3.10 EMC characteristics

Table 30. EMS characteristics

Table 31. EMI characteristics

5.3.11 Absolute maximum ratings (electrical sensitivity)

Table 32. ESD absolute maximum ratings

Table 33. Electrical sensitivities

5.3.12 I/O current injection characteristics

Table 34. I/O current injection susceptibility

5.3.13 I/O port characteristics

Table 35. I/O static characteristics

Figure 26. Standard I/O input characteristics - CMOS port

Figure 27. Standard I/O input characteristics - TTL port

Figure 28. 5 V tolerant I/O input characteristics - CMOS port

Figure 29. 5 V tolerant I/O input characteristics - TTL port

Table 36. Output voltage characteristics

Table 37. I/O AC characteristics

Figure 30. I/O AC characteristics definition

5.3.14 NRST pin characteristics

Table 38. NRST pin characteristics

Figure 31. Recommended NRST pin protection

5.3.15 TIM timer characteristics

Table 39. TIMx characteristics

5.3.16 Communications interfaces

Table 40. I2C characteristics

Figure 32. I2C bus AC waveforms and measurement circuit

Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V)

Table 42. SPI characteristics

Figure 33. SPI timing diagram - slave mode and CPHA = 0

Figure 34. SPI timing diagram - slave mode and CPHA = 1(1)

Figure 35. SPI timing diagram - master mode(1)

Table 43. USB startup time

Table 44. USB DC electrical characteristics

Figure 36. USB timings: definition of data signal rise and fall time

Table 45. USB: Full-speed electrical characteristics

5.3.17 CAN (controller area network) interface

5.3.18 12-bit ADC characteristics

Table 46. ADC characteristics

Table 47. RAIN max for fADC = 14 MHz

Table 48. ADC accuracy - limited test conditions

Table 49. ADC accuracy

Figure 37. ADC accuracy characteristics

Figure 38. Typical connection diagram using the ADC

Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA)

Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA)

5.3.19 Temperature sensor characteristics

Table 50. TS characteristics

6 Package information

6.1 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package information

Figure 41. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline

Table 51. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data

Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint

Figure 43. VFPFPN36 package top view example

6.2 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information

Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

Table 52. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data

Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint

Figure 46. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example

6.3 LFBGA100 10 x 10 mm, low-profile fine pitch ball grid array package information

Figure 47. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x10 mm, 0.8 mm pitch, package outline

Table 53. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data

Figure 48. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint

Table 54. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)

Figure 49. LFBGA100 package top view example

6.4 LQFP100 14 x 14 mm, 100-pin low-profile quad flat package information

Figure 50. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline

Table 55. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data

Figure 51. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package recommended footprint

Figure 52. LQFP100 package top view example

6.5 UFBGA100 7x 7 mm, ultra fine pitch ball grid array package information

Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline

Table 56. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data

Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint

Table 57. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)

Figure 55. UFBGA100 package top view example

6.6 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information

Figure 56. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

Table 58. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data

Figure 57. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

Figure 58. LQFP64 package top view example

6.7 TFBGA64 5 x 5 mm, thin profile fine pitch package information

Figure 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline

Table 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data

Figure 60. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package recommended footprint

Table 60. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)

Figure 61. TFBGA64 package top view example

6.8 LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information

Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data

Figure 63. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

Figure 64. LQFP48 package top view example

6.9 Thermal characteristics

Table 62. Package thermal characteristics

6.9.1 Reference document

6.9.2 Selecting the product temperature range

Figure 65. LQFP100 PD max vs. TA

7 Ordering information scheme

Table 63. Ordering information scheme

8 Revision history

Table 64. Document revision history

STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM • Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration • Low-power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers • 2 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor • DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs • Up to 80 fast I/O ports – 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant VFQFPN36 6 × 6 mm UFQFPN48 7 × 7 mm BGA100 10 × 10 mm UFBGA100 7 x 7 mm BGA64 5 × 5 mm • Debug mode LQFP100 14 × 14 mm LQFP64 10 × 10 mm LQFP48 7 × 7 mm – Serial wire debug (SWD) & JTAG interfaces • 7 timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with dead- time generation and emergency stop – 2 watchdog timers (Independent and Window) – SysTick timer 24-bit downcounter • Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface • CRC calculation unit, 96-bit unique ID • Packages are ECOPACK® Table 1. Device summary Part number Reference STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB, STM32F103TB August 2015 This is information on a product in full production. DocID13587 Rev 17 1/117 www.st.com

Contents Contents STM32F103x8, STM32F103xB 1 2 3 4 2/117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 14 2.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.4 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.11 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.16 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID13587 Rev 17

STM32F103x8, STM32F103xB Contents 5 6 5.2 5.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.3 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.5 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39 5.3.2 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 40 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.5 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.7 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.8 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.10 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 60 5.3.11 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.14 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.17 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.19 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package information . . . . . . . . . . . 80 6.1 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . . 84 6.2 LFBGA100 10 x 10 mm, low-profile fine pitch ball grid array 6.3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DocID13587 Rev 17 3/117 4

Contents STM32F103x8, STM32F103xB 6.4 6.5 6.6 6.7 6.8 6.9 LQFP100 14 x 14 mm, 100-pin low-profile quad flat package information 90 UFBGA100 7x 7 mm, ultra fine pitch ball grid array package information 93 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information . . 96 TFBGA64 5 x 5 mm, thin profile fine pitch package information . . . . . . . 99 LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information . . . 102 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.9.1 6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 106 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7 8 4/117 DocID13587 Rev 17

STM32F103x8, STM32F103xB List of tables List of tables Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 Table 2. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8. Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 11. Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 13. Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 14. Maximum current consumption in Run mode, code with data processing Table 18. running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 44 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 45 Table 16. Typical current consumption in Run mode, code with data processing Table 17. running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 21. HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 34. Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 36. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 37. Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 39. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 40. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 41. Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 43. Table 44. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DocID13587 Rev 17 5/117 6

List of tables STM32F103x8, STM32F103xB Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 RAIN max for fADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . . 88 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 90 UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 94 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 100 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 62. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 63. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 64. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 52. Table 53. Table 60. Table 61. 6/117 DocID13587 Rev 17

STM32F103x8, STM32F103xB List of figures List of figures STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 1. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3. STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. STM32F103xx performance line UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5. STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6. STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7. STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8. Figure 9. STM32F103xx performance line UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 12. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 43 Figure 17. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 43 Figure 18. Typical current consumption on VBAT with RTC on versus temperature at different Figure 19. Typical current consumption in Stop mode with regulator in Run mode versus VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 20. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 23. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 26. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 27. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 28. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 29. Figure 30. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 31. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 32. Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 35. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 36. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 37. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 38. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 78 Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 79 Figure 41. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DocID13587 Rev 17 7/117 8

List of figures STM32F103x8, STM32F103xB Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 43. VFPFPN36 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 46. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . . 86 Figure 47. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 LFBGA100 package top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 90 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LQFP100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 52. Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid Figure 48. Figure 49. Figure 50. Figure 51. array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 55. UFBGA100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 96 Figure 56. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package Figure 57. recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 58. Figure 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 60. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 61. TFBGA64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 102 Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package Figure 63. recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 64. Figure 65. 8/117 DocID13587 Rev 17

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