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ESP32-S3技术参考手册（英文）(文件:Esp32-s3_technical_reference_manual_en).pdf
1 Processor Instruction Extensions (PIE)
1.1 Overview
1.2 Features
1.3 Structure Overview
1.3.1 Bank of Vector Registers
1.3.2 ALU
1.3.3 QACC Accumulator Register
1.3.4 ACCX Accumulator Register
1.3.5 Address Unit
1.4 Syntax Description
1.4.1 Bit/Byte Order
1.4.2 Instruction Field Definition
1.5 Components of Extended Instruction Set
1.5.1 Registers
1.5.2 Fast GPIO Interface
1.5.3 Data Format and Alignment
1.5.4 Data Overflow and Saturation Handling
1.6 Extended Instruction List
1.6.1 Read Instructions
1.6.2 Write Instructions
1.6.3 Data Exchange Instructions
1.6.4 Arithmetic Instructions
1.6.5 Comparison Instructions
1.6.6 Bitwise Logical Instructions
1.6.7 Shift Instructions
1.6.8 FFT Dedicated Instructions
1.6.9 GPIO Control Instructions
1.6.10 Processor Control Instructions
1.7 Instruction Performance
1.7.1 Data Hazard
1.7.2 Hardware Resource Hazard
1.7.3 Control Hazard
1.8 Extended Instruction Functional Description
1.8.1 EE.ANDQ
1.8.2 EE.BITREV
1.8.3 EE.CLR_BIT_GPIO_OUT
1.8.4 EE.CMUL.S16
1.8.5 EE.CMUL.S16.LD.INCP
1.8.6 EE.CMUL.S16.ST.INCP
1.8.7 EE.FFT.AMS.S16.LD.INCP
1.8.8 EE.FFT.AMS.S16.LD.INCP.UAUP
1.8.9 EE.FFT.AMS.S16.LD.R32.DECP
1.8.10 EE.FFT.AMS.S16.ST.INCP
1.8.11 EE.FFT.CMUL.S16.LD.XP
1.8.12 EE.FFT.CMUL.S16.ST.XP
1.8.13 EE.FFT.R2BF.S16
1.8.14 EE.FFT.R2BF.S16.ST.INCP
1.8.15 EE.FFT.VST.R32.DECP
1.8.16 EE.GET_GPIO_IN
1.8.17 EE.LD.128.USAR.IP
1.8.18 EE.LD.128.USAR.XP
1.8.19 EE.LD.ACCX.IP
1.8.20 EE.LD.QACC_H.H.32.IP
1.8.21 EE.LD.QACC_H.L.128.IP
1.8.22 EE.LD.QACC_L.H.32.IP
1.8.23 EE.LD.QACC_L.L.128.IP
1.8.24 EE.LD.UA_STATE.IP
1.8.25 EE.LDF.128.IP
1.8.26 EE.LDF.128.XP
1.8.27 EE.LDF.64.IP
1.8.28 EE.LDF.64.XP
1.8.29 EE.LDQA.S16.128.IP
1.8.30 EE.LDQA.S16.128.XP
1.8.31 EE.LDQA.S8.128.IP
1.8.32 EE.LDQA.S8.128.XP
1.8.33 EE.LDQA.U16.128.IP
1.8.34 EE.LDQA.U16.128.XP
1.8.35 EE.LDQA.U8.128.IP
1.8.36 EE.LDQA.U8.128.XP
1.8.37 EE.LDXQ.32
1.8.38 EE.MOV.S16.QACC
1.8.39 EE.MOV.S8.QACC
1.8.40 EE.MOV.U16.QACC
1.8.41 EE.MOV.U8.QACC
1.8.42 EE.MOVI.32.A
1.8.43 EE.MOVI.32.Q
1.8.44 EE.NOTQ
1.8.45 EE.ORQ
1.8.46 EE.SET_BIT_GPIO_OUT
1.8.47 EE.SLCI.2Q
1.8.48 EE.SLCXXP.2Q
1.8.49 EE.SRC.Q
1.8.50 EE.SRC.Q.LD.IP
1.8.51 EE.SRC.Q.LD.XP
1.8.52 EE.SRC.Q.QUP
1.8.53 EE.SRCI.2Q
1.8.54 EE.SRCMB.S16.QACC
1.8.55 EE.SRCMB.S8.QACC
1.8.56 EE.SRCQ.128.ST.INCP
1.8.57 EE.SRCXXP.2Q
1.8.58 EE.SRS.ACCX
1.8.59 EE.ST.ACCX.IP
1.8.60 EE.ST.QACC_H.H.32.IP
1.8.61 EE.ST.QACC_H.L.128.IP
1.8.62 EE.ST.QACC_L.H.32.IP
1.8.63 EE.ST.QACC_L.L.128.IP
1.8.64 EE.ST.UA_STATE.IP
1.8.65 EE.STF.128.IP
1.8.66 EE.STF.128.XP
1.8.67 EE.STF.64.IP
1.8.68 EE.STF.64.XP
1.8.69 EE.STXQ.32
1.8.70 EE.VADDS.S16
1.8.71 EE.VADDS.S16.LD.INCP
1.8.72 EE.VADDS.S16.ST.INCP
1.8.73 EE.VADDS.S32
1.8.74 EE.VADDS.S32.LD.INCP
1.8.75 EE.VADDS.S32.ST.INCP
1.8.76 EE.VADDS.S8
1.8.77 EE.VADDS.S8.LD.INCP
1.8.78 EE.VADDS.S8.ST.INCP
1.8.79 EE.VCMP.EQ.S16
1.8.80 EE.VCMP.EQ.S32
1.8.81 EE.VCMP.EQ.S8
1.8.82 EE.VCMP.GT.S16
1.8.83 EE.VCMP.GT.S32
1.8.84 EE.VCMP.GT.S8
1.8.85 EE.VCMP.LT.S16
1.8.86 EE.VCMP.LT.S32
1.8.87 EE.VCMP.LT.S8
1.8.88 EE.VLD.128.IP
1.8.89 EE.VLD.128.XP
1.8.90 EE.VLD.H.64.IP
1.8.91 EE.VLD.H.64.XP
1.8.92 EE.VLD.L.64.IP
1.8.93 EE.VLD.L.64.XP
1.8.94 EE.VLDBC.16
1.8.95 EE.VLDBC.16.IP
1.8.96 EE.VLDBC.16.XP
1.8.97 EE.VLDBC.32
1.8.98 EE.VLDBC.32.IP
1.8.99 EE.VLDBC.32.XP
1.8.100 EE.VLDBC.8
1.8.101 EE.VLDBC.8.IP
1.8.102 EE.VLDBC.8.XP
1.8.103 EE.VLDHBC.16.INCP
1.8.104 EE.VMAX.S16
1.8.105 EE.VMAX.S16.LD.INCP
1.8.106 EE.VMAX.S16.ST.INCP
1.8.107 EE.VMAX.S32
1.8.108 EE.VMAX.S32.LD.INCP
1.8.109 EE.VMAX.S32.ST.INCP
1.8.110 EE.VMAX.S8
1.8.111 EE.VMAX.S8.LD.INCP
1.8.112 EE.VMAX.S8.ST.INCP
1.8.113 EE.VMIN.S16
1.8.114 EE.VMIN.S16.LD.INCP
1.8.115 EE.VMIN.S16.ST.INCP
1.8.116 EE.VMIN.S32
1.8.117 EE.VMIN.S32.LD.INCP
1.8.118 EE.VMIN.S32.ST.INCP
1.8.119 EE.VMIN.S8
1.8.120 EE.VMIN.S8.LD.INCP
1.8.121 EE.VMIN.S8.ST.INCP
1.8.122 EE.VMUL.S16
1.8.123 EE.VMUL.S16.LD.INCP
1.8.124 EE.VMUL.S16.ST.INCP
1.8.125 EE.VMUL.S8
1.8.126 EE.VMUL.S8.LD.INCP
1.8.127 EE.VMUL.S8.ST.INCP
1.8.128 EE.VMUL.U16
1.8.129 EE.VMUL.U16.LD.INCP
1.8.130 EE.VMUL.U16.ST.INCP
1.8.131 EE.VMUL.U8
1.8.132 EE.VMUL.U8.LD.INCP
1.8.133 EE.VMUL.U8.ST.INCP
1.8.134 EE.VMULAS.S16.ACCX
1.8.135 EE.VMULAS.S16.ACCX.LD.IP
1.8.136 EE.VMULAS.S16.ACCX.LD.IP.QUP
1.8.137 EE.VMULAS.S16.ACCX.LD.XP
1.8.138 EE.VMULAS.S16.ACCX.LD.XP.QUP
1.8.139 EE.VMULAS.S16.QACC
1.8.140 EE.VMULAS.S16.QACC.LD.IP
1.8.141 EE.VMULAS.S16.QACC.LD.IP.QUP
1.8.142 EE.VMULAS.S16.QACC.LD.XP
1.8.143 EE.VMULAS.S16.QACC.LD.XP.QUP
1.8.144 EE.VMULAS.S16.QACC.LDBC.INCP
1.8.145 EE.VMULAS.S16.QACC.LDBC.INCP.QUP
1.8.146 EE.VMULAS.S8.ACCX
1.8.147 EE.VMULAS.S8.ACCX.LD.IP
1.8.148 EE.VMULAS.S8.ACCX.LD.IP.QUP
1.8.149 EE.VMULAS.S8.ACCX.LD.XP
1.8.150 EE.VMULAS.S8.ACCX.LD.XP.QUP
1.8.151 EE.VMULAS.S8.QACC
1.8.152 EE.VMULAS.S8.QACC.LD.IP
1.8.153 EE.VMULAS.S8.QACC.LD.IP.QUP
1.8.154 EE.VMULAS.S8.QACC.LD.XP
1.8.155 EE.VMULAS.S8.QACC.LD.XP.QUP
1.8.156 EE.VMULAS.S8.QACC.LDBC.INCP
1.8.157 EE.VMULAS.S8.QACC.LDBC.INCP.QUP
1.8.158 EE.VMULAS.U16.ACCX
1.8.159 EE.VMULAS.U16.ACCX.LD.IP
1.8.160 EE.VMULAS.U16.ACCX.LD.IP.QUP
1.8.161 EE.VMULAS.U16.ACCX.LD.XP
1.8.162 EE.VMULAS.U16.ACCX.LD.XP.QUP
1.8.163 EE.VMULAS.U16.QACC
1.8.164 EE.VMULAS.U16.QACC.LD.IP
1.8.165 EE.VMULAS.U16.QACC.LD.IP.QUP
1.8.166 EE.VMULAS.U16.QACC.LD.XP
1.8.167 EE.VMULAS.U16.QACC.LD.XP.QUP
1.8.168 EE.VMULAS.U16.QACC.LDBC.INCP
1.8.169 EE.VMULAS.U16.QACC.LDBC.INCP.QUP
1.8.170 EE.VMULAS.U8.ACCX
1.8.171 EE.VMULAS.U8.ACCX.LD.IP
1.8.172 EE.VMULAS.U8.ACCX.LD.IP.QUP
1.8.173 EE.VMULAS.U8.ACCX.LD.XP
1.8.174 EE.VMULAS.U8.ACCX.LD.XP.QUP
1.8.175 EE.VMULAS.U8.QACC
1.8.176 EE.VMULAS.U8.QACC.LD.IP
1.8.177 EE.VMULAS.U8.QACC.LD.IP.QUP
1.8.178 EE.VMULAS.U8.QACC.LD.XP
1.8.179 EE.VMULAS.U8.QACC.LD.XP.QUP
1.8.180 EE.VMULAS.U8.QACC.LDBC.INCP
1.8.181 EE.VMULAS.U8.QACC.LDBC.INCP.QUP
1.8.182 EE.VPRELU.S16
1.8.183 EE.VPRELU.S8
1.8.184 EE.VRELU.S16
1.8.185 EE.VRELU.S8
1.8.186 EE.VSL.32
1.8.187 EE.VSMULAS.S16.QACC
1.8.188 EE.VSMULAS.S16.QACC.LD.INCP
1.8.189 EE.VSMULAS.S8.QACC
1.8.190 EE.VSMULAS.S8.QACC.LD.INCP
1.8.191 EE.VSR.32
1.8.192 EE.VST.128.IP
1.8.193 EE.VST.128.XP
1.8.194 EE.VST.H.64.IP
1.8.195 EE.VST.H.64.XP
1.8.196 EE.VST.L.64.IP
1.8.197 EE.VST.L.64.XP
1.8.198 EE.VSUBS.S16
1.8.199 EE.VSUBS.S16.LD.INCP
1.8.200 EE.VSUBS.S16.ST.INCP
1.8.201 EE.VSUBS.S32
1.8.202 EE.VSUBS.S32.LD.INCP
1.8.203 EE.VSUBS.S32.ST.INCP
1.8.204 EE.VSUBS.S8
1.8.205 EE.VSUBS.S8.LD.INCP
1.8.206 EE.VSUBS.S8.ST.INCP
1.8.207 EE.VUNZIP.16
1.8.208 EE.VUNZIP.32
1.8.209 EE.VUNZIP.8
1.8.210 EE.VZIP.16
1.8.211 EE.VZIP.32
1.8.212 EE.VZIP.8
1.8.213 EE.WR_MASK_GPIO_OUT
1.8.214 EE.XORQ
1.8.215 EE.ZERO.ACCX
1.8.216 EE.ZERO.Q
1.8.217 EE.ZERO.QACC
2 ULP Coprocessor (ULP-FSM, ULP-RISC-V)
2.1 Overview
2.2 Features
2.3 Programming Workflow
2.4 ULP Coprocessor Sleep and Weakup Workflow
2.5 ULP-FSM
2.5.1 Features
2.5.2 Instruction Set
2.6 ULP-RISC-V
2.6.1 Features
2.6.2 Multiplier and Divider
2.6.3 ULP-RISC-V Interrupts
2.7 RTC I2C Controller
2.7.1 Connecting RTC I2C Signals
2.7.2 Configuring RTC I2C
2.7.3 Using RTC I2C
2.7.4 RTC I2C Interrupts
2.8 Address Mapping
2.9 Register Summary
2.9.1 ULP (ALWAYS_ON) Register Summary
2.9.2 ULP (RTC_PERI) Register Summary
2.9.3 RTC I2C (RTC_PERI) Register Summary
2.9.4 RTC I2C (I2C) Register Summary
2.10 Registers
2.10.1 ULP (ALWAYS_ON) Registers
2.10.2 ULP (RTC_PERI) Registers
2.10.3 RTC I2C (RTC_PERI) Registers
2.10.4 RTC I2C (I2C) Registers
3 GDMA Controller (GDMA)
3.1 Overview
3.2 Features
3.3 Architecture
3.4 Functional Description
3.4.1 Linked List
3.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer
3.4.3 Memory-to-Memory Data Transfer
3.4.4 Channel Buffer
3.4.5 Enabling GDMA
3.4.6 Linked List Reading Process
3.4.7 EOF
3.4.8 Accessing Internal RAM
3.4.9 Accessing External RAM
3.4.10 External RAM Access Permissions
3.4.11 Seamless Access to Internal and External RAM
3.4.12 Arbitration
3.5 GDMA Interrupts
3.6 Programming Procedures
3.6.1 Programming Procedures for GDMA's Transmit Channel
3.6.2 Programming Procedures for GDMA's Receive Channel
3.6.3 Programming Procedures for Memory-to-Memory Transfer
3.7 Register Summary
3.8 Registers
4 System and Memory
4.1 Overview
4.2 Features
4.3 Functional Description
4.3.1 Address Mapping
4.3.2 Internal Memory
4.3.3 External Memory
4.3.4 GDMA Address Space
4.3.5 Modules/Peripherals
5 eFuse Controller
5.1 Overview
5.2 Features
5.3 Functional Description
5.3.1 Structure
5.3.2 Programming of Parameters
5.3.3 User Read of Parameters
5.3.4 eFuse VDDQ Timing
5.3.5 The Use of Parameters by Hardware Modules
5.3.6 Interrupts
5.4 Register Summary
5.5 Registers
6 IO MUX and GPIO Matrix (GPIO, IO MUX)
6.1 Overview
6.2 Features
6.3 Architectural Overview
6.4 Peripheral Input via GPIO Matrix
6.4.1 Overview
6.4.2 Signal Synchronization
6.4.3 Functional Description
6.4.4 Simple GPIO Input
6.5 Peripheral Output via GPIO Matrix
6.5.1 Overview
6.5.2 Functional Description
6.5.3 Simple GPIO Output
6.5.4 Sigma Delta Modulated Output
6.6 Direct Input and Output via IO MUX
6.6.1 Overview
6.6.2 Functional Description
6.7 RTC IO MUX for Low Power and Analog Input/Output
6.7.1 Overview
6.7.2 Low Power Capabilities
6.7.3 Analog Functions
6.8 Pin Functions in Light-sleep
6.9 Pin Hold Feature
6.10 Power Supply and Management of GPIO Pins
6.10.1 Power Supply of GPIO Pins
6.10.2 Power Supply Management
6.11 Peripheral Signals via GPIO Matrix
6.12 IO MUX Function List
6.13 RTC IO MUX Pin List
6.14 Register Summary
6.14.1 GPIO Matrix Register Summary
6.14.2 IO MUX Register Summary
6.14.3 SDM Output Register Summary
6.14.4 RTC IO MUX Register Summary
6.15 Registers
6.15.1 GPIO Matrix Registers
6.15.2 IO MUX Registers
6.15.3 SDM Output Registers
6.15.4 RTC IO MUX Registers
7 Reset and Clock
7.1 Reset
7.1.1 Overview
7.1.2 Architectural Overview
7.1.3 Features
7.1.4 Functional Description
7.2 Clock
7.2.1 Overview
7.2.2 Architectural Overview
7.2.3 Features
7.2.4 Functional Description
8 Chip Boot Control
8.1 Overview
8.2 Boot Mode Control
8.3 ROM Messages Printing Control
8.4 VDD_SPI Voltage Control
8.5 JTAG Signal Source Control
9 Interrupt Matrix (INTERRUPT)
9.1 Overview
9.2 Features
9.3 Functional Description
9.3.1 Peripheral Interrupt Sources
9.3.2 CPU Interrupts
9.3.3 Allocate Peripheral Interrupt Source to CPUx Interrupt
9.3.4 Disable CPUx NMI Interrupt
9.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
9.4 Register Summary
9.4.1 CPU0 Interrupt Register Summary
9.4.2 CPU1 Interrupt Register Summary
9.5 Registers
9.5.1 CPU0 Interrupt Registers
9.5.2 CPU1 Interrupt Registers
10 Low-power Management (RTC_CNTL)
10.1 Introduction
10.2 Features
10.3 Functional Description
10.3.1 Power Management Unit
10.3.2 Low-Power Clocks
10.3.3 Timers
10.3.4 Voltage Regulators
10.4 Power Modes Management
10.4.1 Power Domain
10.4.2 RTC States
10.4.3 Pre-defined Power Modes
10.4.4 Wakeup Source
10.4.5 Reject Sleep
10.5 Retention DMA
10.6 RTC Boot
10.7 Register Summary
10.8 Registers
11 System Timer (SYSTIMER)
11.1 Overview
11.2 Features
11.3 Clock Source Selection
11.4 Functional Description
11.4.1 Counter
11.4.2 Comparator and Alarm
11.4.3 Synchronization Operation
11.4.4 Interrupt
11.5 Programming Procedure
11.5.1 Read Current Count Value
11.5.2 Configure One-Time Alarm in Target Mode
11.5.3 Configure Periodic Alarms in Period Mode
11.5.4 Update After Deep-sleep and Light-sleep
11.6 Register Summary
11.7 Registers
12 Timer Group (TIMG)
12.1 Overview
12.2 Functional Description
12.2.1 16-bit Prescaler and Clock Selection
12.2.2 54-bit Time-base Counter
12.2.3 Alarm Generation
12.2.4 Timer Reload
12.2.5 RTC_SLOW_CLK Frequency Calculation
12.2.6 Interrupts
12.3 Configuration and Usage
12.3.1 Timer as a Simple Clock
12.3.2 Timer as One-shot Alarm
12.3.3 Timer as Periodic Alarm
12.3.4 RTC_SLOW_CLK Frequency Calculation
12.4 Register Summary
12.5 Registers
13 Watchdog Timers (WDT)
13.1 Overview
13.2 Digital Watchdog Timers
13.2.1 Features
13.2.2 Functional Description
13.3 Super Watchdog
13.3.1 Features
13.3.2 Super Watchdog Controller
13.4 Interrupts
13.5 Registers
14 XTAL32K Watchdog Timers (XTWDT)
14.1 Overview
14.2 Features
14.2.1 Interrupt and Wake-Up
14.2.2 BACKUP32K_CLK
14.3 Functional Description
14.3.1 Workflow
14.3.2 BACKUP32K_CLK Working Principle
14.3.3 Configuring the Divisor Component of BACKUP32K_CLK
15 Permission Control (PMS)
15.1 Overview
15.2 Features
15.3 Internal Memory
15.3.1 ROM
15.3.2 SRAM
15.3.3 RTC FAST Memory
15.3.4 RTC SLOW Memory
15.4 Peripherals
15.4.1 Access Configuration
15.4.2 Split Peripheral Regions into Split Regions
15.5 External Memory
15.5.1 Address
15.5.2 Access Configuration
15.5.3 GDMA
15.6 Unauthorized Access and Interrupts
15.6.1 Interrupt upon Unauthorized IBUS Access
15.6.2 Interrupt upon Unauthorized DBUS Access
15.6.3 Interrupt upon Unauthorized Access to External Memory
15.6.4 Interrupt upon Unauthorized Access to Internal Memory via GDMA
15.6.5 Interrupt upon Unauthorized peripheral bus (PIF) Access
15.6.6 Interrupt upon Unauthorized PIF Access Alignment
15.7 Protection of CPU VECBASE Registers
15.8 Register Locks
15.9 Register Summary
15.10 Registers
16 World Controller (WCL)
16.1 Introduction
16.2 Features
16.3 Functional Description
16.4 CPU's World Switch
16.4.1 From Secure World to Non-secure World
16.4.2 From Non-secure World to Secure World
16.4.3 Clearing the write_buffer
16.5 World Switch Log
16.5.1 Structure of World Switch Log Register
16.5.2 How World Switch Log Registers are Updated
16.5.3 How to Read World Switch Log Registers
16.5.4 Nested Interrupts
16.6 NMI Interrupt Masking
16.7 Register Summary
16.8 Registers
17 System Registers (SYSTEM)
17.1 Overview
17.2 Features
17.3 Function Description
17.3.1 System and Memory Registers
17.3.2 Clock Registers
17.3.3 Interrupt Signal Registers
17.3.4 Low-power Management Registers
17.3.5 Peripheral Clock Gating and Reset Registers
17.3.6 CPU Control Registers
17.4 Register Summary
17.5 Registers
18 SHA Accelerator (SHA)
18.1 Introduction
18.2 Features
18.3 Working Modes
18.4 Function Description
18.4.1 Preprocessing
18.4.2 Hash task Process
18.4.3 Message Digest
18.4.4 Interrupt
18.5 Register Summary
18.6 Registers
19 AES Accelerator (AES)
19.1 Introduction
19.2 Features
19.3 AES Working Modes
19.4 Typical AES Working Mode
19.4.1 Key, Plaintext, and Ciphertext
19.4.2 Endianness
19.4.3 Operation Process
19.5 DMA-AES Working Mode
19.5.1 Key, Plaintext, and Ciphertext
19.5.2 Endianness
19.5.3 Standard Incrementing Function
19.5.4 Block Number
19.5.5 Initialization Vector
19.5.6 Block Operation Process
19.6 Memory Summary
19.7 Register Summary
19.8 Registers
20 RSA Accelerator (RSA)
20.1 Introduction
20.2 Features
20.3 Functional Description
20.3.1 Large Number Modular Exponentiation
20.3.2 Large Number Modular Multiplication
20.3.3 Large Number Multiplication
20.3.4 Options for Acceleration
20.4 Memory Summary
20.5 Register Summary
20.6 Registers
21 HMAC Accelerator (HMAC)
21.1 Main Features
21.2 Functional Description
21.2.1 Upstream Mode
21.2.2 Downstream JTAG Enable Mode
21.2.3 Downstream Digital Signature Mode
21.2.4 HMAC eFuse Configuration
21.2.5 HMAC Initialization
21.2.6 HMAC Process (Detailed)
21.3 HMAC Algorithm Details
21.3.1 Padding Bits
21.3.2 HMAC Algorithm Structure
21.4 Register Summary
21.5 Registers
22 Digital Signature (DS)
22.1 Overview
22.2 Features
22.3 Functional Description
22.3.1 Overview
22.3.2 Private Key Operands
22.3.3 Software Prerequisites
22.3.4 DS Operation at the Hardware Level
22.3.5 DS Operation at the Software Level
22.4 Memory Summary
22.5 Register Summary
22.6 Registers
23 External Memory Encryption and Decryption (XTS_AES)
23.1 Overview
23.2 Features
23.3 Module Structure
23.4 Functional Description
23.4.1 XTS Algorithm
23.4.2 Key
23.4.3 Target Memory Space
23.4.4 Data Padding
23.4.5 Manual Encryption Block
23.4.6 Auto Encryption Block
23.4.7 Auto Decryption Block
23.5 Software Process
23.6 Register Summary
23.7 Registers
24 Clock Glitch Detection
24.1 Overview
24.2 Functional Description
24.2.1 Clock Glitch Detection
24.2.2 Reset
25 Random Number Generator (RNG)
25.1 Introduction
25.2 Features
25.3 Functional Description
25.4 Programming Procedure
25.5 Register Summary
25.6 Register
26 UART Controller (UART)
26.1 Overview
26.2 Features
26.3 UART Structure
26.4 Functional Description
26.4.1 Clock and Reset
26.4.2 UART RAM
26.4.3 Baud Rate Generation and Detection
26.4.4 UART Data Frame
26.4.5 AT_CMD Character Structure
26.4.6 RS485
26.4.7 IrDA
26.4.8 Wake-up
26.4.9 Loopback Test
26.4.10 Flow Control
26.4.11 GDMA Mode
26.4.12 UART Interrupts
26.4.13 UHCI Interrupts
26.5 Programming Procedures
26.5.1 Register Type
26.5.2 Detailed Steps
26.6 Register Summary
26.6.1 UART Register Summary
26.6.2 UHCI Register Summary
26.7 Registers
26.7.1 UART Registers
26.7.2 UHCI Regsiters
27 I2C Controller (I2C)
27.1 Overview
27.2 Features
27.3 I2C Architecture
27.4 Functional Description
27.4.1 Clock Configuration
27.4.2 SCL and SDA Noise Filtering
27.4.3 SCL Clock Stretching
27.4.4 Generating SCL Pulses in Idle State
27.4.5 Synchronization
27.4.6 Open-Drain Output
27.4.7 Timing Parameter Configuration
27.4.8 Timeout Control
27.4.9 Command Configuration
27.4.10 TX/RX RAM Data Storage
27.4.11 Data Conversion
27.4.12 Addressing Mode
27.4.13 R/W Bit Check in 10-bit Addressing Mode
27.4.14 To Start the I2C Controller
27.5 Programming Example
27.5.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence
27.5.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence
27.5.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Command Sequence
27.5.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Command Sequences
27.5.5 I2C master Reads I2C slave with a 7-bit Address in One Command Sequence
27.5.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence
27.5.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Command Sequence
27.5.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences
27.6 Interrupts
27.7 Register Summary
27.8 Registers
28 I2S Controller (I2S)
28.1 Overview
28.2 Terminology
28.3 Features
28.4 System Architecture
28.5 Supported Audio Standards
28.5.1 TDM Philips Standard
28.5.2 TDM MSB Alignment Standard
28.5.3 TDM PCM Standard
28.5.4 PDM Standard
28.6 TX/RX Clock
28.7 I2Sn Reset
28.8 I2Sn Master/Slave Mode
28.8.1 Master/Slave TX Mode
28.8.2 Master/Slave RX Mode
28.9 Transmitting Data
28.9.1 Data Format Control
28.9.2 Channel Mode Control
28.10 Receiving Data
28.10.1 Channel Mode Control
28.10.2 Data Format Control
28.11 Software Configuration Process
28.11.1 Configure I2Sn as TX Mode
28.11.2 Configure I2Sn as RX Mode
28.12 I2Sn Interrupts
28.13 Register Summary
28.14 Registers
29 LCD and Camera Controller (LCD_CAM)
29.1 Overview
29.2 Features
29.3 Functional Description
29.3.1 Block Diagram
29.3.2 Signal Description
29.3.3 LCD_CAM Module Clocks
29.3.4 LCD_CAM Reset
29.3.5 LCD_CAM Data Format Control
29.3.6 YUV-RGB Data Format Conversion
29.4 Software Configuration Process
29.4.1 Configure LCD (RGB Format) as TX Mode
29.4.2 Configure LCD (I8080/MOTO6800 Format) as TX Mode
29.4.3 Configure Camera as RX Mode
29.5 LCD_CAM Interrupts
29.6 Register Summary
29.7 Registers
30 SPI Controller (SPI)
30.1 Overview
30.2 Glossary
30.3 Features
30.4 Architectural Overview
30.5 Functional Description
30.5.1 Data Modes
30.5.2 Introduction to FSPI bus and SPI3 Bus Signals
30.5.3 Bit Read/Write Order Control
30.5.4 Transfer Modes
30.5.5 CPU-Controlled Data Transfer
30.5.6 DMA-Controlled Data Transfer
30.5.7 Data Flow Control in GP-SPI Master and Slave Modes
30.5.8 GP-SPI Works as a Master
30.5.9 GP-SPI Works as a Slave
30.6 CS Setup Time and Hold Time Control
30.7 GP-SPI Clock Control
30.7.1 Clock Phase and Polarity
30.7.2 Clock Control in Master Mode
30.7.3 Clock Control in Slave Mode
30.8 GP-SPI Timing Compensation
30.9 Differences Between GP-SPI2 and GP-SPI3
30.10 Interrupts
30.11 Register Summary
30.12 Registers
31 Two-wire Automotive Interface (TWAI®)
31.1 Overview
31.2 Features
31.3 Functional Protocol
31.3.1 TWAI Properties
31.3.2 TWAI Messages
31.3.3 TWAI Errors
31.3.4 TWAI Bit Timing
31.4 Architectural Overview
31.4.1 Registers Block
31.4.2 Bit Stream Processor
31.4.3 Error Management Logic
31.4.4 Bit Timing Logic
31.4.5 Acceptance Filter
31.4.6 Receive FIFO
31.5 Functional Description
31.5.1 Modes
31.5.2 Bit Timing
31.5.3 Interrupt Management
31.5.4 Transmit and Receive Buffers
31.5.5 Receive FIFO and Data Overruns
31.5.6 Error Management
31.5.7 Error Code Capture
31.5.8 Arbitration Lost Capture
31.6 Register Summary
31.7 Registers
32 USB On-The-Go (USB)
32.1 Overview
32.2 Features
32.2.1 General Features
32.2.2 Device Mode Features
32.2.3 Host Mode Features
32.3 Functional Description
32.3.1 Controller Core and Interfaces
32.3.2 Memory Layout
32.3.3 FIFO and Queue Organization
32.3.4 Interrupt Hierarchy
32.3.5 DMA Modes and Slave Mode
32.3.6 Transaction and Transfer Level Operation
32.4 OTG
32.4.1 OTG Interface
32.4.2 ID Pin Detection
32.4.3 Session Request Protocol (SRP)
32.4.4 Host Negotiation Protocol (HNP)
33 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
33.1 Overview
33.2 Features
33.3 Functional Description
33.3.1 USB Serial/JTAG host connection
33.3.2 CDC-ACM USB Interface Functional Description
33.3.3 CDC-ACM Firmware Interface Functional Description
33.3.4 USB-to-JTAG Interface
33.3.5 JTAG Command Processor
33.3.6 USB-to-JTAG Interface: CMD_REP usage example
33.3.7 USB-to-JTAG Interface: Response Capture Unit
33.3.8 USB-to-JTAG Interface: Control Transfer Requests
33.4 Recommended Operation
33.4.1 Internal/external PHY selection
33.4.2 Runtime operation
33.5 Register Summary
33.6 Registers
34 SD/MMC Host Controller (SDHOST)
34.1 Overview
34.2 Features
34.3 SD/MMC External Interface Signals
34.4 Functional Description
34.4.1 SD/MMC Host Controller Architecture
34.4.2 Command Path
34.4.3 Data Path
34.5 Software Restrictions for Proper CIU Operation
34.6 RAM for Receiving and Sending Data
34.6.1 TX RAM Module
34.6.2 RX RAM Module
34.7 DMA Descriptor Chain
34.8 The Structure of DMA descriptor chain
34.9 Initialization
34.9.1 DMA Initialization
34.9.2 DMA Transmission Initialization
34.9.3 DMA Reception Initialization
34.10 Clock Phase Selection
34.11 Interrupt
34.12 Register Summary
34.13 Registers
35 LED PWM Controller (LEDC)
35.1 Overview
35.2 Features
35.3 Functional Description
35.3.1 Architecture
35.3.2 Timers
35.3.3 PWM Generators
35.3.4 Duty Cycle Fading
35.3.5 Interrupts
35.4 Register Summary
35.5 Registers
36 Motor Control PWM (MCPWM)
36.1 Overview
36.2 Features
36.3 Submodules
36.3.1 Overview
36.3.2 PWM Timer Submodule
36.3.3 PWM Operator Submodule
36.3.4 Capture Submodule
36.4 Register Summary
36.5 Registers
37 Remote Control Peripheral (RMT)
37.1 Overview
37.2 Features
37.3 Functional Description
37.3.1 Architecture
37.3.2 RAM
37.3.3 Clock
37.3.4 Transmitter
37.3.5 Receiver
37.3.6 Configuration Update
37.4 Interrupts
37.5 Register Summary
37.6 Registers
38 Pulse Count Controller (PCNT)
38.1 Features
38.2 Functional Description
38.3 Applications
38.3.1 Channel 0 Incrementing Independently
38.3.2 Channel 0 Decrementing Independently
38.3.3 Channel 0 and Channel 1 Incrementing Together
38.4 Register Summary
38.5 Registers
39 On-Chip Sensors and Analog Signal Processing
39.1 Overview
39.2 Capacitive Touch Sensors
39.2.1 Terminology
39.2.2 Overview
39.2.3 Features
39.2.4 Capacitive Touch Pins
39.2.5 Touch Sensors Operating Principle and Signals
39.2.6 Touch FSM
39.2.7 Touch Detection
39.2.8 Noise Detection
39.2.9 Proximity Mode
39.2.10 Moisture Tolerance and Water Rejection
39.3 SAR ADCs
39.3.1 Overview
39.3.2 Features
39.3.3 SAR ADC Architecture
39.3.4 Input Signals
39.3.5 ADC Conversion and Attenuation
39.3.6 RTC ADC Controller
39.3.7 DIG ADC Controller
39.3.8 SAR ADC2 Arbiter
39.4 Temperature Sensor
39.4.1 Overview
39.4.2 Features
39.4.3 Functional Description
39.5 Interrupts
39.6 Register Summary
39.6.1 SENSOR (ALWAYS_ON) Register Summary
39.6.2 SENSOR (RTC_PERI) Register Summary
39.6.3 SENSOR (DIG_PERI) Register Summary
39.7 Registers
39.7.1 SENSOR (ALWAYS_ON) Registers
39.7.2 SENSOR (RTC_PERI) Registers
39.7.3 SENSOR (DIG_PERI) Registers
40 Related Documentation and Resources
Glossary
Abbreviations for Peripherals
Abbreviations Related to Registers
Access Types for Registers
Revision History
ESP32S3
Technical Reference Manual
Version 1.2
Espressif Systems
Copyright © 2023
www.espressif.com
About This Document
The ESP32S3 is targeted at developers working on low level software projects that use the ESP32-S3 SoC. It
describes the hardware modules listed below for the ESP32-S3 SoC and other products in ESP32-S3 series.
The modules detailed in this document provide an overview, list of features, hardware architecture details, any
necessary programming procedures, as well as register descriptions.
Navigation in This Document
Here are some tips on navigation through this extensive document:
• Release Status at a Glance on the very next page is a minimal list of all chapters from where you can
directly jump to a specific chapter.
• Use the Bookmarks on the side bar to jump to any specific chapters or sections from anywhere in the
document. Note this PDF document is configured to automatically display Bookmarks when open, which
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Release Status at a Glance
No. ESP32S3 Chapters
1
Processor Instruction Extensions (PIE)
ULP Coprocessor (ULP-FSM,
ULP-RISC-V)
Progress No. ESP32S3 Chapters
Published
SHA Accelerator (SHA)
21
Published
22
Digital Signature (DS)
Progress
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
Published
External Memory Encryption and
Decryption (XTS_AES)
Random Number Generator (RNG)
Clock Glitch Detection
UART Controller (UART)
SPI Controller (SPI)
I2C Controller (I2C)
I2S Controller (I2S)
Pulse Count Controller (PCNT)
USB On-The-Go (USB)
USB Serial/JTAG Controller
(USB_SERIAL_JTAG)
Two-wire Automotive Interface
(TWAI®)
SD/MMC Host Controller (SDHOST)
LED PWM Controller (LEDC)
34
35
36 Motor Control PWM (MCPWM)
37
Remote Control Peripheral (RMT)
LCD and Camera Controller
(LCD_CAM)
On-Chip Sensors and Analog Signal
Processing
2
3
4
5
6
7
8
9
10
11
12
GDMA Controller (GDMA)
Published
Published
Published
System and Memory
eFuse Controller
IO MUX and GPIO Matrix (GPIO, IO
MUX)
Published
Reset and Clock
Published
Chip Boot Control
Interrupt Matrix (INTERRUPT)
Published
Low-power Management (RTC_CNTL) Published
System Timer (SYSTIMER)
Published
Published
Timer Group (TIMG)
Published
23
24
25
26
27
28
29
30
31
32
13 Watchdog Timers (WDT)
Published
33
XTAL32K Watchdog Timers (XTWDT)
Permission Control (PMS)
14
15
16 World Controller (WCL)
17
System Registers (SYSTEM)
Published
Published
Published
Published
18
AES Accelerator (AES)
Published
38
HMAC Accelerator (HMAC)
Published
39
RSA Accelerator (RSA)
Published
19
20
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/documentation/esp32-s3_technical_reference_manual_en.pdf
Contents
Contents
1 Processor Instruction Extensions (PIE)
1.1
1.2
1.3
ALU
Overview
Features
Structure Overview
1.3.1 Bank of Vector Registers
1.3.2
1.3.3 QACC Accumulator Register
1.3.4
ACCX Accumulator Register
1.3.5
Address Unit
Syntax Description
1.4.1 Bit/Byte Order
1.4.2
Components of Extended Instruction Set
1.5.1 Registers
Instruction Field Definition
1.5.2
Special Registers
1.5.1.1 General-Purpose Registers
1.5.1.2
Fast GPIO Interface
1.5.2.1 GPIO_OUT
1.5.2.2 GPIO_IN
Arithmetic Instructions
1.5.3 Data Format and Alignment
1.5.4 Data Overflow and Saturation Handling
Extended Instruction List
1.6.1 Read Instructions
1.6.2 Write Instructions
1.6.3 Data Exchange Instructions
1.6.4
1.6.5 Comparison Instructions
1.6.6 Bitwise Logical Instructions
Shift Instructions
1.6.7
1.6.8
FFT Dedicated Instructions
1.6.9 GPIO Control Instructions
1.6.10 Processor Control Instructions
Instruction Performance
1.7.1 Data Hazard
1.7.2 Hardware Resource Hazard
1.7.3 Control Hazard
Extended Instruction Functional Description
1.4
1.5
1.6
1.7
1.8
GoBack
36
36
36
36
37
38
38
38
38
38
39
40
42
42
43
43
45
45
45
45
46
47
49
50
51
52
56
57
57
58
59
59
61
61
70
70
72
296
296
296
297
2 ULP Coprocessor (ULPFSM, ULPRISCV)
2.1
2.2
2.3
Overview
Features
Programming Workflow
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2.4
2.5
2.6
2.7
2.8
2.9
ULP Coprocessor Sleep and Weakup Workflow
ULP-FSM
2.5.1
2.5.2
ALU - Perform Arithmetic and Logic Operations
ST – Store Data in Memory
LD – Load Data from Memory
JUMP – Jump to an Absolute Address
JUMPR – Jump to a Relative Address (Conditional upon R0)
JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register)
HALT – End the Program
Features
Instruction Set
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.5.2.5
2.5.2.6
2.5.2.7
2.5.2.8 WAKE – Wake up the Chip
2.5.2.9 WAIT – Wait for a Number of Cycles
2.5.2.10 TSENS – Take Measurement with Temperature Sensor
2.5.2.11 ADC – Take Measurement with ADC
2.5.2.12 REG_RD – Read from Peripheral Register
2.5.2.13 REG_WR – Write to Peripheral Register
Features
ULP-RISC-V
2.6.1
2.6.2 Multiplier and Divider
2.6.3 ULP-RISC-V Interrupts
Introduction
Interrupt Controller
Interrupt Instructions
RTC Peripheral Interrupts
2.6.3.1
2.6.3.2
2.6.3.3
2.6.3.4
RTC I2C Controller
2.7.1 Connecting RTC I2C Signals
2.7.2 Configuring RTC I2C
2.7.3 Using RTC I2C
2.7.3.1
2.7.3.2
2.7.3.3
2.7.3.4
Instruction Format
I2C_RD - I2C Read Workflow
I2C_WR - I2C Write Workflow
Detecting Error Conditions
2.7.4 RTC I2C Interrupts
Address Mapping
Register Summary
2.9.1 ULP (ALWAYS_ON) Register Summary
2.9.2 ULP (RTC_PERI) Register Summary
2.9.3 RTC I2C (RTC_PERI) Register Summary
2.9.4 RTC I2C (I2C) Register Summary
2.10 Registers
2.10.1 ULP (ALWAYS_ON) Registers
2.10.2 ULP (RTC_PERI) Registers
2.10.3 RTC I2C (RTC_PERI) Registers
2.10.4 RTC I2C (I2C) Registers
298
300
300
300
301
303
306
307
307
308
309
309
309
310
310
311
311
312
312
312
313
313
313
314
315
316
316
317
317
317
318
318
319
319
320
320
320
321
321
321
322
322
325
329
331
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Linked List
Peripheral-to-Memory and Memory-to-Peripheral Data Transfer
3 GDMA Controller (GDMA)
3.1
3.2
3.3
3.4
Overview
Features
Architecture
Functional Description
3.4.1
3.4.2
3.4.3 Memory-to-Memory Data Transfer
3.4.4 Channel Buffer
Enabling GDMA
3.4.5
3.4.6
Linked List Reading Process
EOF
3.4.7
Accessing Internal RAM
3.4.8
3.4.9
Accessing External RAM
3.4.10 External RAM Access Permissions
3.4.11 Seamless Access to Internal and External RAM
3.4.12 Arbitration
GDMA Interrupts
Programming Procedures
3.6.1
3.6.2
3.6.3
Register Summary
Registers
3.5
3.6
3.7
3.8
Programming Procedures for GDMA’s Transmit Channel
Programming Procedures for GDMA’s Receive Channel
Programming Procedures for Memory-to-Memory Transfer
4 System and Memory
4.1
4.2
4.3
Overview
Features
Functional Description
4.3.1
4.3.2
4.3.3
Address Mapping
Internal Memory
External Memory
4.3.3.1
4.3.3.2
4.3.3.3
GDMA Address Space
External Memory Address Mapping
Cache
Cache Operations
4.3.4
4.3.5 Modules/Peripherals
4.3.5.1 Module/Peripheral Address Mapping
5
5.1
5.2
5.3
eFuse Controller
Overview
Features
Functional Description
5.3.1
Structure
5.3.1.1
5.3.1.2
EFUSE_WR_DIS
EFUSE_RD_DIS
345
345
345
346
347
347
348
348
349
349
350
350
351
351
352
353
353
353
354
354
354
354
356
362
385
385
385
386
386
387
390
390
390
391
392
393
393
396
396
396
396
396
403
403
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Data Storage
5.3.1.3
Programming of Parameters
5.3.2
5.3.3 User Read of Parameters
eFuse VDDQ Timing
5.3.4
The Use of Parameters by Hardware Modules
5.3.5
5.3.6
Interrupts
Register Summary
Registers
IO MUX and GPIO Matrix (GPIO, IO MUX)
Overview
Features
Architectural Overview
Peripheral Input via GPIO Matrix
6.4.1 Overview
6.4.2
6.4.3
6.4.4
Peripheral Output via GPIO Matrix
6.5.1 Overview
6.5.2
6.5.3
6.5.4
Signal Synchronization
Functional Description
Simple GPIO Input
Functional Description
Simple GPIO Output
Sigma Delta Modulated Output
6.5.4.1
6.5.4.2
Functional Description
SDM Configuration
5.4
5.5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Functional Description
Direct Input and Output via IO MUX
6.6.1 Overview
6.6.2
RTC IO MUX for Low Power and Analog Input/Output
6.7.1 Overview
6.7.2
6.7.3
Pin Functions in Light-sleep
Pin Hold Feature
Low Power Capabilities
Analog Functions
6.8
6.9
6.10 Power Supply and Management of GPIO Pins
6.10.1 Power Supply of GPIO Pins
6.10.2 Power Supply Management
6.11 Peripheral Signals via GPIO Matrix
6.12 IO MUX Function List
6.13 RTC IO MUX Pin List
6.14 Register Summary
6.14.1 GPIO Matrix Register Summary
6.14.2 IO MUX Register Summary
6.14.3 SDM Output Register Summary
6.14.4 RTC IO MUX Register Summary
6.15 Registers
403
404
406
408
408
408
409
413
457
457
457
457
459
459
459
460
461
461
461
462
463
463
463
464
464
464
464
464
464
465
465
465
466
466
466
466
466
478
479
481
481
482
484
484
486
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6.15.1 GPIO Matrix Registers
6.15.2 IO MUX Registers
6.15.3 SDM Output Registers
6.15.4 RTC IO MUX Registers
7 Reset and Clock
7.1
Architectural Overview
Features
Functional Description
Reset
7.1.1 Overview
7.1.2
7.1.3
7.1.4
Clock
7.2.1 Overview
7.2.2
7.2.3
7.2.4
7.2
Architectural Overview
Features
Functional Description
CPU Clock
7.2.4.1
7.2.4.2
Peripheral Clocks
7.2.4.3 Wi-Fi and Bluetooth LE Clock
7.2.4.4
RTC Clock
8 Chip Boot Control
8.1
8.2
8.3
8.4
8.5
Overview
Boot Mode Control
ROM Messages Printing Control
VDD_SPI Voltage Control
JTAG Signal Source Control
9
9.1
9.2
9.3
9.4
9.5
Interrupt Matrix (INTERRUPT)
Overview
Features
Functional Description
9.3.1
9.3.2 CPU Interrupts
9.3.3
Peripheral Interrupt Sources
Allocate Peripheral Interrupt Source to CPUx Interrupt
9.3.3.1
9.3.3.2
9.3.3.3
Allocate one peripheral interrupt source (Source_Y) to CPUx
Allocate multiple peripheral interrupt sources (Source_Yn) to CPUx
Disable CPUx peripheral interrupt source (Source_Y)
9.3.4 Disable CPUx NMI Interrupt
9.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
Register Summary
9.4.1 CPU0 Interrupt Register Summary
9.4.2 CPU1 Interrupt Register Summary
Registers
9.5.1 CPU0 Interrupt Registers
9.5.2 CPU1 Interrupt Registers
486
497
499
501
510
510
510
510
510
511
512
512
512
512
513
513
513
515
515
516
516
517
517
518
519
520
520
520
521
521
525
526
526
527
527
527
527
527
528
531
536
536
540
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