TLC1543 英文数据手册(TLC1543-en).pdf

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FEATURES

DESCRIPTION

TYPICAL EQUIVALENT INPUTS

DETAILED DESCRIPTION

FAST MODES

MODE 1: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 10-CLOCK TRANSFER

MODE 2: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 10-CLOCK TRANSFER

MODE 3: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER

MODE 4: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

SLOW MODES

MODE 5: SLOW MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER

MODE 6: SLOW MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

ADDRESS BITS

ANALOG INPUTS AND TEST MODES

CONVERTER AND ANALOG INPUT

CHIP-SELECT OPERATION

REFERENCE VOLTAGE INPUTS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

PARAMETER MEASUREMENT INFORMATION

TIMING DIAGRAMS

APPLICATION INFORMATION

SIMPLIFIED ANALOG INPUT ANALYSIS

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS FEATURES • 10-Bit Resolution A/D Converter • 11 Analog Input Channels • Three Built-In Self-Test Modes • Inherent Sample-and-Hold Function • Total Unadjusted Error: – 1LSB Max • On-Chip System Clock • End-of-Conversion (EOC) Output • Terminal Compatible With TLC542 • CMOS Technology (DATA OUT)] DESCRIPTION The TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, and TLC1543Q are CMOS 10-bit switched-capacitor successive-approximation analog-to-digital converters. These devices have three inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), address input (ADDRESS), and data output that provide a direct 4-wire interface to the serial port of a host processor. These devices allow high-speed data transfers from the host. In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the devices features differential high-impedance reference inputs facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A low-error switched-capacitor conversion over free-air temperature range. the end of A/D conversion, allows operating that design full the Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992–2006, Texas Instruments Incorporated www.ti.com1234 567891020191817161514131211A0A1A2A3A4A5A6A7A8GNDVCCEOCI/O CLOCKADDRESSDATA OUTCSREF+REF−A10A9DB, DW, J, OR N PACKAGE(TOP VIEW)3212019910111213456781817161514I/O CLOCKADDRESSDATA OUTCSREF+A3A4A5A6A7FK OR FN PACKAGE(TOP VIEW)A2A1A0A10REF −EOCA8GNDA9VCC

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGE SMALL OUTLINE (DW) CHIP CARRIER (FN) PLASTIC DIP (N) CHIP CARRIER (FK) CERAMIC DIP (J) FUNCTIONAL BLOCK DIAGRAM TLC1542MFK TLC1542MJ SMALL OUTLINE (DB) TLC1543CDB TLC1543IDB TA 0 C to 70 C -40 C to 85 C -40 C to 125 C -55 C to 125 C TLC1542CDW TLC1543CDW TLC1542IDW TLC1543IDW TLC1542CN TLC1543CN TLC1542IN TLC1543IN TLC1542CFN TLC1543CFN TLC1542IFN TLC1543IFN TLC1542QFN TLC1543QFN TLC1543QDB TLC1543QDW TYPICAL EQUIVALENT INPUTS 2 Submit Documentation Feedback www.ti.com14-ChannelAnalogMultiplexer410104REF+REF−DATAOUTADDRESSI/O CLOCKCS3EOCA0A1A2A3A4A5A6A7A8A9A1012345678911121815171916141310-BitAnalog-to-DigitalConverter(switched capacitors)Sample andHoldInput AddressRegisterSelf-TestReferenceOutputDataRegisterSystem Clock,Control Logic,and I/OCounters10-to-1 DataSelector andDriverINPUT CIRCUIT IMPEDANCE DURING SAMPLING MODEINPUT CIRCUIT IMPEDANCE DURING HOLD MODE1 kW TYPCi = 60 pF TYP(equivalent inputcapacitance)5 MW TYPA0−A10A0−A10

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 TERMINAL NAME ADDRESS NO. 17 A0-A10 1-9, 11, 12 CS DATA OUT EOC GND I/O CLOCK REF+ REF- VCC 15 16 19 10 18 14 13 20 TERMINAL FUNCTIONS I/O DESCRIPTION I I I O O I I I I I . Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be converted next. The address data is presented with the MSB first and shifts in on the first four rising edges of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for the remainder of the current conversion period. Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal to 1 kW Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges of the internal system clock. The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs. End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to this terminal. Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four functions: 1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock. The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF- terminal. The lower reference voltage value (nominally ground) is applied to this terminal. Positive supply voltage DETAILED DESCRIPTION With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state. The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired analog channel, and the next six clocks providing the control timing for sampling the analog input. There are six basic serial-interface timing modes that can be used with the device. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a 16-clock transfer and CS active (low) continuously. Submit Documentation Feedback 3 www.ti.com

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten clocks long. Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that can be used, and the timing edge on which the MSB of the previous conversion appears at the output. MODES CS NO. OF 1/O CLOCK MSB AT DATA OUT(1) Table 1. MODE OPERATION Fast Modes Slow Modes Mode 1 High between conversion cycles Mode 2 Low continuously Mode 3 High between conversion cycles Mode 4 Low continuously Mode 5 High between conversion cycles Mode 6 Low continuously (1) These edges also initiate serial-interface communication. (2) No more than 16 clocks should be used. (3) No more than 16 clocks should be used. 10 10 11 TO 16 (2) 16(2) 11 to 16 (3) 16(3) CS falling edge EOC rising edge CS falling edge EOC rising edge CS falling edge 16th clock falling edge TIMING DIAGRAM Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 FAST MODES The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not begin until the falling edge of the tenth I/O CLOCK. MODE 1: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 10-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. MODE 2: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 10-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output. MODE 3: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. 4 Submit Documentation Feedback www.ti.com

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 MODE 4: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output. SLOW MODES In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must occur within 9.5 m s after the tenth I/O clock falling edge. MODE 5: SLOW MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. MODE 6: SLOW MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16-clock transfer initiated by the serial interface. ADDRESS BITS The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal (MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address selects one of 14 inputs (11 analog inputs or three internal test inputs). ANALOG INPUTS AND TEST MODES The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs. Submit Documentation Feedback 5 www.ti.com

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 Table 2. ANALOG-CHANNEL-SELECT ADDRESS ANALOG INPUT SELECTED VALUE SHIFTED INTO ADDRESS INPUT BINARY HEX A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 0 1 2 3 4 5 6 7 8 9 A Table 3. TEST-MODE-SELECT ADDRESS INTERNAL SELF-TEST VOLTAGE SELECTED(1) VALUE SHIFTED INTO ADDRESS INPUT BINARY HEX OUTPUT RESULT (HEX)(2) Vref- Vref+ 1011 1100 1101 B C D 200 000 3FF (1) Vref+ is the voltage applied to the REF+ input, and Vref- is the voltage applied to the REF- input. (2) The output results shown are the ideal values and vary with the reference stability and with internal offsets. In the first phase of CONVERTER AND ANALOG INPUT The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-) voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC), a 0 bit is placed in the output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB. 6 Submit Documentation Feedback www.ti.comVref+ − Vref−2

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 Figure 1. Simplified Model of the Successive-Approximation System CHIP-SELECT OPERATION The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode. A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device returns to the initial state (the contents of the output data register remain at the previous conversion result). Exercise care to prevent CS from being taken low close to completion of conversion because the output data can be corrupted. REFERENCE VOLTAGE INPUTS There are two reference inputs used with the device: REF+ and REF-. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than REF-. Submit Documentation Feedback 7 www.ti.comSCThresholdDetectorNode 512REF−REF+ST512VITo OutputLatchesREF+REF+REF+REF+1248161282561REF+REF+REF−REF−REF−REF−REF−REF−REF−REF−STSTSTSTSTSTSTST

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G–MARCH 1992–REVISED JANUARY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) VCC, see (2) VI VO Vref+ Vref- TA Tstg Supply voltage range Input voltage range Output voltage range Positive reference voltage Negative reference voltage Peak input current (any input) Peak total input current (all inputs) Operating free-air temperature range TLC1542C, TLC1543C TLC1542I, TLC1543I TLC1542Q, TLC1543Q TLC1542M Storage temperature range, Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds UNIT -0.5 V to 6.5 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V VCC + 0.1 V -0.1 V – 20 mA – 30 mA 0 C to 70 C -40 C to 85 C -40 C to 125 C -55 C to 125 C -65 C to 150 C 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted). RECOMMENDED OPERATING CONDITIONS VCC Vref+, see (1) Vref-, see (1) Supply voltage Positive reference voltage Negative reference voltage Vref+-Vref-, see (1) Differential reference voltage VIH VIL tsu(A), see Figure 4 th(A), see Figure 4 th(CS), see Figure 5 tsu(CS), see (2) and Figure 5 twH(I/O) twL(I/O) tt(I/O), see (4) and Figure 6 tt(CS) Analog input voltage ,see (1) High-level control input voltage Low-level control input voltage Setup time, address bits at data input before I/O CLOCK› Hold time, address bits after I/O CLOCK› Hold time, CS low after last I/O CLOCKﬂ Setup time, CS low before clocking in first address bit Clock frequency at I/O CLOCK, see (3) Pulse duration, I/O CLOCK high, Pulse duration, I/O CLOCK low, Transition time, I/O CLOCK, Transition time, ADDRESS and CS, VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V MIN 4.5 2.5 0 2 100 0 0 1.425 0 190 190 NOM 5 VCC 0 VCC MAX 5.5 VCC+0. 2 VCC 0.8 UNIT V V V V V V V ns ns ns m s 2.1 1 10 MHz ns ns m s m s (1) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however, the electrical specifications are no longer applicable. (2) To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CSﬂ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. (3) For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (£ 2 V) at least 1 I/O CLOCK rising edge (‡ 2 V) must occur within 9.5 m s. room temperature, the devices function with input clock transition time as slow as 1 m s for remote data-acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. (4) This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal 8 Submit Documentation Feedback www.ti.com

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