Preliminary
FM24CL16B
16Kb Serial 3V F-RAM Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High Endurance 1014 Read/Writes
•
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1MHz Maximum Bus Frequency
• Direct Hardware Replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz
38 year Data Retention
Description
The FM24CL16B is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
The FM24CL16B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24CL16B is capable of
supporting 1014 read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24CL16B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where a long write time
can cause data loss. The combination of features
allows the system to write data more frequently, with
less system overhead.
The FM24CL16B provides substantial benefits to
users of serial EEPROM, yet these benefits are
available in a hardware drop-in replacement. The
FM24CL16B is available in an industry standard 8-
pin SOIC package and uses a familiar two-wire
protocol. The specifications are guaranteed over the
industrial temperature range from -40°C to +85°C.
2.7 - 3.65V Operation
100 µA Active Current (100 kHz)
3 µA (typ.) Standby Current
Low Power Operation
•
•
•
Industry Standard Configuration
•
•
Industrial Temperature -40° C to +85° C
8-pin “Green”/RoHS SOIC and TDFN Packages
Pin Configuration
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Top View
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
SDA
SCL
WP
VDD
VSS
Function
Serial Data/Address
Serial Clock
Write Protect
Supply Voltage
Ground
Ordering Information
FM24CL16B-G
FM24CL16B-GTR
FM24CL16B-DG
FM24CL16B-DGTR
“Green”/RoHS 8-pin SOIC
“Green”/RoHS 8-pin SOIC,
Tape & Reel
“Green”/RoHS 8-pin TDFN
“Green”/RoHS 8-pin TDFN,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.4
Feb. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
FM24CL16B - 16Kb 3V I2C F-RAM
Counter
Address
Latch
256 x 64
FRAM Array
SDA
SCL
WP
Serial to Parallel
Converter
Control Logic
8
Data Latch
Figure 1. Block Diagram
Pin Description
Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR’d with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.
Input
Input Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
Supply Voltage
Supply
Supply Ground
-
No connect
Pin Description
Pin Name
SDA
Type
I/O
SCL
WP
VDD
VSS
NC
Rev. 1.4
Feb. 2011
Page 2 of 13
Overview
The FM24CL16B is a serial FRAM memory. The
memory array is logically organized as a 2,048 x 8
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24CL16B and a serial
EEPROM with the same pinout relates to its superior
write performance.
Memory Architecture
When accessing the FM24CL16B, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The 2,048 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), a row address, and a segment address. The
row address consists of 8-bits that specify one of 256
rows. The 3-bit segment address specifies one of 8
segments within each row. The complete 11-bit
address specifies each byte uniquely.
Most functions of
the FM24CL16B either are
controlled by the two-wire interface or handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
section below.
Note
the FM24CL16B contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.
that
FM24CL16B - 16Kb 3V I2C F-RAM
two-wire bus
industry standard
Two-wire Interface
The FM24CL16B employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24CL16B in a microcontroller-based
system. The
is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL16B is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that define
the four states. Detailed timing diagrams are in the
electrical specifications.
Microcontroller
VDD
Rmin = 1.1 Kohm
Rmax = tR/Cbus
SDA
SCL
SDA
SCL
FM24CL16B
Other Slave
Device
Figure 2. Typical System Configuration
Rev. 1.4
Feb. 2011
Page 3 of 13
SCL
SDA
Stop
(Master)
Start
(Master)
FM24CL16B - 16Kb 3V I2C F-RAM
7
6
0
Data bits
(Transmitter)
Data bit
(Transmitter)
Acknowledge
(Receiver)
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL16B must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
prepare the FM24CL16B for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high. For system design
considerations, keeping SCL in a low state while idle
improves robustness.
Acknowledge
The Acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state,
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL16B
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24CL16B to attempt to drive
the bus on the next clock while the master is sending
a new command such as a Stop.
Slave Address
The first byte that the FM24CL16B expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
specifies if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24CL16B. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-1 are used
for page select. They specify the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. R/W=1 indicates a read
operation and R/W=0 indicates a write operation.
Rev. 1.4
Feb. 2011
Page 4 of 13
Slave ID
Page
Select
1
0
1
0
A2
A1
A0
R/W
Figure 4. Slave Address
Word Address
After the FM24CL16B (as receiver) acknowledges
the slave ID, the master will place the word address
on the bus for a write operation. The word address is
the lower 8-bits of the address to be combined with
the 3-bits of the page select to specify the exact byte
to be written. The complete 11-bit address is latched
internally.
No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.
After transmission of each data byte, just prior to the
acknowledge,
the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing.
After the last address (7FFh) is reached, the address
latch will roll over to 000h. There is no limit on the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After all address information has been transmitted,
data
the
FM24CL16B can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be
the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24CL16B
will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
the bus master and
transfer between
the FM24CL16B
increments
transferred.
If
FM24CL16B - 16Kb 3V I2C F-RAM
Memory Operation
The FM24CL16B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16B and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master
sends each byte of data to the memory and the
memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
end of the address range is reached internally, the
address counter will wrap from 7FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a
to
determine if a write is complete is unnecessary and
will always return a ‘ready’ condition.
An actual memory array write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition
prior to the 8th data bit. The FM24CL16B needs no
page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL16B will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.
technique used with EEPROMs
Rev. 1.4
Feb. 2011
Page 5 of 13
By Master
Start
FM24CL16B - 16Kb 3V I2C F-RAM
Address & Data
Stop
S
Slave Address
0
A
Word Address
A
Data Byte
A P
By FM24CL16
Acknowledge
Figure 5. Single Byte Write
By Master
Start
Address & Data
Stop
S
Slave Address
0
A
Word Address
A
Data Byte
A
Data Byte
A P
By FM24CL16
Acknowledge
Figure 6. Multiple Byte Write
Read Operation
There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24CL16B uses the
internal address latch to supply the lower 8 address
bits. In a selective read, the user performs a procedure
to set these lower address bits to a specific value.
is
the
read operation. This
Current Address & Sequential Read
As mentioned above the FM24CL16B uses an
internal latch to supply the lower 8 address bits for a
read operation. A current address read uses the
existing value in the address latch as a starting place
for
the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. The 3
page select bits in the slave ID specify the block of
memory that is used for the read operation. On the
next clock, the FM24CL16B will begin shifting out
data from the current address. The current address is
the 3 bits from the slave ID combined with the 8 bits
that were in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address counter
will be incremented. Each time the bus master
acknowledges a byte
the
FM24CL16B should read out the next sequential
byte.
Rev. 1.4
Feb. 2011
indicates
that
this
likely create a bus contention as
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most
the
FM24CL16B attempts to read out additional data
onto the bus. The four valid methods are as follows.
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
the preferred method.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle. Bus contention may result.
4. The bus master issues a start in the 9th clock
cycle. Bus contention may result.
If the internal address reaches 7FFh it will wrap
around to 000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
A simple technique allows a user to select a random
address location as the starting point for a read
operation. It uses the first two bytes of a write
operation to set the internal address byte followed by
subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol, the
bus master then sends the word address byte that is
loaded into the internal address latch. After the
FM24CL16B acknowledges the word address, the
bus master
condition. This
issues
start
a
Page 6 of 13
simultaneously aborts the write operation and allows
the read command to be issued with the slave address
By Master
Start
Address
FM24CL16B - 16Kb 3V I2C F-RAM
set to 1. The operation is now a current address read.
This operation is illustrated in Figure 9.
No
Acknowledge
Stop
S
Slave Address
1
A
Data Byte
1 P
By FM24CL16
Acknowledge
Data
Figure 7. Current Address Read
By Master
Start
Address
Acknowledge
No
Acknowledge
Stop
S
Slave Address
1
A
Data Byte
A
Data Byte
1 P
By FM24CL16
Acknowledge
Data
Figure 8. Sequential Read
By Master
Start
Address
Start
Address
Acknowledge
No
Acknowledge
Stop
S
Slave Address
0
A
Word Address
A
S
Slave Address
1
A
Data Byte
A
Data Byte
1 P
By FM24CL16
Acknowledge
Data
Figure 9. Selective (Random) Read
Rev. 1.4
Feb. 2011
Page 7 of 13
FM24CL16B - 16Kb 3V I2C F-RAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
VIN
TSTG
TLEAD
VESD
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
Storage Temperature
Lead temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V *
-55°C to + 125°C
260° C
4kV
1.25kV
300V
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified)
Min
2.7
Typ
3.3
3
0.7 VDD
-0.3
40
1
Max
3.65
100
170
300
6
±1
±1
0.4
VDD + 0.3
0.3 VDD
Notes
1
2
3
3
5
Units
V
µA
µA
µA
µA
µA
µA
V
V
V
KΩ
MΩ
V
Symbol
VDD
IDD
ISB
ILI
ILO
VIH
VIL
VOL
RIN
Parameter
Main Power Supply
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz
Standby Current
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output Low Voltage
@ IOL = 3.0 mA
WP Input Resistance (WP)
For VIN = VIL (max)
For VIN = VIH (min)
Input Hysteresis (Does not apply to WP)
VHYS
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to the WP pin.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is strong (40KΩ) when the input voltage is below VIL and much weaker (1MΩ)
0.05 VDD
4
when the input voltage is above VIH.
Rev. 1.4
Feb. 2011
Page 8 of 13