MCP2515(MCP2515).pdf

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1.0 Device Overview

1.1 CAN Module

1.2 Control Logic

1.3 SPI Protocol Block

Figure 1-1: Block DIagram

Figure 1-2: Example System Implementation

Table 1-1: Pinout Description

1.4 Transmit/Receive Buffers/Masks/Filters

Figure 1-3: CAN Buffers and Protocol engine Block Diagram

1.5 CAN Protocol Engine

Figure 1-4: CAN Protocol engine Block Diagram

2.0 Can Message Frames

2.1 Standard Data Frame

2.2 Extended Data Frame

2.3 Remote Frame

2.4 Error Frame

2.5 Overload Frame

2.6 Interframe Space

Figure 2-1: Standard Data Frame

Figure 2-2: Extended Data Frame

Figure 2-3: Remote Frame

Figure 2-4: Active Error Frame

Figure 2-5: Overload Frame

3.0 Message Transmission

3.1 Transmit Buffers

3.2 Transmit Priority

3.3 Initiating Transmission

3.4 One-Shot Mode

3.5 TXnRTS PINS

3.6 Aborting Transmission

Figure 3-1: Transmit Message Flowchart

4.0 Message Reception

4.1 Receive Message Buffering

4.2 Receive Priority

4.3 Start-of-Frame Signal

4.4 RX0BF and RX1BF Pins

Figure 4-1: StArt-Of-FrAme Signaling

Table 4-1: CONFIGURING RXnBF PINS

Figure 4-2: Receive Buffer Block Diagram

Figure 4-3: Receive Flow Flowchart

4.5 Message Acceptance Filters and Masks

Table 4-2: Filter/Mask Truth Table

Figure 4-4: Masks AnD Filters Apply to CAN Frames

Figure 4-5: Message Acceptance Mask and Filter Operation

5.0 Bit Timing

5.1 The CAN Bit TIme

Figure 5-1: can Bit time Segments

Figure 5-2: TQ and the Bit Period

5.2 Synchronization

Figure 5-3: Synchronizing the Bit Time

5.3 Programming Time Segments

5.4 Oscillator Tolerance

5.5 Bit Timing Configuration Registers

6.0 Error Detection

6.1 CRC Error

6.2 Acknowledge Error

6.3 Form Error

6.4 Bit Error

6.5 Stuff Error

6.6 Error States

6.7 Error Modes and Error Counters

Figure 6-1: ErrOr Modes State Diagram

7.0 Interrupts

7.1 Interrupt Code Bits

Table 7-1: ICOD<2:0> DecOde

7.2 Transmit Interrupt

7.3 Receive Interrupt

7.4 Message Error Interrupt

7.5 Bus Activity Wakeup Interrupt

7.6 Error Interrupt

7.7 Interrupt Acknowledge

8.0 Oscillator

8.1 Oscillator Startup Timer

8.2 CLKOUT Pin

Figure 8-1: Crystal/Ceramic Resonator Operation

Figure 8-2: External Clock Source

Figure 8-3: External Series Resonant Crystal Oscillator Circuit(1)

Table 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Table 8-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR

9.0 RESET

Figure 9-1: RESET Pin Configuration Example

10.0 Modes of Operation

10.1 Configuration Mode

10.2 Sleep Mode

10.3 Listen-only Mode

10.4 Loopback Mode

10.5 Normal Mode

11.0 Register Map

Table 11-1: CAN Controller Register Map

Table 11-2: Control Register Summary

12.0 SPI™ Interface

12.1 Overview

12.2 Reset Instruction

12.3 Read Instruction

12.4 Read RX Buffer Instruction

12.5 Write Instruction

12.6 Load TX Buffer Instruction

12.7 Request-To-Send (RTS) Instruction

12.8 Read Status Instruction

12.9 RX Status Instruction

12.10 Bit Modify Instruction

Figure 12-1: Bit Modify

Table 12-1: SPI™ Instruction Set

Figure 12-2: Read instruction

Figure 12-3: Read RX Buffer Instruction

Figure 12-4: Byte Write instruction

Figure 12-5: Load TX Buffer

Figure 12-6: Request-to-send (RTS) instruction

Figure 12-7: BIT Modify instruction

Figure 12-8: Read Status instruction

Figure 12-9: RX StatUs Instruction

Figure 12-10: SPI™ Input Timing

Figure 12-11: SPI™ Output TIming

13.0 Electrical Characteristics

13.1 Absolute Maximum Ratings†

Table 13-1: DC Characteristics

Table 13-2: Oscillator Timing Characteristics

Table 13-3: CAN Interface AC Characteristics

Table 13-4: Reset AC Characteristics

Table 13-5: CLKOUT Pin AC Characteristics

Figure 13-1: Start-of-frame Pin AC Characteristics

Table 13-6: SPI™ Interface AC Characteristics

14.0 PackAging Information

14.1 Package Marking Information

MCP2515 Stand-Alone CAN Controller With SPI™ Interface Features Description • Implements CAN V2.0B at 1 Mb/s: - 0 – 8 byte length in the data field - Standard and extended data and remote frames Receive buffers, masks and filters: - Two receive buffers with prioritized message storage - Six 29-bit filters - Two 29-bit masks Data byte filtering on the first two data bytes (applies to standard data frames) Three transmit buffers with prioritizaton and abort features High-speed SPI™ Interface (10 MHz): - SPI modes 0,0 and 1,1 One-shot mode ensures message transmission is attempted only one time Clock out pin with programmable prescaler: - Can be used as a clock source for other device(s) Start-of-Frame (SOF) signal is available for monitoring the SOF signal: - Can be used for time-slot-based protocols and/or bus diagnostics to detect early bus degredation Interrupt output pin with selectable enables Buffer Full output pins configurable as: Interrupt output for each receive buffer - - General purpose output Request-to-Send (RTS) input pins individually configurable as: - Control pins to request transmission for each transmit buffer - General purpose inputs Low-power CMOS technology: - Operates from 2.7V – 5.5V - 5 mA active current (typical) - 1 µA standby current (typical) (Sleep mode) Temperature ranges supported: Industrial (I): -40°C to +85°C - - Extended (E): -40°C to +125°C Microchip Technology’s MCP2515 is a stand-alone Controller Area Network (CAN) controller that imple- ments the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via an industry standard Serial Peripheral Interface (SPI). Package Types 18-Lead PDIP/SOIC TXCAN RXCAN CLKOUT/SOF TX0RTS TX1RTS TX2RTS OSC2 OSC1 Vss 20-LEAD TSSOP TXCAN RXCAN CLKOUT/SOF TX0RTS TX1RTS NC TX2RTS OSC2 OSC1 VSS 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 5 1 5 2 P C M 5 1 5 2 P C M 18 17 16 15 14 13 12 11 10 20 19 18 17 16 15 14 13 12 11 VDD RESET CS SO SI SCK INT RX0BF RX1BF VDD RESET CS SO SI NC SCK INT RX0BF RX1BF © 2005 Microchip Technology Inc. Preliminary DS21801D-page 1

to simplify applications DEVICE OVERVIEW 1.0 is a stand-alone CAN controller The MCP2515 developed require interfacing with a CAN bus. A simple block diagram of the MCP2515 is shown in Figure 1-1. The device consists of three main blocks: 1. The CAN module, which includes the CAN protocol engine, masks, filters, transmit and receive buffers. that 2. The control logic and registers that are used to configure the device and its operation. 3. The SPI protocol block. An example system implementation using the device is shown in Figure 1-2. 1.1 CAN Module first loading transmitted by The CAN module handles all functions for receiving and transmitting messages on the CAN bus. Messages are the appropriate message buffer and control registers. Transmission is initiated by using control register bits via the SPI interface or by using the transmit enable pins. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against the user- defined filters to see if it should be moved into one of the two receive buffers. MCP2515 1.2 Control Logic The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided to allow greater system flexibility. There is one multi-purpose interrupt pin (as well as specific interrupt pins) for each of the receive registers that can be used to indicate a valid message has been received and loaded into one of the receive buffers. Use of the specific interrupt pins is optional. The general purpose interrupt pin, as well as status registers (accessed via the SPI interface), can also be used to determine when a valid message has been received. Additionally, there are three pins available to initiate immediate transmission of a message that has been loaded into one of the three transmit registers. Use of these pins initiating message transmissions can also be accomplished by utilizing control registers, accessed via the SPI interface. is optional, as 1.3 SPI Protocol Block The MCU interfaces to the device via the SPI interface. Writing is accomplished using standard SPI read and write commands, in addition to specialized SPI commands. from, all registers to, and reading FIGURE 1-1: BLOCK DIAGRAM CAN Module RXCAN TXCAN CAN Protocol Engine OSC1 OSC2 CLKOUT Timing Generation TX and RX Buffers Masks and Filters Control Logic Control and Interrupt Registers SPI™ Interface Logic CS SCK SI SO SPI Bus INT RX0BF RX1BF TX0RTS TX1RTS TX2RTS RESET © 2005 Microchip Technology Inc. Preliminary DS21801D-page 3

MCP2515 FIGURE 1-2: EXAMPLE SYSTEM IMPLEMENTATION Node Controller SPI™ MCP2515 TX RX XCVR Node Controller SPI MCP2515 TX RX XCVR Node Controller SPI MCP2515 TX RX XCVR CANH CANL TABLE 1-1: PINOUT DESCRIPTION Name PDIP/SOIC Pin # TSSOP Pin # I/O/P Type Description Alternate Pin Function TXCAN RXCAN CLKOUT TX0RTS TX1RTS TX2RTS OSC2 OSC1 VSS RX1BF RX0BF INT SCK SI SO CS RESET VDD NC Note: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 — 1 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 O I O I I I O I P O O O I I O I I P Transmit output pin to CAN bus Receive input pin from CAN bus — — Clock output pin with programmable prescaler Transmit buffer TXB0 request-to-send. 100 kΩ internal pull-up to VDD Transmit buffer TXB1 request-to-send. 100 kΩ internal pull-up to VDD Transmit buffer TXB2 request-to-send. 100 kΩ internal pull-up to VDD Oscillator output Start-of-Frame signal General purpose digital input. 100 kΩ internal pull-up to VDD General purpose digital input. 100 kΩ internal pull-up to VDD General purpose digital input. 100 kΩ internal pull-up to VDD — Oscillator input External clock input Ground reference for logic and I/O pins — Receive buffer RXB1 interrupt pin or general purpose digital output Receive buffer RXB0 interrupt pin or general purpose digital output Interrupt output pin Clock input pin for SPI™ interface Data input pin for SPI interface Data output pin for SPI interface General purpose digital output General purpose digital output — — — — Chip select input pin for SPI interface — Active low device reset input — Positive supply for logic and I/O pins — 6,15 — No internal connection Type Identification: I = Input; O = Output; P = Power DS21801D-page 4 Preliminary © 2005 Microchip Technology Inc.

MCP2515 1.4 Transmit/Receive Buffers/Masks/Filters The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. Figure 1-3 shows a block diagram of these buffers and their connection to the protocol engine. FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 TXB2 Q E R X T F T B A A O L M R R E X T E G A S S E M Q E R X T F T B A A O L M R R E X T E G A S S E M Q E R X T F T B A A O L M R R E X T Acceptance Mask RXM1 Acceptance Filter RXF2 E G A S S E M A c c e p t R X B 0 Acceptance Mask Acceptance Filter RXM0 RXF3 Acceptance Filter Acceptance Filter RXF0 RXF4 Acceptance Filter Acceptance Filter RXF1 RXF5 Identifier M A B Identifier Message Queue Control PROTOCOL ENGINE Transmit Byte Sequencer Data Field Data Field Receive Error Counter Transmit<7:0> Receive<7:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator CRC<14:0> Transmit Error Counter Protocol Finite State Machine A c c e p t R X B 1 REC TEC ErrPas BusOff SOF Transmit Logic TX Bit Timing Logic RX Clock Generator Configuration Registers © 2005 Microchip Technology Inc. Preliminary DS21801D-page 5

MCP2515 1.5 CAN Protocol Engine 1.5.3 ERROR MANAGEMENT LOGIC The CAN protocol engine combines several functional blocks, shown in Figure 1-4 and described below. 1.5.1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine (FSM). The FSM is a sequencer that controls the sequential data stream between the TX/RX shift register, the CRC register and the bus line. The FSM also controls the Error Management Logic (EML) and the parallel data stream between the TX/RX shift registers and the buffers. The FSM ensures that the processes of reception, arbitration, transmission and error-signaling are performed according to the CAN protocol. The automatic retransmission of messages on the bus line is also handled by the FSM. 1.5.2 CYCLIC REDUNDANCY CHECK The Cyclic Redundancy Check register generates the Cyclic Redundancy Check (CRC) code, which is transmitted after either the Control Field (for messages with 0 data bytes) or the Data Field and is used to check the CRC field of incoming messages. The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its two counters, the Receive Error Counter (REC) and the Transmit Error Counter (TEC), are incremented and decremented by commands from the bit stream processor. Based on the values of the error counters, the CAN controller is set into the states error-active, error-passive or bus-off. 1.5.4 BIT TIMING LOGIC The Bit Timing Logic (BTL) monitors the bus line input and handles the bus-related bit timing according to the CAN protocol. The BTL synchronizes on a recessive- to-dominant bus transition at Start-of-Frame (hard syn- chronization) and on any further recessive-to-dominant bus line transition if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable to compensate for the propagation delay time, phase shifts and to define the position of the sample point within the bit time. The programming of the BTL depends on the baud rate and external physical delay times. time segments FIGURE 1-4: CAN PROTOCOL ENGINE BLOCK DIAGRAM RX Bit Timing Logic SAM Sample<2:0> Majority Decision BusMon StuffReg<5:0> Comparator CRC<14:0> Comparator Shift<14:0> (Transmit<5:0>, Receive<7:0>) Receive<7:0> Transmit<7:0> Transmit Logic TX Receive Error Counter Transmit Error Counter REC TEC ErrPas BusOff Protocol FSM SOF RecData<7:0> TrmData<7:0> Interface to Standard Buffer Rec/Trm Addr. DS21801D-page 6 Preliminary © 2005 Microchip Technology Inc.

MCP2515 standard CAN frame will win arbitration due to the assertion of a dominant lDE bit. Also, the SRR bit in an extended CAN frame must be recessive to allow the assertion of a dominant RTR bit by a node that is sending a standard CAN remote frame. The SRR and lDE bits are followed by the remaining 18 bits of the identifier (Extended lD) and the remote transmission request bit. To enable standard and extended frames to be sent across a shared network, the 29-bit extended message identifier is split into 11-bit (most significant) and 18-bit (least significant) sections. This split ensures that the lDE bit can remain at the same bit position in both the standard and extended frames. Following the arbitration field is the six-bit control field. The first two bits of this field are reserved and must be dominant. The remaining four bits of the control field are the DLC, which specifies the number of data bytes contained in the message. The remaining portion of the frame (data field, CRC field, acknowledge field, end-of-frame and intermis- sion) is constructed in the same way as a standard data frame (see Section 2.1 “Standard Data Frame”). 2.3 Remote Frame identifier of the required data Normally, data transmission is performed on an autonomous basis by the data source node (e.g., a sensor sending out a data frame). It is possible, however, for a destination node to request data from the source. To accomplish this, the destination node sends a remote frame with an identifier that matches the frame. The appropriate data source node will then send a data frame in response to the remote frame request. There are two differences between a remote frame (shown in Figure 2-3) and a data frame. First, the RTR bit is at the recessive state and, second, there is no data field. In the event of a data frame and a remote frame with the same identifier being transmitted at the same time, the data frame wins arbitration due to the dominant RTR bit following the identifier. In this way, the node that transmitted the remote frame receives the desired data immediately. 2.4 Error Frame An error frame is generated by any node that detects a bus error. An error frame, shown in Figure 2-4, consists of two fields: an error flag field followed by an error delimiter field. There are two types of error flag fields. The type of error flag field sent depends upon the error status of the node that detects and generates the error flag field. CAN MESSAGE FRAMES 2.0 The MCP2515 supports standard data frames, extended data frames and remote frames (standard and extended), as defined the CAN 2.0B specification. in 2.1 Standard Data Frame The CAN standard data frame is shown in Figure 2-1. As with all other frames, the frame begins with a Start- Of-Frame (SOF) bit, which is of the dominant state and allows hard synchronization of all nodes. The SOF is followed by the arbitration field, consisting of 12 bits: the 11-bit identifier and the Remote Transmission Request (RTR) bit. The RTR bit is used to distinguish a data frame (RTR bit dominant) from a remote frame (RTR bit recessive). Following the arbitration field is the control field, consisting of six bits. The first bit of this field is the Identifier Extension (IDE) bit, which must be dominant to specify a standard frame. The following bit, Reserved Bit Zero (RB0), is reserved and is defined as a dominant bit by the CAN protocol. The remaining four bits of the control field are the Data Length Code (DLC), which specifies the number of bytes of data (0 – 8 bytes) contained in the message. After the control field is the data field, which contains any data bytes that are being sent, and is of the length defined by the DLC (0 – 8 bytes). The Cyclic Redundancy Check (CRC) field follows the data field and is used to detect transmission errors. The CRC field consists of a 15-bit CRC sequence, followed by the recessive CRC Delimiter bit. The final field is the two-bit Acknowledge (ACK) field. During the ACK Slot bit, the transmitting node sends out a recessive bit. Any node that has received an error-free frame acknowledges the correct reception of the frame by sending back a dominant bit (regardless of whether the node is configured to accept that specific message or not). The recessive acknowledge delimiter completes the acknowledge field and may not be overwritten by a dominant bit. 2.2 Extended Data Frame In the extended CAN data frame, shown in Figure 2-2, the SOF bit is followed by the arbitration field, which consists of 32 bits. The first 11 bits are the Most Significant bits (MSb) (Base-lD) of the 29-bit identifier. These 11 bits are followed by the Substitute Remote Request (SRR) bit, which is defined to be recessive. The SRR bit is followed by the lDE bit, which is recessive to denote an extended CAN frame. It should be noted that if arbitration remains unresolved after transmission of the first 11 bits of the identifier, and one of the nodes involved in the arbitration is sending a standard CAN frame (11-bit identifier), the © 2005 Microchip Technology Inc. Preliminary DS21801D-page 7

MCP2515 ACTIVE ERRORS 2.4.1 If an error-active node detects a bus error, the node interrupts transmission of the current message by generating an active error flag. The active error flag is composed of six consecutive dominant bits. This bit sequence actively violates the bit-stuffing rule. All other stations recognize the resulting bit-stuffing error and, in turn, generate error frames themselves, called error echo flags. The error flag field, therefore, consists of between six and twelve consecutive dominant bits (generated by one or more nodes). The error delimiter field (eight recessive bits) completes the error frame. Upon completion of the error frame, bus activity returns to normal and the interrupted node attempts to resend the aborted message. Note: Error echo flags typically occur when a localized disturbance causes one or more (but not all) nodes to send an error flag. The remaining nodes generate error flags in response (echo) to the original error flag. PASSIVE ERRORS 2.4.2 If an error-passive node detects a bus error, the node transmits an error-passive flag followed by the error delimiter field. The error-passive flag consists of six consecutive recessive bits. The error frame for an error- passive node consists of 14 recessive bits. From this it follows that, unless the bus error is detected by an error- active node or the transmitting node, the message will continue transmission because the error-passive flag does not interfere with the bus. If the transmitting node generates an error-passive flag, it will cause other nodes to generate error frames due to the resulting bit-stuffing violation. After transmission of an error frame, an error-passive node must wait for six consecutive recessive bits on the bus before attempting to rejoin bus communications. The error delimiter consists of eight recessive bits and allows the bus nodes to restart bus communications cleanly after an error has occurred. 2.5 Overload Frame An overload frame, shown in Figure 2-5, has the same format as an active error frame. An overload frame, however, can only be generated during an interframe space. In this way, an overload frame can be differen- tiated from an error frame (an error frame is sent during the transmission of a message). The overload frame consists of two fields: an overload flag followed by an overload delimiter. The overload flag consists of six dominant bits followed by overload flags generated by other nodes (and, as for an active error flag, giving a maximum of twelve dominant bits). The overload delimiter consists of eight recessive bits. An overload frame can be generated by a node as a result of two conditions: 1. The node detects a dominant bit during the interframe condition. Exception: The dominant bit is detected during the third bit of IFS. In this case, the receivers will interpret this as a SOF. space, an illegal 2. Due to internal conditions, the node is not yet able to begin reception of the next message. A node may generate a maximum of two sequential overload frames to delay the start of the next message. Note: Case 2 should never occur with the MCP2515 due to very short internal delays. 2.6 Interframe Space The interframe space separates a preceding frame (of any type) from a subsequent data or remote frame. The interframe space is composed of at least three recessive bits called the Intermission. This allows nodes time for internal processing before the start of the next message frame. After the intermission, the bus line remains in the recessive state (bus idle) until the next transmission starts. DS21801D-page 8 Preliminary © 2005 Microchip Technology Inc.

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