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K9F1G08U0D FLASH MEMORY K9F1G08U0D INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Samsung Confidential 1

K9F1G08U0D Document Title 128M x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No 0.0 1. Initial issue History Draft Date Remark Dec. 9, 2009 Advance The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. Samsung Confidential 2

K9F1G08U0D 1.0 Introduction 1.1 GENERAL DESCRIPTION Part Number K9F1G08U0D-S K9F1G08U0D-H 1.2 FEATURES FLASH MEMORY Vcc Range 2.7V ~ 3.6V 2.7V ~ 3.6V Organization x8 x8 PKG Type TSOP1 63FBGA • Voltage Supply - 3.3V Device(K9F1G08U0D) : 2.7V ~ 3.6V • Organization - Memory Cell Array : (128M + 4M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation - Page Size : (2K + 64)Byte - Random Read :35μs(Max.) - Serial Access : 30ns(Min.) • Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology -Endurance & Data Retention : Refor to the gualification report -ECC regnirement : 1 bit / 528bytes • Command Driven Operation • Unique ID for Copyright Protection • Package : - K9F1G08U0D-SCB0/SIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F1G08U0D-HCB0/HIB0 : Pb-FREE PACKAGE 63 FBGA (9 x 11 / 0.8 mm pitch) 1.3 GENERAL DESCRIPTION Offered in 128Mx8bit, the K9F1G08X0D is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost- effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 30ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on- chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08X0D′s extended reliability by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable app.lications requiring non-volatility. Samsung Confidential 3

K9F1G08U0D 1.4 PIN CONFIGURATION (TSOP1) FLASH MEMORY K9F1G08X0D-SCB0/SIB0 48-pin TSOP1 Standard Type 12mm x 20mm N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 1.4.1 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F Unit :mm/Inch X A M 0 1 . 0 4 0 0 . 0 ) 5 2 . 0 0 1 0 . 0 ( 2 7 4 . 0 0 . 2 1 0 X A M 0 4 . 2 1 8 8 4 . 0 0.05 MIN 0.002 1.00±0.05 0.039±0.002 1.20 MAX 0.047 #48 #25 5 7 0 0 + . 5 3 0 . 0 5 2 1 . 0 3 0 0 . 0 + . 1 0 0 0 - 5 0 0 . 0 20.00±0.20 0.787±0.008 #1 . 7 0 0 + 3 0 0 - . 0 2 . 0 . . 3 0 0 0 + 1 0 0 0 - 8 0 0 . 0 7 9 1 0 . 0 5 . 0 0 #24 P Y T 5 2 . 0 0 1 0 . 0 0~8° 0.45~0.75 0.018~0.030 18.40±0.10 0.724±0.004 ( 0.50 0.020 ) Samsung Confidential 4

FLASH MEMORY K9F1G08U0D 1.5 PIN CONFIGURATION (FBGA) A B C D E F G H K9F1G08U0D-HCB0/HIB0 Top View 4 3 1 2 5 6 N.C N.C N.C N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 NC NC NC Vcc NC I/O1 NC Vcc I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C Samsung Confidential 5

K9F1G08U0D 1.5.1 PACKAGE DIMENSIONS 63-Ball FBGA (measured in millimeters) Top View 9.00±0.10 #A1 FLASH MEMORY (Datum A) . 0 1 0 ± 0 0 . 1 1 (Datum B) 0 8 . 2 A B C D E F G H 63-∅0.45±0.05 ∅ 0.20 M A B Bottom View 9.00±0.10 0.80 x 9= 7.20 0.80 x 5= 4.00 0.80 4 5 6 3 2 1 2.00 2.00 Side View 9.00±0.10 0.10MAX 0.45±0.05 A 0 8 . 0 B 0 6 . 5 = 7 x 0 8 . 0 0 8 . 8 = 1 1 x 0 8 . 0 . 0 1 0 ± 0 0 . 1 1 i ) . n M ( 5 2 0 . ) . x a M ( 0 0 1 . Samsung Confidential 6

K9F1G08U0D 1.6 PIN DESCRIPTION FLASH MEMORY Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP R/B Vcc Vss N.C Pin Function DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt- age generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected. Note : Connect all VCC and VSS pins of each device to common power supply outputs. Samsung Confidential 7

K9F1G08U0D FLASH MEMORY Figure 1. K9F1G08X0D Functional Block Diagram VCC VSS A12 - A27 A0 - A11 Command CE RE WE X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Register Control Logic & High Voltage Generator CLE ALE WP 1,024M + 32M Bit NAND Flash ARRAY (2,048 + 64)Byte x 65,536 Data Register & S/A Y-Gating I/O Buffers & Latches Global Buffers Output Driver VCC VSS I/0 0 I/0 7 Figure 2. K9F1G08X0D Array Organization 64K Pages (=1,024 Blocks) 1 Block = 64 Pages (128K + 4k) Byte 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 1,024 Blocks = 1,056 Mbits 2K Bytes 64 Bytes 8 bit Page Register 2K Bytes 64 Bytes I/O 0 ~ I/O 7 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O 0 A0 A8 A12 A20 I/O 1 A1 A9 A13 A21 I/O 2 A2 A10 A14 A22 I/O 3 A3 A11 A15 A23 I/O 4 A4 *L A16 A24 I/O 5 A5 *L A17 A25 I/O 6 A6 *L A18 A26 I/O 7 A7 *L A19 A27 Column Address Column Address Row Address Row Address Note : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. Samsung Confidential 8

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