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FM24CL64B(FM24CL64B).pdf
Preliminary
FM24CL64B
64Kb Serial 3V F-RAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
• Organized as 8,192 x 8 bits
• High Endurance 1014 Read/Writes
•
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz
38 year Data Retention
level
Description
The FM24CL64B is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system
reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24CL64B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24CL64B is capable of
supporting 1014 read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24CL64B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data
loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24CL64B provides substantial benefits to
users of serial EEPROM, yet these benefits are
available in a hardware drop-in replacement. The
FM24CL64B is available in an industry standard 8-
pin SOIC package and uses a familiar two-wire
protocol. The specifications are guaranteed over an
industrial temperature range of -40°C to +85°C.
Low Power Operation
•
2.7V-3.6V Operation
100 µA Active Current (100 kHz)
•
•
3 µA (typ.) Standby Current
Industry Standard Configuration
•
•
Industrial Temperature -40° C to +85° C
8-pin “Green”/RoHS SOIC and TDFN Packages
Pin Configuration
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Top View
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
A0-A2
SDA
SCL
WP
VSS
VDD
Function
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24CL64B-G
FM24CL64B-GTR
FM24CL64B-DG
FM24CL64B-DGTR
“Green”/RoHS 8-pin SOIC
“Green”/RoHS 8-pin SOIC,
Tape & Reel
“Green”/RoHS 8-pin TDFN
“Green”/RoHS 8-pin TDFN,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Feb. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
FM24CL64B
Counter
Address
Latch
1,024 x 64
FRAM Array
SDA
SCL
WP
A0-A2
Serial to Parallel
Converter
Control Logic
Figure 1. FM24CL64B Block Diagram
8
Data Latch
Pin Description
Pin Name
A0-A2
Type
Input
SDA
I/O
SCL
WP
VDD
VSS
Input
Input
Supply
Supply
Pin Description
Address 0-2. These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
Serial Data Address. This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of
the part on the falling edge, and in on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
Write Protect. When WP is high, addresses in the entire memory map will be write-
protected. When WP is low, all addresses may be written. This pin is pulled down
internally.
Supply Voltage: 2.7V to 3.6V
Ground
Rev. 1.2
Feb. 2011
Page 2 of 13
FM24CL64B
Two-wire Interface
The FM24CL64B employs a bi-directional two-wire
bus protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24CL64B in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL64B always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are in the electrical
specifications.
Microcontroller
VDD
Rmin = 1.1 Kohm
Rmax = tR/Cbus
SDA
SCL
SDA
SCL
FM24CL64B
FM24CL64B
A0 A1 A2
A0 A1 A2
Figure 2. Typical System Configuration
Overview
The FM24CL64B is a serial F-RAM memory. The
memory array is logically organized as a 8,192 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the F-RAM is similar to serial EEPROMs. The major
difference between the FM24CL64B and a serial
EEPROM with the same pinout relates to its superior
write performance.
Memory Architecture
When accessing the FM24CL64B, the user addresses
8,192 locations each with 8 data bits. These data bits
are shifted serially. The 8,192 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other non-memory devices),
and an extended 16-bit address. Only the lower 13
bits are used by the decoder for accessing the
memory. The upper three address bits should be set
to 0 for compatibility with larger devices in the
future.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
Users expect several obvious system benefits from
the FM24CL64B due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM
is
vulnerable to noise during much of the cycle.
Note that it is the user’s responsibility to ensure that
VDD
to prevent
incorrect operation.
requiring milliseconds
to write
is within datasheet
tolerances
Rev. 1.2
Feb. 2011
Page 3 of 13
FM24CL64B
7
6
0
Stop
(Master)
Start
(Master)
Data bits
(Transmitter)
Data bit
(Transmitter)
Acknowledge
(Receiver)
Figure 3. Data Transfer Protocol
SCL
SDA
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL64B should
end with a stop condition. If an operation is in
progress when a stop is asserted, the operation will be
aborted. The master must have control of SDA (not a
memory read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24CL64B for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL64B
will continue to place data onto the bus as long as
the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24CL64B to attempt to drive the
bus on the next clock while the master is sending a
new command such as stop.
Slave Address
The first byte that the FM24CL64B expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select address bits, and a bit that specifies
if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24CL64B. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address
the
corresponding value on the external address pins to
select the device. Up to eight FM24CL64Bs can
reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
R/W=1indicates a read operation and R/W=0
indicates a write operation.
select bits. They must match
Rev. 1.2
Feb. 2011
Page 4 of 13
Slave ID
Device Select
1
7
0
6
1
5
0
4
A2
3
A1
2
A0
R/W
1
0
Figure 4. Slave Address
Addressing Overview
After the FM24CL64B (as receiver) acknowledges
the device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 13 address bits, the value of the
upper three bits are “don’t care”. Following the MSB
is the LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge,
the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing.
After the last address (1FFFh) is reached, the address
latch will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address information has been transmitted,
data
the
FM24CL64B can begin. For a read operation the
FM24CL64B will place 8 data bits on the bus then
wait for an acknowledge from the master. If the
acknowledge occurs, the FM24CL64B will transfer
the next sequential byte. If the acknowledge is not
sent, the FM24CL64B will end the read operation.
For a write operation, the FM24CL64B will accept 8
data bits from the master then send an acknowledge.
All data transfer occurs MSB (most significant bit)
first.
the bus master and
transfer between
the FM24CL64B
increments
Rev. 1.2
Feb. 2011
FM24CL64B
Memory Operation
The FM24CL64B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24CL64B and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory
technologies,
there is no effective write delay with F-RAM. Since
the read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
including read or write can occur
operation
following a write. Acknowledge
immediately
polling, a
to
determine if a write is complete is unnecessary and
will always return a ready condition.
Internally, an actual memory write occurs after the
8th data bit is transferred. It will be complete before
the acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using start or stop
condition prior to the 8th data bit. The FM24CL64B
uses no page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL64B will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figure 5 below illustrates both a single-byte and
multiple-byte write cycles.
technique used with EEPROMs
Page 5 of 13
By Master
Start
Address & Data
FM24CL64B
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
A
Data Byte
A P
By FM24CL64
Start
By Master
Acknowledge
Figure 5. Single Byte Write
Address & Data
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
A
Data Byte
A
Data Byte
A
P
By FM24CL64
Acknowledge
Figure 6. Multiple Byte Write
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24CL64B uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24CL64B uses an
internal latch to supply the address for a read
operation. A current address read uses the existing
value in the address latch as a starting place for the
read operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving
the
FM24CL64B will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
complete device
address,
the
Each time the bus master acknowledges a byte,
this indicates that the FM24CL64B should read
out the next sequential byte.
Rev. 1.2
Feb. 2011
likely create a bus contention as
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most
the
FM24CL64B attempts to read out additional data
onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
cycle.
4. The bus master issues a start in the 9th clock
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the device address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the address bytes
that are loaded into the internal address latch. After
the FM24CL64B acknowledges the address, the bus
Page 6 of 13
master issues a start condition. This simultaneously
aborts the write operation and allows the read
command to be issued with the device address LSB
FM24CL64B
set to a 1. The operation is now a current address
read.
By Master
Start
Address
No
Acknowledge
Stop
S
Slave Address
1
A
Data Byte
1 P
By FM24CL64
Acknowledge
Data
Figure 7. Current Address Read
By Master
Start
Address
Acknowledge
No
Acknowledge
Stop
S
Slave Address
1
A
Data Byte
A
Data Byte
1 P
By FM24CL64
Start
By Master
Acknowledge
Data
Figure 8. Sequential Read
Address
Start
Address
No
Acknowledge
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
A
S
Slave Address
1
A
Data Byte
1 P
By FM24CL64
Acknowledge
Data
Figure 9. Selective (Random) Read
Rev. 1.2
Feb. 2011
Page 7 of 13
Electrical Specifications
FM24CL64B
Absolute Maximum Ratings
Symbol
VDD
VIN
Description
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V *
-55°C to +125°C
260° C
4kV
1.25kV
300V
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified)
Symbol Parameter
VDD
IDD
Min
2.7
Max
3.65
Units
Typ
3.3
Main Power Supply
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
@ IOL = 3.0 mA
Address Input Resistance (WP, A2-A0)
For VIN = VIL (max)
For VIN = VIH (min)
Input Hysteresis
ISB
ILI
ILO
VIL
VIH
VOL
RIN
100
170
300
6
±1
±1
0.3 VDD
VDD + 0.3
0.4
Notes
1
2
3
3
5
V
µA
µA
µA
µA
µA
µA
V
V
V
KΩ
MΩ
V
3
-0.3
0.7 VDD
40
1
0.05 VDD
VHYS
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is strong (40KΩ) when the input voltage is below VIL and weak (1MΩ) when the
4
input voltage is above VIH.
Rev. 1.2
Feb. 2011
Page 8 of 13
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