23LC1024数据手册(23LC1024).pdf

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23A1024/23LC1024

Device Selection Table

Features:

Pin Function Table

Description:

Package Types (not to scale)

1.0 Electrical Characteristics

Absolute Maximum Ratings (†)

TABLE 1-1: DC Characteristics

TABLE 1-2: AC Characteristics

TABLE 1-3: AC Test Conditions

FIGURE 1-1: Hold Timing

FIGURE 1-2: Serial Input Timing (SPI Mode)

FIGURE 1-3: Serial Output Timing (SPI Mode)

2.0 Functional Description

2.1 Principles of Operation

2.2 Modes of Operation

2.3 Read Sequence

2.4 Write Sequence

TABLE 2-1: Instruction set

FIGURE 2-1: Byte Read Sequence (SPI Mode)

FIGURE 2-2: Byte Write Sequence (spi mode)

FIGURE 2-3: Page Read Sequence (spi Mode)

FIGURE 2-4: Page Write Sequence (spi mode)

FIGURE 2-5: Sequential Read Sequence (spi mode)

FIGURE 2-6: Sequential Write Sequence (spi mode)

2.5 Read Mode Register Instruction (RDMR)

TABLE 2-2: Mode Register

FIGURE 2-7: Read Mode Register Timing Sequence (rdMr)

2.6 Write Mode Register Instruction (WRMR)

FIGURE 2-8: Write Mode Register Timing Sequence (wrMr)

2.7 Power-On State

3.0 Pin Descriptions

TABLE 3-1: Pin Function Table

3.1 Chip Select (CS)

3.2 Serial Output (SO)

3.3 Serial Input (SI)

3.4 Serial Dual Interface Pins(SIO0, SIO1)

3.5 Serial Quad Interface Pins (SIO0 – SIO3)

3.6 Serial Clock (SCK)

3.7 Hold Function (HOLD)

3.8 SPI/SDI and SQI Pin Designations

4.0 Dual and Quad Serial Mode

4.1 Dual Interface Mode

4.2 Quad Interface Mode

FIGURE 4-2: Byte Read Mode SDI

FIGURE 4-3: Byte Write Mode SDI

FIGURE 4-4: Enter SQI Mode (EQIO) from SPI mode

4.3 Exit SDI or SQI Mode

FIGURE 4-5: Byte Read Mode SQII

FIGURE 4-6: Byte Write Mode SQI

FIGURE 4-7: RESET SDI Mode (RSTIO) – from SDi Mode

FIGURE 4-8: RESET SDI/sqi Mode (RSTIO) – from SQI mode

5.0 Packaging Information

5.1 Package Marking Information

Appendix A: Revision History

Product ID System

Trademarks

Worldwide Sales

23A1024/23LC1024 1Mbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table Part Number 23A1024 23LC1024 VCC Range 1.7-2.2V 2.5-5.5V Dual I/O (SDI) Yes Yes Quad I/O (SQI) Yes Yes Max Clock Frequency 20 MHz 20 MHz Packages SN, ST, P SN, ST, P Features: • SPI-Compatible Bus Interface: - 20 MHz Clock rate - SPI/SDI/SQI mode • Low-Power CMOS Technology: - Read Current: 3 mA at 5.5V, 20 MHz - Standby Current: 4 A at +85°C • Unlimited Read and Write Cycles • Zero Write Time • 128K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential mode for Reads and Writes • High Reliability • Temperature Range Supported: - Industrial (I): -40C to +85C • Pb-Free and RoHS Compliant, Halogen Free • 8 Lead SOIC, TSSOP and PDIP Packages Pin Function Table Name CS SO/SIO1 SIO2 Vss SI/SIO0 SCK HOLD/SIO3 Vcc Function Chip Select Input Serial Output/SDI/SQI Pin SQI Pin Ground Serial Input/SDI/SQI Pin Serial Clock Hold/SQI Pin Power Supply Description: The Microchip Technology Inc. 23A1024/23LC1024 are 1 Mbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The 23A1024/23LC1024 is available in standard packages including 8-lead SOIC, PDIP and advanced 8-lead TSSOP. Package Types (not to scale) SOIC/TSSOP/PDIP CS SO/SIO1 SIO2 Vss 1 2 3 4 8 7 6 5 Vcc HOLD/SIO3 SCK SI/SIO0  2011 Microchip Technology Inc. Preliminary DS25142A-page 1

23A1024/23LC1024 ELECTRICAL CHARACTERISTICS 1.0 Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature under bias...............................................................................................................-40°C to +85°C † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. Industrial (I): TA = -40°C to +85°C Min. Typ(1) Max. Units Test Conditions D010 CINT Input capacitance D011 VDR RAM data retention voltage (2) — 1.0 Note 1: This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature (25°C). 2: This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested. DS25142A-page 2 Preliminary  2011 Microchip Technology Inc. DC CHARACTERISTICS TABLE 1-1: DC CHARACTERISTICS Param. Sym. No. D001 Characteristic VCC Supply voltage D002 VIH D003 VIL D004 VOL D005 VOH D006 ILI D007 ILO High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current D008 ICC Read Operating current D009 ICCS Standby current 1.7 2.5 .7 VCC -0.3 — — — — — 2.2 5.5 VCC +0.3 0.2xVCC 0.10xVCC 0.2 VCC -0.5 — — — — — — — — — 1 3 1 4 V V V V V 23A1024 23LC1024 23A1024 23LC1024 IOL = 1 mA IOH = -400 A A CS = VCC, VIN = VSS OR VCC A CS = VCC, VOUT = VSS OR VCC FCLK = 20 MHz; SO = O, 2.2V FCLK = 20 MHz; SO = O, 5.5V CS = VCC = 2.2V, Inputs tied to VCC or VSS CS = VCC = 5.5V, Inputs tied to VCC or VSS VCC = 0V, f = 1 MHz, Ta = 25°C (Note 1) mA mA A A pF V — ±1 ±1 10 10 4 10 7 —

23A1024/23LC1024 Industrial (I): TA = -40°C to +85°C Min. Max. Units Test Conditions TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Characteristic FCLK Clock frequency TCSS CS setup time TCSH CS hold time TCSD CS disable time Data setup time Tsu Data hold time THD TR CLK rise time CLK fall time TF Clock high time THI Clock low time TLO TCLD Clock delay time TV THO TDIS Output disable time THS THH THZ THV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note 1: This parameter is periodically sampled and not 100% tested. HOLD setup time HOLD hold time HOLD low to output High-Z HOLD high to output valid Output valid from clock low Output hold time 20 — — — — — 20 20 — — — 25 — 20 — — — 50 — 25 50 25 10 10 — — 25 25 25 — 0 — 10 10 10 — MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns — ns — ns — ns — Note 1 Note 1 Note 1 TABLE 1-3: AC Waveform: AC TEST CONDITIONS Input pulse level Input rise/fall time Operating temperature CL = 30 pF 0.1 VCC to 0.9 VCC 5 ns -40°C to +85°C — Timing Measurement Reference Level: Input Output 0.5 VCC 0.5 VCC  2011 Microchip Technology Inc. Preliminary DS25142A-page 3

23A1024/23LC1024 FIGURE 1-1: HOLD TIMING 15 n + 2 n + 1 16 17 n n + 2 n + 1 n 15 16 High-Impedance 18 Don’t Care n 5 n n - 1 n - 1 CS SCK SO SI HOLD FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE) 2 5 6 MSB in CS SCK SI SO 7 8 3 LSB in High-Impedance FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE) CS SCK SO SI 9 10 12 MSB out 13 Don’t Care 4 11 3 14 LSB out DS25142A-page 4 Preliminary  2011 Microchip Technology Inc.

23A1024/23LC1024 After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin. Write Sequence 2.4 Prior to any attempt to write data to the 23A1024/ 23LC1024, the device must be selected by bringing CS low. Once the device is selected, the Write command can be started by issuing a WRITE instruction, followed by the 24-bit address, with the first seven MSB’s of the address being a “don’t care” bit, and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Address Pointer is automati- cally incremented. When the Address Pointer reaches the highest address (1FFFFh), the address counter rolls over to (00000h). This allows the operation to continue indefinitely, however, previous data will be overwritten. 2.0 FUNCTIONAL DESCRIPTION Principles of Operation 2.1 The 23A1024/23LC1024 is an 1 Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcon- trollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. In addition, the 23A1024/ 23LC1024 is also capable of operating in SDI/SQI high speed SPI mode. The 23A1024/23LC1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Modes of Operation 2.2 The 23X1024 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks (Figure 2-1, Figure 2-2). Page Operation – is selected when bits 7 and 6 in the MODE register are set to 10. The 23X1024 has 4096 pages of 32 bytes. In this mode, the read and write oper- ations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential opera- tion allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 (Figure 2-5, Figure 2-6). Read Sequence 2.3 The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23A1024/ 23LC1024 followed by the 24-bit address, with the first seven MSB’s of the address being a “don’t care” bit.  2011 Microchip Technology Inc. Preliminary DS25142A-page 5

23A1024/23LC1024 TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format READ WRITE EDIO EQIO RSTIO RDMR WRMR 0000 0011 0000 0010 0011 1011 0011 1000 1111 1111 0000 0101 0000 0001 Description Read data from memory array beginning at selected address Hex Code 0x03 0x02 Write data to memory array beginning at selected address 0x3B Enter Dual I/O access 0x38 Enter Quad I/O access 0xFF Reset Dual and Quad I/O access 0x05 Read Mode Register 0x01 Write Mode Register FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE) CS SCK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 Instruction 00 000 24-bit Address 0 1 1 23 22 21 20 2 1 0 High-Impedance Data Out 4 3 2 1 0 7 6 5 FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE) CS SCK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 Instruction 00 000 0 1 0 24-bit Address 23 22 21 20 2 1 0 7 6 Data Byte 5 3 4 2 1 0 High-Impedance DS25142A-page 6 Preliminary  2011 Microchip Technology Inc.

FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) 23A1024/23LC1024 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 Instruction 00 000 0 1 1 24-bit Address 23 22 21 20 2 Page X, Word Y 1 0 High Impedance 7 6 40 41 42 43 44 45 46 47 Page X, Word Y 5 4 3 2 1 0 CS SCK SI SO CS SCK SI SO 7 6 Page X, Word Y+1 1 5 4 3 2 Page X, Word 31 0 7 6 5 4 3 2 1 0 7 6 Page X, Word 0 5 4 3 2 1 0 FIGURE 2-4: PAGE WRITE SEQUENCE (SPI MODE) CS SCK SI CS SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 Instruction 00000 0 1 0 24-bit Address 23 22 21 20 2 Page X, Word Y 1 0 7 6 40 41 42 43 44 45 46 47 Page X, Word Y 5 4 3 2 1 0 Page X, Word Y+1 1 5 4 3 2 Page X, Word 31 0 7 6 5 4 3 2 1 0 7 6 Page X, Word 0 5 4 3 2 1 0 7 6  2011 Microchip Technology Inc. Preliminary DS25142A-page 7

23A1024/23LC1024 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 Instruction 00 000 0 1 1 24-bit Address 23 22 21 20 2 1 0 Page X, Word Y 2 5 4 3 1 0 CS SCK SI SO CS SCK SI SO CS SCK SI SO 7 6 0 7 6 Page X, Word 31 7 6 5 4 3 2 1 0 7 Page X+1, Word 0 6 1 5 4 3 2 Page X+1, Word 1 1 5 4 3 2 Page X+1, Word 31 6 5 4 3 2 1 0 7 Page X+n, Word 1 6 5 4 3 2 1 0 7 Page X+n, Word 31 6 1 5 4 3 2 7 0 0 DS25142A-page 8 Preliminary  2011 Microchip Technology Inc.

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