4514 CMOS 四位锁存、4-16高有效译码器.pdf-资料库

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October 1987 Revised January 1999 C D 4 5 1 4 B C • C D 4 5 1 5 B C 4 - B / i t L a t c h e d 4 - t o - 1 6 L n e D e c o d e r s i CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima- rily used in decoding applications where low power dissipa- tion and/or high noise immunity is required. The CD4514BC (output active high option) presents a logi- cal “1” at the selected output, whereas the CD4515BC pre- sents a logical “0” at the selected output. The input latches are R–S type flip-flops, which hold the last input data pre- sented prior to the strobe transition from “1” to “0”. This input data is decoded and the corresponding output is acti- vated. An output inhibit line is also available. Ordering Code: Features n Wide supply voltage range: n High noise immunity: 0.45 VDD (typ.) n Low power TTL: fan out of 2 compatibility: driving 74L 3.0V to 15V n Low quiescent power dissipation: 0.025 m W/package @ 5.0 VDC n Single supply operation n Input impedance = 1012W n Plug-in replacement for MC14514, MC14515 typically Order Number CD4514BCWM CD4514BCN CD4515BCWM CD4515BCN Package Number Package Diagram M24B N24A M24B N24A 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for SOIC and DIP Top View © 1999 Fairchild Semiconductor Corporation DS005994.prf www.fairchildsemi.com

C B 5 1 5 4 D C • C B 4 1 5 4 D C Truth Table Decode Truth Table (Strobe = 1) Inhibit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data Inputs C B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X Selected Output CD4514 = Logic “1” CD4515 = Logic “0” S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 All Outputs = 0, CD4514 All Outputs = 1, CD4515 X = Don’t Care Logic Diagram www.fairchildsemi.com 2

Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) - 40 C to +85 C CD4514BC, CD4515BC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device opera- tion. Note 2: VSS = 0V unless otherwise specified. 3V to 15V 0V to VDD C D 4 5 1 4 B C • C D 4 5 1 5 B C Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) - 0.5V to +18V - 0.5V to VDD + 0.5V - 65 C to +150 C 700 mW 500 mW 260 C DC Electrical Characteristics (Note 2) CD4514BC, CD4515BC Symbol Parameter Conditions IDD VOL Quiescent Device Current LOW Level Output Voltage VOH HIGH Level Output Voltage VIL VIH IOL IOH LOW Level Input Voltage HIGH Level Input Voltage LOW Level Output Current (Note 3) HIGH Level Output Current (Note 3) IIN Input Current VDD = 5V, VIN = VDD or V SS VDD = 10V, VIN = VDD or V SS VDD = 15V, VIN = VDD or V SS VIL = 0V, VIH = VDD, |IO| < 1 m A VDD = 5V VDD = 10V VDD = 15V VIL = 0V, VIH = VDD, |IO| < 1 m A VDD = 5V VDD = 10V VDD = 15V |IO| < 1 m A VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V |IO| < 1 m A VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 3: IOH and IOL are tested one output at a time. 4.95 9.95 14.95 4.95 9.95 14.95 - 40 C Min Max 20 40 80 0.05 0.05 0.05 1.5 3.0 4.0 - 0.3 0.3 3.5 7.0 11.0 0.52 1.3 3.6 - 0.52 - 1.3 - 3.6 Min +25 C Typ 0.005 0.010 0.015 0 0 0 5.0 10.0 15.0 2.25 4.50 6.75 2.75 3.5 5.50 7.0 8.25 11.0 0.88 0.44 2.25 1.1 3.0 8.8 - 0.44 - 0.88 - 2.25 - 1.1 - 8.8 - 3.0 - 10- 5 10- 5 Max 20 40 80 0.05 0.05 0.05 1.5 3.0 4.0 +85 C Max 150 300 600 0.05 0.05 0.05 1.5 3.0 4.0 Min 4.95 9.95 14.95 3.5 7.0 11.0 0.36 0.90 2.4 - 0.36 - 0.90 - 2.4 - 0.3 0.3 - 1.0 1.0 Units m A m A m A V V V V V V V V V V V V mA mA mA mA mA mA m A m A 3 www.fairchildsemi.com

AC Electrical Characteristics (Note 4) All types CL = 50 pF, TA = 25 C, tr = tf = 20 ns unless otherwise specified Symbol Parameter Conditions Min Typ C B 5 1 5 4 D C • C B 4 1 5 4 D C tTHL, tTLH Transition Times tPLH, tPHL Propagation Delay Times tPLH, tPHL Inhibit Propagation Delay Times tSU tWH Setup Time Strobe Pulse Width VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Per Package (Note 5) Any Input (Note 6) Max 200 100 80 1100 450 300 800 300 200 250 100 75 350 100 75 7.5 100 50 40 550 225 150 400 150 100 125 50 38 175 50 38 150 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Power Dissipation Capacitance Input Capacitance CPD CIN Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note, AN-90. Note 6: Capacitance is guaranteed by periodic testing. www.fairchildsemi.com 4

AC Test Circuit and Switching Time Waveforms C D 4 5 1 4 B C • C D 4 5 1 5 B C FIGURE 1. 5 www.fairchildsemi.com

C B 5 1 5 4 D C • C B 4 1 5 4 D C Applications Two CD4512 8-channel data selectors are used here with the CD4514B 4-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3-STATE data bus to a data distributor for rearrangement and entry into 16 output regis- ters. In this way sequential data can be re-routed or inter- mixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the 8 inputs on both CD4512 data selectors. One register is assigned to each input. The signals on A0, A1 and A2 choose 1-of-8 inputs for transfer out to the 3-STATE data bus. A fourth signal, labelled Dis, disables one of the CD4512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1–16, the rate of transfer of the sequential information can also be varied. That is, if the CD4512 were addressed at a rate that is 8 times faster than the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be trans- ferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the 3-STATE bus is redistributed by the CD4514B 4-bit latch/decoder. Using the 4-bit address, INA–IND, the information on the inhibit line can be trans- ferred to the addressed output line to the desired output registers, A–P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input regis- ters can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizon- tal, vertical, or other methods of data slicing can be imple- mented. www.fairchildsemi.com 6

Physical Dimensions inches (millimeters) unless otherwise noted C D 4 5 1 4 B C • C D 4 5 1 5 B C 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M24B 7 www.fairchildsemi.com

i s r e d o c e D e n L 6 1 - o t - 4 d e h c t a L t i / B - 4 C B 5 1 5 4 D C • C B 4 1 5 4 D C Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Package Number N24A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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4514 CMOS 四位锁存、4-16高有效译码器.pdf

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