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ST-VX6593摄像头模组规格书.pdf
1 Overview
Table 1. Technical specification
1.1 VX6953CB use in a system with a hardware coprocessor
Figure 1. VX6953CB in system with processor
1.2 VX6953CB use in a system with software image processing
Figure 2. VX6953CB in a system with software image processing
1.3 Reference documents
Table 2. Reference documents
2 Device pinout
Figure 3. VX6953CB module pinout (viewed from bottom of camera module)
Table 3. Pin descriptions
3 Functional description
3.1 Analog video block
3.1.1 Block diagram
Figure 4. Overview of analog video block
3.2 Digital video block
3.2.1 Dark calibration algorithm
3.3 Device operating modes
Figure 5. System state diagram
3.3.1 Power off
3.3.2 Hardware standby
3.3.3 Software standby
3.3.4 Streaming
3.4 Power management
Table 4. Power management matrix
3.4.1 Power-up procedure
Table 5. Power-up sequence timing constraints for CCP2/CSI2 communications
Figure 6. VX6953CB power-up sequence for CCP2 mode
Figure 7. VX6953CB power-up sequence for CSI-2 mode
3.4.2 Power-down procedure
Table 6. Power-down sequence timing constraints for CSI2 communications
Figure 8. VX6953CB power-down sequence for CSI-2 mode
3.4.3 Internal power-on reset (POR)
Figure 9. POR timing
Table 7. POR cell characteristics
3.4.4 Failsafe signals
3.5 Clock and frame rate timing
3.5.1 Video frame rate control
3.5.2 PLL and clock input
Table 8. System input clock frequency range
3.5.3 Clock input type
Figure 10. Clock input types
3.6 Control and video interface formats
3.6.1 CCP serial data link
3.6.2 CSI-2 serial data link
Figure 11. CSI serial data link
3.6.3 CCI serial control bus
4 Register map
4.1 Status registers [0x0000 to 0x000F]
Table 9. Status registers [0x0000 to 0x000F]
4.2 Frame format description registers [0x0040 to 0x007F]
Table 10. Frame format description registers [0x0040 to 0x007F]
4.3 Analog gain description registers [0x0080 to 0x0097]
Table 11. Analog gain description [0x0080 to 0x0093]
4.4 Data format description registers [0x00C0 to 0x00FF]
Table 12. Data format description registers [0x00C0 to 0x00FF]
4.5 Setup registers [0x0100 to 0x01FF]
Table 13. Setup registers [0x0100 to 0x01FF]
4.6 Integration time and gain registers [0x0200 to 0x02FF]
Table 14. Integration time and gain registers [0x0200 to 0x02FF]
4.7 Video timing registers [0x0300 to 0x03FF]
Table 15. Video timing registers [0x0300 to 0x03FF]
4.8 Image scaling registers [0x0400 to 0x04FF]
Table 16. Image scaling registers [0x0400 to 0x04FF]
4.9 Image compression registers [0x0500 to 0x05FF]
Table 17. Image compression registers [0x0500 to 0x05FF]
4.10 Test pattern registers [0x0600 to 0x06FF]
Table 18. Test pattern registers [0x0600 to 0x06FF]
4.11 Fifo water mark [0x0700 to 0x0701]
Table 19. Fifo water mark registers [0x0700 to 0x0701]
4.12 DPHY [0x0810 to 0x0811]
Table 20. DPHY registers [0x0810 to 0x0811]
4.13 Binning [0x0900 to 0x0902] and [0x170C to 0x1719]
Table 21. Binning registers [0x0900 to 0x0902]
4.14 Shading correction [0x0B00]
Table 22. Shading correction registers [0x0B00]
4.15 Defect correction [0x0B05 to 0x0B09]
Table 23. Defect correction registers [0x0B05 to 0x0B09]
4.16 EDOF [0x0B80 to 0x0B8A]
Table 24. EDOF registers [0x0B80 to 0x0B8A]
4.17 Color feedback registers [0x0B8C to 0x0B95]
Table 25. Color feedback registers [0x0B8C to 0x0B95]
4.18 Integration time and gain parameter limit registers [0x1000 to 0x10FF]
Table 26. Integration time and gain parameter limit registers [0x1000 to 0x10FF]
4.19 Video timing parameter limit registers [0x1100 to 0x11FF]
Table 27. Video timing parameter limit registers [0x1100 to 0x11FF]
4.20 Image scaling parameter limit registers [0x1200 to 0x120B]
Table 28. Image scaling parameter limit registers [0x1200 to 0x120B]
4.21 Image compression parameter registers [0x1300 to 0x13FF]
Table 29. Image compression parameter limit registers [0x1300 to 0x13FF]
4.22 CSI lane mode capability [0x1600 to 0x1602]
Table 30. CSI lane mode capability registers [0x1600 - 0x1602]
4.23 Binning capability [0x1700 to 0x170B]
Table 31. Binning capability registers [0x1700 to 0x170B]
4.24 Manufacturer specific registers - Clipper 1 [0x31E8 to 0x31EB]
Table 32. Manufacturer specific registers [0x31E8 to 0x31EB]
5 Video data interface
5.1 Frame format
Figure 12. VX6953CB CCP frame format
Figure 13. VX6953CB CSI-2 frame format
6 Video timing
6.1 Output size
6.1.1 Programmable addressable region of the pixel array
Figure 14. Programmable addressable region of the pixel array
6.1.2 Programmable width and height for output image data
Figure 15. Output size within a CCP data frame
6.1.3 Scaling
Figure 16. Scaling modes
Figure 17. Scaler quality
Figure 18. Example image full scaled by a downscale factor of 2
6.1.4 Subsampling
Figure 19. Subsample readout example
6.1.5 Binning
Table 33. Binning register settings
Figure 20. Binning repair
6.2 Video timing
6.2.1 PLL block
Figure 21. VX6953CB clock relationships
6.2.2 Spread spectrum clock generator
6.2.3 Framerate
Table 34. External clock frequency examples - 5.0 Mpixel RAW10 14.5 fps (CSI-2)
Table 35. External clock frequency examples - 5.0 Mpixel RAW10 15 fps (CSI-2)
Table 36. External clock frequency examples - 5.0 Mpixel 10-8 compressed 15 fps
Table 37. Example - 5.0 Mpixel 10-8 compressed 16.65 fps (CSI-2)
Table 38. External clock frequency examples - 1080x1920 in 10-8 bit @ 30fps (CCP)
Table 39. 720x1280 @ 30 fps in RAW10 (CSI2/CCP2)
6.2.4 Derating
Figure 22. Timing block diagram
Figure 23. SMIA output timing
Figure 24. FIFO water mark control
6.3 Bayer pattern
Figure 25. Bayer pattern
6.4 Image compression
6.5 Exposure and gain control
6.5.1 Analogue gain model
Figure 26. Analogue gain register format
Table 40. Analog gain control
6.5.2 Digital gain
6.5.3 Integration and gain parameter retiming
7 Application
7.1 Schematics
Figure 27. Example of a mobile camera application (CCP2)
Figure 28. Example of a mobile camera application (CSI2)
7.2 Personality file and firmware updates
8 EDOF control
Figure 29. What is sharp?
Figure 30. EDoF main principle
8.1 EDoF capabilities
8.2 Control Interface
8.3 EDOF control registers [0x0B80 to 0x0B8A]
Table 41. EDOF registers [0x0B80 to 0x0B8A]
8.3.1 EDoF_Mode (0xB80)
8.3.2 EDoF_est_focus_distance (0x0B82)
8.3.3 EDoF tuning sliders (0xB83 to 0x0B85)
8.3.4 EDoF focus distance (0x0B88)
8.3.5 EDoF estimation control (0x0B8A)
Figure 31. Focus strategy weightings
8.4 Supermacro mode
8.5 Video modes and EDoF
8.6 EDoF and white balance
Table 42. Color feedback registers [0x0B8C to 0x0B95]
9 Image optimization
Figure 32. Processing pipe
9.1 Defect categorization
9.1.1 Pixel defects
9.1.2 Sensor array area definition
Figure 33. VX6953CB pixel defect test area
9.1.3 Pixel fault numbering convention
Figure 34. Pixel numbering notation
9.1.4 Single pixel faults
Figure 35. Single pixel fault
9.1.5 Couplet definition
Figure 36. General couplet example
9.1.6 Physical aberrations
Figure 37. Test region definition
Figure 38. Scan array for blemish
Figure 39. Fail map
Figure 40. Contiguous pixel example
9.2 Defect correction
Figure 41. Image showing defective pixels
Figure 42. Block diagram of dynamic defect correction block
Figure 43. Dynamic defect correction output example
Figure 44. Corrected Bayer pattern
9.3 Mapped couplet correction (Bruce)
9.4 Green imbalance correction
Figure 45. Green imbalance correction plots
9.5 Lens shading correction
Figure 46. Lens shading images
10 NVM contents
10.1 Green imbalance corrector
10.2 Lens shading gridiron correction
10.3 Sensitivity data
10.4 NVM map
11 EMC recommendations
12 Electrical characteristics
12.1 Operating conditions
Table 43. Operating conditions
12.2 Absolute maximum ratings
Table 44. Absolute maximum ratings
12.3 Power supply - VDIG, VANA
Table 45. Power supplies VDIG, VANA
12.3.1 Power supply (peak current) - VDIG, VANA
Table 46. In-rush current VDIG, VANA for CCP2 interface
Table 47. In-rush current VDIG, VANA for CSI-2 interface
12.3.2 Power supply ripple requirement
Table 48. Ripple requirement
12.4 System clock - EXTCLK
Table 49. System clock - EXTCLK
12.5 Power down control - XSHUTDOWN
Table 50. Power down control - XSHUTDOWN
12.6 CCI interface - SDA, SCL
12.6.1 CCI interface - DC specification
Table 51. CCI interface
12.6.2 CCI interface - timing characteristics
Table 52. CCI interface - timing characteristics
Figure 47. CCI AC characteristics
12.7 CCP interface
12.7.1 CCP interface - DC specification
Table 53. CCP interface - DC specification
12.7.2 CCP interface - timing characteristics
Table 54. CCP interface - timing characteristics
Figure 48. SubLVDS AC timing
12.8 CSI-2 interface
12.8.1 CSI-2 interface - DC specification
Table 55. CSI-2 interface - high speed mode - DC specification
Table 56. CSI-2 interface - low power mode - DC specification
12.8.2 CSI-2 interface - AC specification
Table 57. CSI-2 interface - high speed mode - AC specification
Table 58. CSI-2 interface - low power mode - AC specification
13 Optical specification
13.1 Lens characteristics
Table 59. Typical lens design characteristics for first source lens supplier
13.2 Text, 1D and 2D codes reading
Figure 49. Barcode and QR code examples
Table 60. QR code (2D)resolution reading capability
14 Mechanical
14.1 Packaging and delivery
Figure 50. Marking diagram
Table 61. Substrate marking codification
14.2 Inner box labelling
14.3 Packing
14.4 Module outline
Table 62. Outline drawing information
15 Ordering information
Table 63. Device summary
16 User precaution
17 Acronyms and abbreviations
Table 64. Acronyms and abbreviations
18 Revision history
Table 65. Document revision history
VX6953CB
5.1 megapixel EDOF camera module
Datasheet - production data
Description
The VX6953CB camera module is designed for
use across a range of mobile phone handsets and
accessories. It embeds high quality still camera
functions and also supports HD video.
The VX6953CB produces raw Bayer 5 Mpixel
images at 15 fps in RAW10. It supports the CCI
control as well as CCP 2.0 and CSI-2 data
interfaces.
The module design is optimized for both footprint
and height. It provides excellent image quality at
focus distances from 15 cm in “Super macro
mode” (bar code) and from 40 cm to infinity in
“Normal mode”.
A separate hardware accelerator device (for
example, an STV0987) can be integrated in the
phone system to run the associated image
processing algorithms in hardware where the
baseband cannot support this processing load.
The sensor is designed to work with any other
host with a MIPI or SMIA interface.
Features
• Extended depth of field (EDoF) technology
• Data formats: RAW8, RAW10 and 10-8
compressed
• SMIA profile 2 compliant
• MIPI CSI-2 (D-PHY v1.0 compliant) and SMIA
CCP2 video data interface
• Maximum data rate: 640 Mbps for CCP2 and
800 Mbps for CSI-2
• 100 KHz to 400 KHz CCI command interface
• EMC shielding
• Ultra low power standby mode, 30 μW (typ.)
• Binning modes (2 x 2)
• HD video formats (1080p30, 720p30)
• Pixel defect correction
• Nine terms lens shading corrections, bi-cubic
correction data available
• 512-byte NVM memory for calibration
March 2013
This is information on a product in full production.
8209023 Rev 5
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www.st.com
1
Contents
Contents
VX6953CB
1
2
3
4
2/107
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VX6953CB use in a system with a hardware coprocessor . . . . . . . . . . . . 12
1.1
1.2
VX6953CB use in a system with software image processing . . . . . . . . . 13
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3
Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1
Dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1
Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2
Software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3
3.3.4
Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
3.4.2
Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3
3.4.4
Failsafe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock and frame rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Video frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1
PLL and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2
3.5.3
Clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control and video interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CCP serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6.1
3.6.2
CSI-2 serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CCI serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6.3
3.2
3.5
3.6
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status registers [0x0000 to 0x000F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
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Contents
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . 30
4.2
Analog gain description registers [0x0080 to 0x0097] . . . . . . . . . . . . . . . 31
4.3
Data format description registers [0x00C0 to 0x00FF] . . . . . . . . . . . . . . . 32
4.4
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . 34
4.6
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . 35
4.7
Image scaling registers [0x0400 to 0x04FF] . . . . . . . . . . . . . . . . . . . . . . 36
4.8
Image compression registers [0x0500 to 0x05FF] . . . . . . . . . . . . . . . . . . 37
4.9
Test pattern registers [0x0600 to 0x06FF] . . . . . . . . . . . . . . . . . . . . . . . . 37
4.10
Fifo water mark [0x0700 to 0x0701] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.11
4.12 DPHY [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.13 Binning [0x0900 to 0x0902] and [0x170C to 0x1719] . . . . . . . . . . . . . . . . 38
4.14 Shading correction [0x0B00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.15 Defect correction [0x0B05 to 0x0B09] . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.16 EDOF [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.17 Color feedback registers [0x0B8C to 0x0B95] . . . . . . . . . . . . . . . . . . . . . 40
4.18
Integration time and gain parameter limit registers [0x1000 to 0x10FF] . 41
4.19 Video timing parameter limit registers [0x1100 to 0x11FF] . . . . . . . . . . . . 42
Image scaling parameter limit registers [0x1200 to 0x120B] . . . . . . . . . . 46
4.20
4.21
Image compression parameter registers [0x1300 to 0x13FF] . . . . . . . . . 46
4.22 CSI lane mode capability [0x1600 to 0x1602] . . . . . . . . . . . . . . . . . . . . . 46
4.23 Binning capability [0x1700 to 0x170B] . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.24 Manufacturer specific registers - Clipper 1 [0x31E8 to 0x31EB] . . . . . . . 47
Video data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1
Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.1
6.1.1
Programmable addressable region of the pixel array . . . . . . . . . . . . . . 51
Programmable width and height for output image data . . . . . . . . . . . . . 52
6.1.2
Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3
6.1.4
Subsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5
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VX6953CB
6.2
6.3
6.4
6.5
Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2.1
6.2.2
Spread spectrum clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2.3
6.2.4
Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Image compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Analogue gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5.1
Digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.5.2
6.5.3
Integration and gain parameter retiming . . . . . . . . . . . . . . . . . . . . . . . . 66
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.1
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Personality file and firmware updates . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2
EDOF control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EDoF capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.1
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.2
8.3
EDOF control registers [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . 71
EDoF_Mode (0xB80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.3.1
EDoF_est_focus_distance (0x0B82) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.2
8.3.3
EDoF tuning sliders (0xB83 to 0x0B85) . . . . . . . . . . . . . . . . . . . . . . . . . 73
EDoF focus distance (0x0B88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.4
8.3.5
EDoF estimation control (0x0B8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Supermacro mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Video modes and EDoF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EDoF and white balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.4
8.5
8.6
Image optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1
Defect categorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pixel defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1.1
Sensor array area definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1.2
9.1.3
Pixel fault numbering convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Single pixel faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.1.4
9.1.5
Couplet definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7
8
9
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Contents
10
11
12
9.1.6
Physical aberrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Defect correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Mapped couplet correction (Bruce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Green imbalance correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.2
9.3
9.4
9.5
NVM contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.1 Green imbalance corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2
Lens shading gridiron correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.3 Sensitivity data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.4 NVM map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMC recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.1
12.3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.3 Power supply - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Power supply (peak current) - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . 92
Power supply ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.4 System clock - EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.5 Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.6 CCI interface - SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CCI interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.7 CCP interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CCP interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CCP interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.8 CSI-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CSI-2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CSI-2 interface - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.1
12.6.2
12.7.1
12.7.2
12.8.1
12.8.2
13
Optical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.1
Lens characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Text, 1D and 2D codes reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.2
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Contents
14
15
16
17
18
VX6953CB
Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.1 Packaging and delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.2
Inner box labelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.3 Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.4 Module outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
User precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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List of tables
List of tables
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 1.
Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.
Power management matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.
Power-up sequence timing constraints for CCP2/CSI2 communications . . . . . . . . . . . . . . 20
Table 5.
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 23
Table 6.
POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.
System input clock frequency range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8.
Status registers [0x0000 to 0x000F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9.
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10.
Analog gain description [0x0080 to 0x0093]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11.
Data format description registers [0x00C0 to 0x00FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12.
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13.
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14.
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15.
Image scaling registers [0x0400 to 0x04FF]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16.
Image compression registers [0x0500 to 0x05FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17.
Test pattern registers [0x0600 to 0x06FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18.
Fifo water mark registers [0x0700 to 0x0701]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19.
DPHY registers [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20.
Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 21.
Shading correction registers [0x0B00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22.
Defect correction registers [0x0B05 to 0x0B09] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23.
EDOF registers [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24.
Color feedback registers [0x0B8C to 0x0B95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25.
Integration time and gain parameter limit registers [0x1000 to 0x10FF]. . . . . . . . . . . . . . . 41
Table 26.
Video timing parameter limit registers [0x1100 to 0x11FF]. . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 27.
Image scaling parameter limit registers [0x1200 to 0x120B] . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28.
Image compression parameter limit registers [0x1300 to 0x13FF]. . . . . . . . . . . . . . . . . . . 46
Table 29.
CSI lane mode capability registers [0x1600 - 0x1602] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30.
Table 31.
Binning capability registers [0x1700 to 0x170B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. Manufacturer specific registers [0x31E8 to 0x31EB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33.
Binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
External clock frequency examples - 5.0 Mpixel RAW10 14.5 fps (CSI-2). . . . . . . . . . . . . 58
Table 34.
External clock frequency examples - 5.0 Mpixel RAW10 15 fps (CSI-2) . . . . . . . . . . . . . . 58
Table 35.
External clock frequency examples - 5.0 Mpixel 10-8 compressed 15 fps . . . . . . . . . . . . . 59
Table 36.
Example - 5.0 Mpixel 10-8 compressed 16.65 fps (CSI-2) . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37.
Table 38.
External clock frequency examples - 1080x1920 in 10-8 bit @ 30fps (CCP) . . . . . . . . . . . 59
720x1280 @ 30 fps in RAW10 (CSI2/CCP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39.
Analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 40.
Table 41.
EDOF registers [0x0B80 to 0x0B8A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 42.
Color feedback registers [0x0B8C to 0x0B95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 44.
Power supplies VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 45.
Table 46.
In-rush current VDIG, VANA for CCP2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
In-rush current VDIG, VANA for CSI-2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 47.
Table 48.
Ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8209023 Rev 5
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List of tables
VX6953CB
System clock - EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 49.
Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 50.
CCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 51.
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 52.
CCP interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53.
CCP interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54.
CSI-2 interface - high speed mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 55.
CSI-2 interface - low power mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 56.
CSI-2 interface - high speed mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 57.
CSI-2 interface - low power mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 58.
Table 59.
Typical lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . 99
Table 60. QR code (2D)resolution reading capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 61.
Substrate marking codification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 62. Outline drawing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 63.
Table 64.
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 65.
8/107
8209023 Rev 5
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