ENC28J60英文(ENC28J60(English)).pdf

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Ethernet Controller Features

Buffer

Medium Access Controller (MAC) Features

Physical Layer (PHY) Features

Operational

Package Types

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 Overview

FIGURE 1-1: ENC28J60 Block Diagram

FIGURE 1-2: Typical ENC28J60-Based Interface

TABLE 1-1: Pinout I/O Descriptions

2.0 External Connections

2.1 Oscillator

FIGURE 2-1: Crystal Oscillator Operation

FIGURE 2-2: External Clock Source(1)

2.2 Oscillator Start-up Timer

2.3 CLKOUT Pin

FIGURE 2-3: CLKOUT Transition

2.4 Magnetics, Termination and Other External Components

FIGURE 2-4: ENC28J60 Ethernet Termination and External Connections

2.5 I/O Levels

FIGURE 2-5: Level Shifting Using AND Gates

FIGURE 2-6: Level Shifting Using 3-State Buffers

2.6 LED Configuration

FIGURE 2-7: LEDB Polarity and Reset Configuration Options

TABLE 2-1: LED Blink Stretch Length

3.0 Memory Organization

FIGURE 3-1: ENC28J60 Memory Organization

3.1 Control Registers

TABLE 3-1: ENC28J60 Control Register Map

TABLE 3-2: ENC28J60 Control Register Summary

3.1.1 ECON1 Register

3.1.2 ECON2 Register

3.2 Ethernet Buffer

3.2.1 Receive Buffer

3.2.2 Transmit Buffer

3.2.3 Reading and Writing to the Buffer

3.2.4 DMA Access to the Buffer

FIGURE 3-2: Ethernet Buffer Organization

3.3 PHY Registers

3.3.1 Reading PHY Registers

3.3.2 Writing PHY Registers

3.3.3 Scanning a PHY Register

TABLE 3-3: ENC28J60 PHY Register Summary

3.3.4 PHSTAT Registers

3.3.5 PHID1 and PHID2 Registers

4.0 Serial Peripheral Interface (SPI)

4.1 Overview

FIGURE 4-1: SPI Input Timing

FIGURE 4-2: SPI Output Timing

4.2 SPI Instruction Set

TABLE 4-1: SPI Instruction Set for the ENC28J60

4.2.1 Read Control Register Command

FIGURE 4-3: Read Control Register Command Sequence (ETH Registers)

FIGURE 4-4: Read Control Register Command Sequence (MAC and MII Registers)

4.2.2 Read Buffer Memory Command

4.2.3 Write Control Register Command

FIGURE 4-5: Write Control Register Command Sequence

4.2.4 Write Buffer Memory Command

4.2.5 Bit Field Set Command

4.2.6 Bit Field Clear Command

FIGURE 4-6: Write Buffer Memory Command Sequence

4.2.7 System Reset Command

FIGURE 4-7: System Reset Command Sequence

5.0 Ethernet Overview

5.1 Packet Format

5.1.1 Preamble/Start-of-Frame Delimiter

FIGURE 5-1: Ethernet Packet Format

5.1.2 Destination Address

5.1.3 Source Address

5.1.4 Type/Length

5.1.5 Data

5.1.6 Padding

5.1.7 CRC

6.0 Initialization

6.1 Receive Buffer

6.2 Transmission Buffer

6.3 Receive Filters

6.4 Waiting For OST

6.5 MAC Initialization Settings

6.6 PHY Initialization Settings

7.0 Transmitting and Receiving Packets

7.1 Transmitting Packets

FIGURE 7-1: Format for Per Packet Control Bytes

FIGURE 7-2: Sample TRansmit Packet Layout

TABLE 7-1: Transmit Status Vectors

TABLE 7-2: Summary of Registers Used for Packet Transmission

7.2 Receiving Packets

7.2.1 Enabling Reception

7.2.2 Receive Packet Layout

FIGURE 7-3: Sample Receive Packet Layout

TABLE 7-3: Receive Status Vectors

7.2.3 Reading Received Packets

EXAMPLE 7-1: Random Access Address Calculation

7.2.4 Freeing Receive Buffer Space

7.2.5 Receive Buffer Free Space

EXAMPLE 7-2: Receive Buffer Free Space Calculation

TABLE 7-4: Summary of Registers Used for Packet Reception

8.0 Receive Filters

FIGURE 8-1: Receive Filtering Using OR Logic

FIGURE 8-2: Receive Filtering Using AND Logic

8.1 Unicast Filter

8.2 Pattern Match Filter

FIGURE 8-3: Sample Pattern Match Format

8.3 Magic Packet™ Filter

FIGURE 8-4: SAMPLE MAGIC PACKET™ Format

8.4 Hash Table Filter

8.5 Multicast Filter

8.6 Broadcast Filter

9.0 Duplex Mode Configuration and Negotiation

9.1 Half-Duplex Operation

9.2 Full-Duplex Operation

10.0 Flow Control

10.1 Half-Duplex Mode

10.2 Full-Duplex Mode

FIGURE 10-1: Sample Full-Duplex Network

TABLE 10-1: Summary of Registers Used with Flow Control

11.0 Reset

FIGURE 11-1: On-Chip Reset Circuit

11.1 Power-on Reset (POR)

11.2 System Reset

11.3 Transmit Only Reset

11.4 Receive Only Reset

11.5 PHY Subsystem Reset

12.0 Interrupts

FIGURE 12-1: ENC28J60 Interrupt Logic

12.1 INT Interrupt Enable (INTIE)

12.1.1 INT Interrupt Registers

12.1.2 Receive Error Interrupt Flag (RXERIF)

12.1.3 Transmit Error Interrupt Flag (TXERIF)

12.1.4 Transmit Interrupt Flag (TXIF)

12.1.5 Link Change Interrupt Flag (LINKIF)

12.1.6 DMA Interrupt Flag (DMAIF)

12.1.7 Receive Packet Pending Interrupt Flag (PKTIF)

12.2 Wake-On-LAN/Remote Wake-up

12.2.1 Setup Steps for Waking Up on a Magic Packet

13.0 Direct Memory Access Controller

13.1 Copying Memory

13.2 Checksum Calculations

TABLE 13-1: Summary of Registers Associated with the DMA Controller

14.0 Power-Down

TABLE 14-1: Summary of Registers Used with Power-Down

15.0 Built-in Self-Test Controller

15.1 Using the BIST

15.2 Random Data Fill Mode

15.3 Address Fill Mode

15.4 Pattern Shift Fill Mode

TABLE 15-1: Summary of Registers Associated with the Self-Test Controller

16.0 Electrical Characteristics

Absolute Maximum Ratings

16.1 DC Characteristics: ENC28J60 (Industrial and Commercial)

TABLE 16-1: AC Characteristics: ENC28J60 (Industrial and Commercial)

TABLE 16-2: Oscillator Timing Characteristics

TABLE 16-3: Reset AC Characteristics

TABLE 16-4: CLKOUT Pin AC Characteristics

TABLE 16-5: Requirements for External Magnetics

FIGURE 16-1: SPI Input Timing

FIGURE 16-2: SPI Output Timing

TABLE 16-6: SPI Interface AC Characteristics

17.0 Packaging Information

17.1 Package Marking Information

17.2 Package Details

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

28-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC)

28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)

28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) – With 0.55 mm Contact Length (S...

INDEX

The Microchip Web Site

Customer Change Notification Service

Customer Support

Reader Response

Product Identification System

Worldwide Sales and Service

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39662B-page ii Preliminary © 2006 Microchip Technology Inc.

ENC28J60 Stand-Alone Ethernet Controller with SPI Interface Ethernet Controller Features Operational IEEE 802.3 compatible Ethernet controller Integrated MAC and 10BASE-T PHY Supports one 10BASE-T port with automatic polarity detection and correction Supports Full and Half-Duplex modes Programmable automatic retransmit on collision Programmable padding and CRC generation Programmable automatic rejection of erroneous packets Six interrupt sources and one interrupt output pin 25 MHz clock input requirement Clock out pin with programmable prescaler Operating voltage of 3.1V to 3.6V (3.3V typical) 5V tolerant inputs Temperature range: -40°C to +85°C Industrial, 0°C to +70°C Commercial (SSOP only) 28-pin SPDIP, SSOP, SOIC, QFN packages SPI Interface with clock speeds up to 20 MHz Package Types Buffer 8-Kbyte transmit/receive packet dual port SRAM Configurable transmit/receive buffer size Hardware-managed circular receive FIFO Byte-wide random and sequential access with auto-increment Internal DMA for fast data movement Hardware assisted checksum calculation for vari- ous network protocols Medium Access Controller (MAC) Features Supports Unicast, Multicast and Broadcast packets Programmable receive packet filtering and wake-up host on logical AND or OR of the following: - Unicast destination address - Multicast address - Broadcast address - Magic Packet™ - Group destination addresses as defined by 64-bit hash table - Programmable pattern matching of up to 64 bytes at user-defined offset Physical Layer (PHY) Features Loopback mode Two programmable LED outputs for LINK, TX, RX, collision and full/half-duplex status 28-Pin SPDIP, SSOP, SOIC VCAP VSS CLKOUT INT NC* SO SI SCK CS RESET VSSRX TPIN- TPIN+ RBIAS E N C 2 8 J 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD LEDA LEDB VDDOSC OSC2 OSC1 VSSOSC VSSPLL VDDPLL VDDRX VSSTX TPOUT+ TPOUT- VDDTX 28-pin QFN T U O K L C T N I P A C V S S V D D V A D E L B D E L NC* SO SI SCK CS RESET VSSRX 1 2 3 4 5 6 7 28 27 26 25 24 23 22 ENC28J60 8 9 10 11 12 13 14 21 20 19 18 17 16 15 VDDOSC OSC2 OSC1 VSSOSC VSSPLL VDDPLL VDDRX - I N P T + N P T I I S A B R X T D D V - T U O P T X T S S V + T U O P T * Reserved pin; always leave disconnected. © 2006 Microchip Technology Inc. Preliminary DS39662B-page 1

ENC28J60 Table of Contents 1.0 Overview ...................................................................................................................................................................................... 3 2.0 External Connections ................................................................................................................................................................... 5 3.0 Memory Organization ................................................................................................................................................................. 11 Serial Peripheral Interface (SPI)................................................................................................................................................. 25 4.0 5.0 Ethernet Overview...................................................................................................................................................................... 31 Initialization................................................................................................................................................................................. 33 6.0 7.0 Transmitting and Receiving Packets .......................................................................................................................................... 39 8.0 Receive Filters............................................................................................................................................................................ 47 9.0 Duplex Mode Configuration and Negotiation.............................................................................................................................. 53 10.0 Flow Control ............................................................................................................................................................................... 55 11.0 Reset .......................................................................................................................................................................................... 59 12.0 Interrupts .................................................................................................................................................................................... 63 13.0 Direct Memory Access Controller ............................................................................................................................................... 71 14.0 Power-Down............................................................................................................................................................................... 73 15.0 Built-in Self-Test Controller ........................................................................................................................................................ 75 16.0 Electrical Characteristics ............................................................................................................................................................ 79 17.0 Packaging Information................................................................................................................................................................ 83 Index .................................................................................................................................................................................................... 89 The Microchip Web Site ....................................................................................................................................................................... 91 Customer Change Notification Service ................................................................................................................................................ 91 Customer Support ................................................................................................................................................................................ 91 Reader Response ................................................................................................................................................................................ 92 Product Identification System............................................................................................................................................................... 93 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: Microchip’s Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39662B-page 2 Preliminary © 2006 Microchip Technology Inc.

ENC28J60 The ENC28J60 consists of seven major functional blocks: 1. An SPI interface that serves as a communica- tion channel between the host controller and the ENC28J60. 2. Control Registers which are used to control and monitor the ENC28J60. 3. A dual port RAM buffer for received and transmitted data packets. 4. An arbiter to control the access to the RAM buffer when requests are made from DMA, transmit and receive blocks. 5. The bus interface that interprets data and commands received via the SPI interface. 6. The MAC (Medium Access Control) module that implements IEEE 802.3 compliant MAC logic. 7. The PHY (Physical Layer) module that encodes and decodes the analog data that is present on the twisted pair interface. The device also contains other support blocks, such as the oscillator, on-chip voltage regulator, level translators to provide 5V tolerant I/Os and system control logic. RX RXBM RXF (Filter) DMA & Checksum TX TXBM Flow Control Host Interface MAC MII Interface MIIM Interface LEDA LEDB TPOUT+ TX TPOUT- PHY TPIN+ RX TPIN- RBIAS OSC1 OSC2 OVERVIEW 1.0 The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI). It is designed to serve as an Ethernet network interface for any controller equipped with SPI. The ENC28J60 meets all of the IEEE 802.3 specifica- tions. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hard- ware assisted checksum calculation, which is used in various network protocols. Communication with the host controller is implemented via an interrupt pin and the SPI, with clock rates of up to 20 MHz. Two dedi- cated pins are used for LED link and network activity indication. A simple block diagram of the ENC28J60 is shown in Figure 1-1. A typical application circuit using the device is shown in Figure 1-2. With the ENC28J60, two pulse transformers and a few passive components are all that is required to connect a microcontroller to an Ethernet network. FIGURE 1-1: ENC28J60 BLOCK DIAGRAM Buffer 8 Kbytes Dual Port RAM CLKOUT Control Registers Arbiter ch0 ch1 ch0 ch1 Bus Interface INT CS(1) SI(1) SO SCK(1) SPI System Control Power-on Reset Voltage Regulator 25 MHz Oscillator Note 1: These pins are 5V tolerant. RESET(1) VCAP © 2006 Microchip Technology Inc. Preliminary DS39662B-page 3

ENC28J60 FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE MCU I/O SDO SDI SCK INTX CS SI SO SCK INT ENC28J60 TX/RX Buffer MAC PHY TPIN+/- TPOUT+/- RJ45 ETHERNET TRANSFORMER LEDA LEDB TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, SOIC, SSOP QFN Pin Type Buffer Type Description VCAP VSS CLKOUT INT NC SO SI SCK CS RESET VSSRX TPIN- TPIN+ RBIAS VDDTX TPOUT- TPOUT+ VSSTX VDDRX VDDPLL VSSPLL VSSOSC OSC1 OSC2 VDDOSC LEDB LEDA VDD Legend: Note 1: 2: 3: 4: 5: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P P O O O O I I I I P I I I P O O P P P P P I O P O O P — 2.5V output from internal regulator. A low Equivalent Series Resistance (ESR) capacitor, with a typical value of 10 μF and a minimum value of 1 μF to ground, must be placed on this pin. — Ground reference. — Programmable clock output pin.(1) — INT interrupt output pin.(2) — Reserved function; always leave unconnected. — Data out pin for SPI interface.(2) Data in pin for SPI interface.(3) ST Clock in pin for SPI interface.(3) ST Chip select input pin for SPI interface.(3,4) ST Active-low device Reset input.(3, 4) ST — Ground reference for PHY RX. ANA Differential signal input. ANA Differential signal input. ANA Bias current pin for PHY. Must be tied to ground via a resistor (refer to Section 2.4 “Magnetics, Termination and Other External Components” for details). — Positive supply for PHY TX. — Differential signal output. — Differential signal output. — Ground reference for PHY TX. — Positive 3.3V supply for PHY RX. — Positive 3.3V supply for PHY PLL. — Ground reference for PHY PLL. — Ground reference for oscillator. ANA Oscillator input. — Oscillator output. — Positive 3.3V supply for oscillator. — LEDB driver pin.(5) — LEDA driver pin.(5) — Positive 3.3V supply. I = Input, O = Output, P = Power, DIG = Digital input, ANA = Analog signal input, ST = Schmitt Trigger Pins have a maximum current capacity of 8 mA. Pins have a maximum current capacity of 4 mA. Pins are 5V tolerant. Pins have an internal weak pull-up to VDD. Pins have a maximum current capacity of 12 mA. DS39662B-page 4 Preliminary © 2006 Microchip Technology Inc.

EXTERNAL CONNECTIONS 2.2 Oscillator Start-up Timer ENC28J60 2.0 2.1 Oscillator The ENC28J60 is designed to operate at 25 MHz with a crystal connected to the OSC1 and OSC2 pins. The ENC28J60 design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer specifications. A typical oscillator circuit is shown in Figure 2-1. The ENC28J60 may also be driven by an external clock source connected to the OSC1 pin as shown in Figure 2-2. FIGURE 2-1: CRYSTAL OSCILLATOR OPERATION The ENC28J60 contains an Oscillator Start-up Timer (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire until 7500 OSC1 clock cycles (300 μs) pass after Power-on Reset or wake-up from Power-Down mode occurs. During the delay, all Ethernet registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set ECON1.TXRTS), enable reception of packets (set ECON1.RXEN) or access any MAC, MII or PHY registers during this period. When the OST expires, the CLKRDY bit in the ESTAT register will be set. The application software should poll this bit as necessary to determine when normal device operation can begin. After a Power-on Reset, or the ENC28J60 is removed from Power-Down mode, the CLKRDY bit must be polled before transmitting packets, enabling packet reception or accessing any MAC, MII or PHY registers. ENC28J60 Note: OSC1 XTAL RS(1) OSC2 C1 C2 To Internal Logic RF(2) Note 1: A series resistor, RS, may be required for AT strip cut crystals. 2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ. FIGURE 2-2: EXTERNAL CLOCK SOURCE(1) 3.3V Clock from External System Open(2) ENC28J60 OSC1 OSC2 Note 1: Duty cycle restrictions must be observed. 2: A resistor to ground may be used to reduce system noise. This may increase system current. © 2006 Microchip Technology Inc. Preliminary DS39662B-page 5

ENC28J60 2.3 CLKOUT Pin is selected via The clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler the ECOCON register (Register 2-1). To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting. When the OST expires, the CLKOUT pin will begin out- putting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT func- tion will not be altered (ECOCON will not change FIGURE 2-3: CLKOUT TRANSITION value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low. The CLKOUT function is designed to ensure that mini- mum timings are preserved when the CLKOUT pin function is enabled, disabled or the prescaler value is changed. No high or low pulses will be outputted which exceed the frequency specified by the ECOCON configuration. However, when switching frequencies, a delay between two and eight OSC1 clock periods will occur where no clock pulses will be produced (see Figure 2-3). During this period, CLKOUT will be held low. ECOCON Changed 80 ns to 320 ns Delay REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER U-0 — bit 7 Legend: R = Readable bit -n = Value at POR U-0 — U-0 — U-0 — U-0 — R/W-1 R/W-0 R/W-0 COCON2 COCON1 COCON0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 bit 2-0 Unimplemented: Read as ‘0’ COCON2:COCON0: Clock Output Configuration bits 11x = Reserved for factory test. Do not use. Glitch prevention not assured. 101 = CLKOUT outputs main clock divided by 8 (3.125 MHz) 100 = CLKOUT outputs main clock divided by 4 (6.25 MHz) 011 = CLKOUT outputs main clock divided by 3 (8.333333 MHz) 010 = CLKOUT outputs main clock divided by 2 (12.5 MHz) 001 = CLKOUT outputs main clock divided by 1 (25 MHz) 000 = CLKOUT is disabled. The pin is driven low. DS39662B-page 6 Preliminary © 2006 Microchip Technology Inc.

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