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Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) • Internally Organized 512 x 8 (4K), or 1024 x 8 (8K) • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility • Write Protect Pin for Hardware Data Protection • 16-byte Page (4K, 8K) Write Modes • Partial Page Writes Allowed • Self-timed Write Cycle (5 ms max) • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages • Lead-free/Halogen-free • Die Sales: Wafer Form, Tape and Reel and Bumped Wafers Description The AT24C04B/08B provides 4096/8192 bits of serial electrically erasable and pro- grammable read-only memory (EEPROM) organized as 512/1024 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C04B/08B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini- MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the AT24C04B/08B is available in 1.8V (1.8V to 5.5V) version. Table 0-1. Pin Configuration Function Pin Name Address Inputs A0 - A2 SDA Serial Data Serial Clock Input SCL Write Protect WP NC No Connect Ground GND VCC Power Supply 8-ball dBGA2 A0 A1 A2 GND Mini-MAP (MLP 2x3) 8-lead Ultra-Thin A0 A1 A2 GND 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA VCC WP SCL SDA VCC WP SCL SDA 8 7 6 5 A0 A1 A2 GND Bottom View 8-lead SOIC 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5 1 2 3 4 Bottom View Two-wire Serial EEPROM 4K (512 x 8) 8K (1024 x 8) AT24C04B AT24C08B Preliminary VCC WP SCL SDA For use of 5-lead SOT23 Note: 4K: The software A2 and A1 bits in the device address word must be set to zero to properly communicate. 8K: The software A2 bit in the device address word must be set to zero to properly communicate. 5-lead SOT23 8-lead PDIP SCL GND SDA 1 2 3 5 4 WP VCC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 5226C–SEEPR–2/08

Absolute Maximum Ratings Operating Temperature..................................–55°C to +125°C *NOTICE: Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground ....................................–1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 0-1. Block Diagram Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCC GND WP SCL SDA A2 A1 A0 START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING COMP DATA RECOVERY LOAD INC R/W DATA WORD ADDR/COUNTER C E D X EEPROM Y DEC SERIAL MUX DOUT/ACK LOGIC DIN DOUT 2 AT24C04B/08B 5226C–SEEPR–2/08

1. Pin Description AT24C04B/08B SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open- drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The AT24C04B uses the A2 and A1 inputs for hard wire addressing and a toal of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground (device addressing is discussed in detail under the Device Addressing section). The AT24C08B only uses the A2 input for hardware addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground (device addressing is discussed in detail under the Device Addressing section). Table 1-1. WP Pin Status At VCC At GND Write Protect Part of the Array Protected 24C04B/08B Full Array Normal Read/Write Operations 5226C–SEEPR–2/08 3

2. Memory Organization AT24C04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires an 9-bit data word address for random word addressing. AT24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. Pin Capacitance(1) Table 2-1. Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V DC Characteristics Test Condition Typ Units Table 2-2. Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted) Symbol VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS Max 5.5 5.5 5.5 5.5 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 V V V V mA mA µA µA µA µA µA µA V V V V 1. VIL min and VIH max are reference only and are not tested. 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 VCC x 0.3 VCC + 0.5 0.4 0.2 IOL = 2.1 mA IOL = 0.15 mA Min 1.8 2.5 2.7 4.5 –0.6 VCC x 0.7 4 AT24C04B/08B 5226C–SEEPR–2/08

AT24C04B/08B AC Characteristics Table 2-3. Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time(1) Inputs Fall Time(1) Stop Setup Time Data Out Hold Time Write Cycle Time Endurance(1) 5.0V, 25°C, Byte Mode Note: 1. This parameter is ensured by characterization only. 1.8, 2.5, 2.7 Min Max 400 1.2 0.6 0.1 1.2 0.6 0.6 0 100 0.6 50 1M 50 0.9 0.3 300 5 5.0-volt Min 0.4 0.4 0.05 0.5 0.25 0.25 0 100 .25 50 1M Max 1000 40 0.55 0.3 100 5 Units kHz µs µs ns µs µs µs µs µs ns µs ns µs ns ms Write Cycles 5226C–SEEPR–2/08 5

3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig- ure 5-3 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by a stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Start bit Dummy Clock Cycles Start bit Stop bit 1 2 3 8 9 SCL SDA 6 AT24C04B/08B 5226C–SEEPR–2/08

4. Bus Timing Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O® tHIGH tF AT24C04B/08B tR tLOW tLOW tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO tAA tDH tBUF SCL SDA IN SDA OUT 5. Write Cycle Timing Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5226C–SEEPR–2/08 7

Figure 5-2. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Figure 5-3. Start and Stop Definition SDA SCL Figure 5-4. Output Acknowledge START STOP SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 8 AT24C04B/08B 5226C–SEEPR–2/08

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