CAT24C23(CAT24C23).pdf

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CAT24C32

32-Kb I2C CMOS Serial EEPROM

Features

Device Description

Pin Configuration

Functional Symbol

Pin Functions

Absolute Maximum Ratings

Reliability Characteristics

D.C. Operating Characteristics

Pin Impedance Characteristics

A.C. Characteristics

A.C. Test Conditions

Power-On Reset (POR)

Pin Description

Functional Description

I2C Bus Protocol

START/STOP Condition

Figure 1. Start/Stop Timing

Device Addressing

Figure 2. Slave Address Bits

Acknowledge

Figure 3. Acknowledge Timing

Figure 4. Bus Timing

Write Operations

Byte Write

Figure 5. Byte Write Sequence

Figure 6. Write Cycle Timing

Page Write

Figure 7. Page Write Sequence

Acknowledge Polling

Hardware Write Protection

Figure 8. WP Timing

Delivery State

Read Operations

Immediate Read

Figure 9. Immediate Read Sequence and Timing

Selective Read

Figure 10. Selective Read Sequence

Sequential Read

Figure 11. Sequential Read Sequence

Package Drawings

8-Lead 300 MIL Wide Plastic DIP (L)

8-Lead 150 MIL Wide SOIC (W)

8-Lead TSSOP (Y)

8-Pad TDFN 3X4.9 Package (ZD2)

8-Lead TDFN 2x3 (VP2)

Example of Ordering Information

Revision History

CAT24C32 32-Kb I2C CMOS Serial EEPROM FEATURES ■ Supports Standard and Fast I2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 32-Byte Page Write Buffer ■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and TDFN packages DEVICE DESCRIPTION The CAT24C32 is a 32-Kb CMOS Serial EEPROM devices, internally organized as 128 pages of 32 bytes each. It features a 32-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. External address pins make it possible to address up to eight CAT24C32 devices on the same bus. For Ordering Information details, see page 15. PIN CONFIGURATION FUNCTIONAL SYMBOL PDIP (L) SOIC (W) TSSOP (Y) TDFN (ZD2, VP2) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA VCC SCL A2, A1, A0 CAT24C32 SDA For the location of Pin 1, please consult the corresponding package drawing. WP PIN FUNCTIONS A0, A1, A2 SDA SCL WP VCC VSS Device Address Serial Data Serial Clock Write Protect Power Supply Ground VSS * The Green & Gold seal identiﬁ es RoHS-compliant packaging, using NiPdAu pre-plated lead frames. © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1101, Rev. G

CAT24C32 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol Parameter (4) Endurance NEND TDR Data Retention -65°C to +150°C -0.5 V to +6.5 V Min 1,000,000 100 Units Program/ Erase Cycles Years D.C. OPERATING CHARACTERISTICS = 1.8 V to 5.5 V, T = -40°C to 85°C, unless otherwise speciﬁ ed. = 1.8 V to 5.5 V, TA VCC = 1.8 V to 5.5 V, TA A = -40°C to 85°C, unless otherwise speciﬁ ed. A Symbol Parameter Test Conditions Min Max Units Read Current ICCR ICCW Write Current ISB IL I/O Pin Leakage Standby Current VIL VIH VOL1 VOL2 Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Read, fSCL = 400 kHz SCL = 400 kHz SCL Write, fSCL = 400 kHz SCL = 400 kHz SCL All I/O Pins at GND or VCC Pin at GND or VCC 1 1 1 1 -0.5 VCC x 0.3 VCC x 0.7 VCC + 0.5 VCC ≥ 2.5 V, IOL = 3.0 mA OL = 3.0 mA OL VCC < 2.5 V, IOL = 1.0 mA OL = 1.0 mA OL 0.4 0.2 mA mA μA μA V V V V PIN IMPEDANCE CHARACTERISTICS = 1.8 V to 5.5 V, T = -40°C to 85°C, unless otherwise speciﬁ ed. = 1.8 V to 5.5 V, TA VCC = 1.8 V to 5.5 V, TA A = -40°C to 85°C, unless otherwise speciﬁ ed. A Symbol Parameter (3) (3) CIN CIN IWP SDA I/O Pin Capacitance Input Capacitance (other pins) (5) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH VIN > VIH Max Units 8 6 100 1 pF pF μA Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speciﬁ cation is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. Doc. No. 1101, Rev. G 2 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

A.C. CHARACTERISTICS(1) = 1.8 V to 5.5 V, T = -40°C to 85°C. = 1.8 V to 5.5 V, TA VCC = 1.8 V to 5.5 V, TA A = -40°C to 85°C. A Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (2) tF tSU:STO tBUF tAA tDH (2) Ti tSU:WP tHD:WP tWR (2, 3) tPU Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode CAT24C32 Max 400 Units kHz μs μs μs μs μs ns ns ns μs μs μs ns ns μs μs ms ms 300 300 0.9 100 5 1 Standard Fast Min 0.6 1.3 0.6 0.6 0 100 0.6 1.3 100 0 2.5 Min 4 4.7 4 4.7 0 250 4 4.7 100 0 2.5 Max 100 1000 300 3.5 100 5 1 Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS 0.2 x VCC to 0.8 x VCC Input Levels Input Rise and Fall Times ≤ 50 ns Input Reference Levels Output Reference Levels Output Load 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (V OL = 3 mA (V OL CC ≥ 2.5 V); IOL = 1 mA (V OL = 1 mA (V OL CC < 2.5 V); CL = 100 pF L = 100 pF L © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1101, Rev. G

CAT24C32 POWER-ON RESET (POR) FUNCTIONAL DESCRIPTION Each CAT24C32 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device ad- dress that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left ﬂ oating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left ﬂ oating, this pin is pulled LOW internally. The CAT24C32 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus trafﬁ c, and Slave devices which execute requests. The CAT24C32 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAT24C32, the ﬁ rst four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/W pins. The R/W pins. The R/ bit tells the Slave whether the Master W bit tells the Slave whether the Master W intends to read (1) or write (0) data (Figure 2). Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allow- ing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4. Doc. No. 1101, Rev. G 4 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

CAT24C32 Figure 1. Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER) 1 8 9 SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4. Bus Timing SCL tSU:STA SDA IN SDA OUT tF tHIGH tR tLOW tLOW tHD:DAT tHD:STA tSU:DAT tAA tDH tSU:STO tBUF © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1101, Rev. G

CAT24C32 WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave ad- dress with the R/W dress with the R/W dress with the R/ bit set to ‘0’. The Master then sends W bit set to ‘0’. The Master then sends W two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowl- edge the Master (Figure 6). Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Acknowledge Polling As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum speciﬁ ed Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply re- peats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left ﬂ oating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C32 is shipped erased, i.e., all bytes are FFh. Doc. No. 1101, Rev. G 6 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

CAT24C32 Figure 5. Byte Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE SLAVE ADDRESS ADDRESS BYTE a15 ÷ a8 * * ** DATA BYTE a7 ÷ a0 DATA BYTE d7 ÷ d0 A C K A C K A C K S T O P P A C K * a15 ÷ a12 are don't care bits. Figure 6. Write Cycle Timing SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Page Write Sequence SLAVE ADDRESS ADDRESS BYTE ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+P A C K A C K A C K A C K A C K S T O P P A C K BUS ACTIVITY: MASTER S T A R T S SLAVE n = 1 P ≤ 31 Figure 8. WP Timing SCL A C K 1 ADDRESS BYTE DATA BYTE 8 9 1 8 d0 SDA a7 a0 d7 tSU:WP WP tHD:WP © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1101, Rev. G

CAT24C32 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave ad- dress with the R/W dress with the R/W dress with the R/ bit set to ‘1’. The Slave responds with W bit set to ‘1’. The Slave responds with W ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a speciﬁ c address, the selected address must ﬁ rst be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W broadcasts a Slave address with the R/W broadcasts a Slave address with the R/ bit set to ‘1’. W bit set to ‘1’. W The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmit- ting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. Doc. No. 1101, Rev. G 8 © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

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