EDA技术与VHDL答案.pdf-资料库

第 3 章 VHDL 基础习题 3-1 如图所示 3-2 程序： IF_THEN 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 S PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1= ELSIF s1= ELSIF s1= ELSIF s1= ELSE y<=NULL ; END IF ; END PROCESS ; END ARCHITECTURE one ; ’0’ AND s0=’0’ THEN y<=a ; ’0’ AND s0=’1’ THEN y<=b ; ’1’ AND s0=’0’ THEN y<=c ; ’1’ AND s0=’1’ THEN y<=d ;

CASE 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE two OF mux21 IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s<=s1 & s0 ; PROCESS ( s ) BEGIN CASE s IS WHEN WHEN “00” => y<=a ; “01” => y<=b ; WHEN “10” => y<=c ; WHEN “11” => y<=d ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ARCHITECTURE two ; 3-3 程序： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MUXK IS PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ; ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; -- 内部连接线 BEGIN

’0’ THEN u1_y<= u1_a ; p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; BEGIN IF u1_s= ELSIF u1_y<= u1_b ; ELSE u1_y<= NULL ; END IF ; END PROCESS p_ MUX21A_u1 ; p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ; BEGIN IF u2_s= ELSIF u2_y<= u2_b ; ELSE u2_y<= NULL ; END IF ; END PROCESS p_ MUX21A_u2 ; u1_s<= s0 ; u1_a<= a2 ; u1_b<= a3 ; tmp<= u1_y ; u2_s<=s1 ; u2_a<= a1 ; u2_b<= tmp; outy <= u2_y ; END ARCHITECTURE double ; ’0’ THEN u2_y<= u2_a ; 3-4 程序：（1）1 位半减器

1 位半减器的设计选用（2）图，两种表达方式：一、 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber IS BEGIN diff<=x XOR y ; s_out<= ( NOT a ) AND b ; END ARCHITECTURE fhd1 ; 二、 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s<= x & y ; PROCESS ( s )

BEGIN CASE s IS WHEN WHEN “00” => s_out <=’0’ ; diff<=’0’ ; “01” => s_out <=’1’ ; diff<=’1’ ; WHEN “10” => s_out <=’0’ ; diff<=’1’ ; WHEN “11” => s_out <=’0’ ; diff<=’0’ ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ARCHITECTURE fhd1 ; 或门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY or IS PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY or ; ARCHITECTURE one OF or IS BEGIN c<= a OR b ; END ARCHITECTURE one ; 1 位全减器： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END ENTITY f_suber ; ARCHITECTURE fhd1 OF f_suber IS COMPONENT h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END COMPONENT h_suber ; COMPONENT or IS

PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT or ; SIGNAL d,e,f : STD_LOGIC ; BEGIN u1 : h_suber PORT MAP ( x=>x, y=>y, diff=>d, s_out=>e ) ; u2 : h_suber PORT MAP ( x=>d, y=>sub_in, diff=>diffr, s_out=>f ) ; u3 : or PORT MAP ( a=>f, b=>e, c=>sub_out ) ; END ARCHITECTURE fhd1 ; （2）8 位减法器： x0 y0 x1 y1 x2 y2 x3 y3 sub_in x y sub_in x y sub_in x y sub_in x y a f_suber sub_out u0 f_suber sub_out u1 diffr0 diffr1 b d c f_suber sub_out u2 f_suber sub_out u3 diffr2 diffr3 x4 y4 x5 y5 x6 y6 x7 y7 sub_in x y sub_in x y sub_in x y sub_in x y e f_suber sub_out u4 f f_suber sub_out u5 g f_suber sub_out u6 f_suber sub_out u7 diffr4 diffr5 diffr6 diffr7 sub_out LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY 8f_suber IS PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ; y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ; sub_in : IN STD_LOGIC ; sub_out : OUT STD_LOGIC ; diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ; diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ; END ENTITY 8f_suber ;

ARCHITECTURE 8fhd1 OF 8f_suber IS COMPONENT f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END COMPONENT f_suber ; SIGNAL a,b,c,d,e,f,g : STD_LOGIC ; BEGIN u0 : f_suber PORT MAP ( x=>x0, y=>y0, sub_in=>, sub_out=>a, diff=>diff0 ) ; u1 : f_suber PORT MAP ( x=>x1, y=>y1, sub_in=>a, sub_out=>b, diff=>diff1 ) ; u2 : f_suber PORT MAP (x=>x2, y=>y2, sub_in=>b, sub_out=>c, diff=>diff2 ) ; u3 : f_suber PORT MAP (x=>x3, y=>y3, sub_in=>c, sub_out=>d, diff=>diff3 ) ; u4 : f_suber PORT MAP (x=>x4, y=>y4, sub_in=>d, sub_out=>e, diff=>diff4 ) ; u5 : f_suber PORT MAP (x=>x5, y=>y5, sub_in=>e, sub_out=>f, diff=>diff5 ) ; u6 : f_suber PORT MAP (x=>x6, y=>y6, sub_in=>f, sub_out=>g, diff=>diff6 ) ; u7 : f_suber PORT MAP (x=>x7, y=>y7, sub_in=>g, sub_out=> sub_out, diff=>diff7 ) ; END ARCHITECTURE 8fhd1 ; 3-5 程序：或非门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nor IS PORT ( d,e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END ENTITY nor ; ARCHITECTURE one OF nor IS BEGIN

f <= NOT ( d OR e ) ; END ARCHITECTURE one ; 时序电路描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY circuit IS PORT ( CL, CLK0 : IN STD_LOGIC ; OUT1 : OUT STD_LOGIC ) ; END ENTITY circuit ; ARCHITECTURE one OF circuit IS COMPONENT DFF1 IS PORT ( CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END COMPONENT DFF1 ; COMPONENT nor IS PORT ( d,e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT nor ; COMPONENT not IS PORT ( g : IN STD_LOGIC ; h : OUT STD_LOGIC ) ; END COMPONENT not ; SIGNAL a,b,c : STD_LOGIC ; BEGIN u0 : nor PORT MAP ( d=>c, e=>CL, f=>a ) ; u1 : DFF1 PORT MAP ( CLK=>CLK0, D=>a, Q=>b ) ; u2 : not PORT MAP ( g=>b, g=>c, h=>OUT1 ) ; END ARCHITECTURE one ; 3-6 3-7 3-8 3-9

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