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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 04

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation 74HC/HCT595 FEATURES • 8-bit serial input • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear • 100 MHz (typ) shift out frequency • Output capability: – parallel outputs; bus driver – serial output; standard • ICC category: MSI. APPLICATIONS • Serial-to-parallel data conversion • Remote control holding register. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. DESCRIPTION The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. SYMBOL PARAMETER CONDITIONS tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V SHCP to Q7’ STCP to Qn MR to Q7’ fmax CI CPD maximum clock frequency SHCP, STCP input capacitance power dissipation capacitance per package notes 1 and 2 TYP. HC HCT 16 17 14 100 3.5 115 21 20 19 57 3.5 130 UNIT ns ns ns MHz pF pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in m W): 2 · PD = CPD · VCC fi + (CL · VCC 2 · fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL · VCC fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2 · 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V. 1998 Jun 04 2

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state ORDERING INFORMATION Product speciﬁcation 74HC/HCT595 TYPE NUMBER 74HC595N 74HC595D 74HC595DB 74HC595PW 74HCT595N 74HCT595D PACKAGE NAME DIP16 SO16 SSOP16 TSSOP16 DIP16 SO16 DESCRIPTION VERSION SOT38-1 plastic dual in-line package; 16 leads (300 mil); long body SOT109-1 plastic small outline package; 16 leads; body width 3.9 mm SOT338-1 plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SOT38-1 plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PINNING Q0 to Q7 GND Q7’ MR SHCP STCP OE DS VCC handbook, halfpage SYMBOL PIN 15, 1 to 7 8 9 10 11 12 13 14 16 DESCRIPTION parallel data output ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable (active LOW) serial data input positive supply voltage Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8 16 VCC 15 14 Q0 DS 13 OE 12 STCP 11 SHCP 10 MR 9 Q7' 595 MLA001 handbook, halfpage 11 SHCP 14 DS 12 STCP Q7' Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 MR OE 10 13 MLA002 Fig.1 Pin configuration. Fig.2 Logic symbol. 1998 Jun 04 3

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation 74HC/HCT595 handbook, full pagewidth handbook, halfpage OE STCP MR SHCP DS 13 12 10 11 14 EN3 C2 SRG8 C1/ R 1D 2D 3 MSA698 Fig.3 IEC logic symbol. 14 11 10 DS SHCP MR 8-STAGE SHIFT REGISTER 12 STCP 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS 15 1 2 3 4 5 6 7 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' Q7' 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 MLA003 Fig.4 Functional diagram. 1998 Jun 04 4

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation 74HC/HCT595 handbook, full pagewidth STAGE 0 STAGES 1 TO 6 STAGE 7 D Q FF0 CP R D Q LATCH CP DS SHCP MR STCP OE D Q Q7' D Q FF7 CP R D Q LATCH CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MLA010 Fig.5 Logic diagram. 1998 Jun 04 5

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state FUNCTION TABLE INPUTS OUTPUTS Q7’ L L L Q6’ SHCP STCP X X X X X X X OE L L H L L L MR L L L H H H DS X X X H X X Product speciﬁcation 74HC/HCT595 FUNCTON QN NC a LOW level on MR only affects the shift registers L Z empty shift register loaded into storage register shift register clear. Parallel outputs in high-impedance OFF-state NC logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages contents of shift register shifted through. Previous contents of the shift register is transferred to the storage register and the parallel output stages. NC Qn’ Q6’ Qn’ Notes 1. H = HIGH voltage level; L = LOW voltage level › = LOW-to-HIGH transition; ﬂ = HIGH-to-LOW transition Z = high-impedance OFF-state; NC = no change X = don’t care. 1998 Jun 04 6 › › › › ›

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation 74HC/HCT595 handbook, full pagewidth SHCP DS STCP MR OE Q0 Q1 Q6 Q7 Q7' Fig.6 Timing diagram. 1998 Jun 04 7 high-impedance OFF-state MLA005 - 1

Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation 74HC/HCT595 DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb ( C) - 40 to +85 SYMBOL PARAMETER tPHL/tPLH propagation delay SHCP to Q7’ tPHL/tPLH propagation delay STCP to Qn tPHL propagation delay MR to Q7’ tPZH/tPZL tPHZ/tPLZ tW tW tW tsu tsu 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW set-up time DS to SHCP set-up time SHCP to STCP min 75 15 13 75 15 13 75 15 13 50 10 9.0 75 15 13 1998 Jun 04 8 240 48 41 265 53 45 265 53 45 225 45 38 225 45 38 200 40 34 220 44 37 220 44 37 190 38 33 190 38 33 160 32 27 175 35 30 175 35 30 150 30 26 150 30 26 - 40 to +125 +25 typ max min max min max 52 19 15 55 20 16 47 17 14 47 17 14 41 15 12 17 6 5 11 4 3 17 6.0 5.0 11 4.0 3.0 22 8 7 95 19 16 95 19 16 95 19 16 65 13 11 95 19 16 110 22 19 110 22 19 110 22 19 75 15 13 110 22 19 TEST CONDITION UNIT VCC (V) WAVEFORMS ns ns ns ns ns ns ns ns ns ns Fig.7 Fig.8 Fig.10 Fig.11 Fig.11 Fig.7 Fig.8 Fig.10 Fig.9 Fig.8 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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