0.1 Reference Documents
Chapter 1 General Description
Figure 1.1 Basic ULPI USB Device Block Diagram
Figure 1.2 ULPI Interface Features as Related to UTMI+
Chapter 2 Functional Overview
Figure 2.1 USB3300 Block Diagram
Chapter 3 Pin Layout
3.1 USB3300 Pin Diagram
Figure 3.1 USB3300 Pin Diagram - Top View
3.2 Pin Function
Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package
Chapter 4 Operational Description
Table 4.1 Maximum Guaranteed Ratings
Table 4.2 Recommended Operating Conditions
Chapter 5 Electrical Characteristics
Table 5.1 Electrical Characteristics: Supply Pins
Table 5.2 Electrical Characteristics: CLKOUT Start-Up
Table 5.3 DC Electrical Characteristics: Logic Pins
Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM)
Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM)
Table 5.6 OTG Electrical Characteristics
Table 5.7 Regulator Output Voltages
Chapter 6 Architecture Overview
Figure 6.1 Simplified USB3300 Architecture
6.1 ULPI Digital
6.1.1 Overview
Figure 6.2 ULPI Digital Block Diagram
6.1.2 ULPI Interface Signals
Table 6.1 ULPI Interface Signals
6.1.3 ULPI Interface Timing
Figure 6.3 ULPI Timing Diagram
Table 6.2 ULPI Interface Timing
6.1.4 ULPI Register Array
Table 6.3 ULPI Register Map
6.1.5 ULPI Register Access
Table 6.4 ULPI TXD CMD Byte Encoding
Figure 6.4 ULPI Register Write
Figure 6.5 ULPI Register Read
6.1.6 ULPI RXD CMD
Table 6.5 ULPI RX CMD Encoding
6.1.7 USB3300 Transmitter
Figure 6.6 ULPI Transmit
6.1.8 USB3300 Receiver
Figure 6.7 ULPI Receive
6.1.9 Low Power Mode
Figure 6.8 Entering Low Power Mode
Table 6.6 Interface Signal Mapping During Low Power Mode
Figure 6.9 Exiting Low Power Mode
6.1.10 Full Speed/Low Speed Serial Modes
Table 6.7 Pin Definitions in 3 pin Serial Mode
6.1.11 Reset Pin
6.2 Hi-Speed USB Transceiver
6.2.1 High Speed and Full Speed Transceivers
6.2.2 Termination Resistors
Table 6.8 DP/DM termination vs. Signaling Mode
6.2.3 Bias Generator
6.3 Crystal Oscillator and PLL
6.4 Internal Regulators and POR
6.4.1 Internal Regulators
6.4.2 Power On Reset (POR)
6.5 USB On-The-Go (OTG) Module
Figure 6.10 USB3300 On-the-Go Module
6.5.1 ID Detection
Table 6.9 IdGnd vs. USB Cable Type
6.5.2 VBUS Control
6.5.3 Driving External Vbus
6.5.4 External Vbus Indicator
Table 6.10 External Vbus Indicator Logic
Chapter 7 Application Notes
Table 7.1 Component Values in Application Diagrams
Table 7.2 Capacitance Values at VBUS of USB Connector
7.1 Application Diagrams
Figure 7.1 USB3300 Application Diagram (Peripheral)
Figure 7.2 USB3300 Application Diagram (Host or OTG)
Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection)
7.2 Multi-port Applications
Figure 7.4 Expanding Downstream Ports for USB3300 Host Applications
7.3 Evaluation Board
7.4 ESD Performance
7.4.1 Human Body Model (HBM) Performance
7.4.2 IEC61000-4-2 Performance
Chapter 8 Package Outline
Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)
Table 8.1 32 Terminal QFN Package Parameters
Figure 8.1 QFN, 5x5 Taping Dimensions and Part Orientation
Figure 8.2 Reel Dimensions for 12mm Carrier Tape
Figure 8.3 Tape Length and Part Quantity