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ncverilog 手册.pdf
Contents
Overview of the NC-Verilog Simulator
Native Compiled Code
The Interleaved Native Compiled Code (INCA) Architecture
Language Support
Memory Requirements
Setting Up Your Design Environment
Environment Setup Files
PATH and Library Path Environment Variables
Running the NC-Verilog Simulator
Single-Step Invocation With ncverilog
Multi-Step Invocation (Library-Based Mode)
64-Bit NC-Verilog
Platform Support
Licensing
Running the 64-Bit Version
Libraries and Snapshots
PLI Applications
Functional Differences Between 32-bit and 64 bit
Simulator Library Databases
Simulating Large Designs
Getting Help
About Online Help
Invoking the Documentation System
Printing Documents
Searching Documents
Getting Help on Commands to Run Tools
Getting Help on Simulator Commands
Getting Help on Tool Messages
Return Codes for Error Conditions
Related Manuals
Other Documentation
Using NCLaunch
Running NC-Verilog with the ncverilog Command
Overview
How ncverilog Works
ncverilog Command Syntax
ncverilog Command Options
Plus Options for NC-Verilog Tools
Verilog-XL Command-Line Options Translation
Verilog-XL Dash (-) Option Translation Table
Verilog-XL Plus (+) Option Translation Table
Example ncverilog Run
Mapping of Warning Messages
Updating Design Changes
Using +ncuid+ to Run in Regression Mode
Using -R and -r to Simulate a Snapshot
Using -R to Simulate a Snapshot Multiple Times
Using -r to Simulate a Saved Snapshot
PLI Tasks
SDF Annotation
Using $test$plusargs to Selectively Perform Annotations
Specifying Precision
Turning Off SDF Annotation
Controlling SDF Annotator Output
Troubleshooting
Modeling Your Hardware
Arrays of Instances
Instance Array Names
Array Range Expressions
Port Connections
Ports of Instance Arrays
Differing Instances in an Array
Hierarchical References
NC-Verilog Restrictions to the IEEE Standard
Arrays of Instances and Tcl Commands
Randomization and Constraints Extensions
Verilog IEEE Std 1364-2001 Enhancements
Comma-Separated Sensitivity List
Combinational Logic Sensitivity Token
Variable Declaration with Initial Value Assignment
Combined Port and Data Type Declarations
Input and Output Declarations
Signed Arithmetic Extensions
Re-Entrant Tasks and Recursive Functions
File I/O Enhancements
PLA System Task Extensions
‘ifndef and ‘elsif Conditional Compilation Compiler Directives
Parameter Value Assignment by Name
$value$plusargs System Function
Disabling Implicit Net Declarations
Indexed Vector Part-Selects
Power Operator
Local Parameters
Implicit Nets with Continuous Assignments
Automatic Width Extension of X and Z Constants beyond 32 Bits
Line and File Compiler Directive
Attributes
Generate Constructs
Multi-Dimensional Arrays and Arrays of Net Data Types
Bit-Selects and Part-Selects within Arrays
Verilog Configurations
Sized and Typed Parameters
SystemVerilog Enhancements
Loading Stimulus from an ASCII File
Syntax
Arguments
Data File Format
$loadStimFileX Example
$loadStrobeFileX/$strobeStimX Example
Loading Scan Chain Elements
repeat Loop Expression Value
Setting Up Your Environment
Overview
The Library.Cell:View Approach
The cds.lib File
The Work Library
cds.lib Statements
cds.lib Syntax Rules
Example cds.lib File
Binding One Library to Multiple Directories
Debugging cds.lib Files
The hdl.var File
hdl.var Statements
hdl.var Variables
hdl.var Syntax Rules
Example hdl.var File
Debugging hdl.var Files
The setup.loc File
setup.loc Syntax Rules
Directory Structure Example
Compiling Verilog Source Files with ncvlog
Overview
ncvlog Command Syntax
ncvlog Command Options
Example ncvlog Command Lines
hdl.var Variables
Conditionally Compiling Source Code
Controlling the Compilation of Design Units into Library.Cell:View
Compiling without Setup Files
The LIB_MAP and VIEW_MAP Variables
The -libmap Command-Line Option
The WORK and VIEW Variables
The -work and -view Command-Line Options
The -specificunit Command-Line Option
The `worklib and `view Compiler Directives
Mapping of Modules Defined within `include Files
cds.lib Files that Map Multiple Logical Names to the Same Physical Directory
Defining Macros on the Command Line
Elaborating the Design with ncelab
Overview
ncelab Command Syntax
General Options
VHDL Only Options
Verilog Only Options
AMS Options
NC-SC Options
ncelab Command Options
Example ncelab Command Lines
hdl.var Variables
How Modules and UDPs Are Resolved during Elaboration
The Default Binding Mechanism
Default Configuration Using a Library Map File
The -binding Option
The `uselib Compiler Directive
Using a Verilog Configuration
Enabling Read, Write, or Connectivity Access to Simulation Objects
Regression Mode and Tcl Commands
Regression Mode and PLI/VPI/VHPI Applications
Regression Mode and the SimVision Debug Environment
Using -access to Specify Read/Write/Connectivity Access
Using -afile to Include an Access File
Generating an Access File
Guidelines for Access Control
Disabling Timing in Selected Portions of a Design
Selecting a Delay Mode
Delay Modes
Reasons to Select a Delay Mode
Setting a Delay Mode
Timescales and Simulation Time Units
Overriding Delay Values
Delay Mode Example
Decompiling with Delay Modes
Macro Module Expansion and Delay Modes
Summary of Delay Mode Rules
Setting Pulse Controls
Overview
Global Pulse Control
Pulse Control for Specific Modules and Module Paths
Pulse Filtering Style
Simulating Your Design with ncsim
Overview
ncsim Command Syntax
General Options
Verilog Only Options
VHDL Only Options
AMS Options
NC-SC Options
ncsim Command Options
Example ncsim Command Lines
hdl.var Variables
Invoking the Simulator
Invoking the Simulator in Noninteractive Mode
Invoking the Simulator in Interactive Mode
Starting a Simulation
Saving, Restarting, Resetting, and Reinvoking a Simulation
Saving and Restarting the Simulation
Resetting the Simulation
Reinvoking a Simulation
Updating Design Changes When You Invoke the Simulator
Providing Interactive Commands from a File
-input Command Syntax
Exiting the Simulation
Mixed Verilog/VHDL Simulation
Mapping of Data Types
Restrictions and Limitations on Mixed-Language Simulation
Importing Verilog into VHDL
Using Default Binding
Using a Configuration Specification or Configuration Declaration
Using Direct Instantiation
Using a Shell
Importing VHDL into Verilog
Importing VHDL into Verilog without a Shell
Importing VHDL into Verilog with a Shell
Importing a VHDL Design Unit with Multiple Architectures
Importing VHDL into Verilog with ncverilog
A Verilog-VHDL-Verilog Example
Preparing the Design without Shells
Preparing the Design with Shells
Generating a Shell with ncshell
ncshell Command Syntax
ncshell Command Options
Configuring a Mixed-Language Design with a VHDL Configuration Declaration
Search Order for Binding Design Units
Example 1: Verilog Instantiating VHDL
Example 2: VHDL Instantiating Verilog
Example 3: VHDL Instantiating Verilog that Instantiates VHDL
Example 4: VHDL Instantiating Verilog that Instantiates Verilog (Using a Verilog Configuration)
Importing a Verilog-XL Design into VHDL
Mixed-Language Networks and Signal Resolution
Mixed-Language Out-of-Module References
Path Names and Mixed-Language Designs
SDF Annotation for Mixed-Language Designs
Generating a Value Change Dump (VCD) File for a Mixed-Language Design
Generating an Extended Value Change Dump (EVCD) File for a Mixed-Language Design
Opening an EVCD Database
Probing Ports to the Database
Examples
Port Value Character Mapping
Strength Mapping
Mixed-Language Simulation Enhancements in LDV 4.1
LDV 4.1 Enhancements
Behavioral Differences
Debugging Your Design
Managing Databases
Creating a Database
Setting a Database As the Default
Displaying Information About Databases
Disabling a Database
Enabling a Database
Creating Incremental SHM Database Files
Closing a Database
Setting and Deleting Probes
Setting a Probe
Displaying Information About Probes
Disabling a Probe
Enabling a Probe
Deleting a Probe
Traversing the Model Hierarchy
Path Names
Setting the Debug Scope
Setting Breakpoints
Setting a Condition Breakpoint
Setting a Source Code Line Breakpoint
Setting an Object Breakpoint
Setting a Time Breakpoint
Setting a Delta Breakpoint
Setting a Process Breakpoint
Setting a Subprogram Breakpoint
Disabling, Enabling, Deleting, and Displaying Breakpoints
Stepping Through Lines of Code
Forcing and Releasing Signal Values
Depositing Values to Signals
Displaying Information About Simulation Objects
Displaying the Drivers of Signals
Checking for Bus Contention and Bus Float Conditions
Detecting Infinite Loops
Displaying Waveforms with the SimVision Waveform Viewer
Creating an SHM Database and Probing Signals
Opening a Database with $shm_open
Probing Signals with $shm_probe
Invoking SimVision
Using $recordvars and Related Tasks
Generating a Value Change Dump (VCD) File
Generating a VCD File with Tcl Commands
Generating a VCD File with VCD System Tasks
Syntax and Format of the VCD File
Generating an Extended Value Change Dump (EVCD) File
Generating an EVCD File with Tcl Commands
Examples
Generating an EVCD File with the $dumpports System Task
Using the $dumpports_close System Task
Using the format_flag Argument to Control $dumpports Output
$dumpports Restrictions
Syntax and Format of the EVCD File
Comparing Databases with Comparescan
Code Coverage with Incisive Comprehensive Coverage
Displaying Debug Settings
Setting a Default Radix
Setting Variables
Suppressing Assert Messages in IEEE or User-Defined Packages
Editing a Source File
Searching for a Line Number in the Source Code
Searching for a Text String in the Source Code
Configuring Your Simulation Environment
Saving and Restoring Your Simulation Environment
Creating or Deleting an Alias
Using the Tcl Command-Line Interface
Overview
Executing UNIX Commands
Using Wildcards Characters in Tcl Commands
Command Description Conventions
alias
alias Command Syntax
alias Command Modifiers and Options
alias Command Examples
analog
assertion
attribute
attribute Command Syntax
attribute Command Options and Modifiers
attribute Command Examples
call
call Command Syntax
call Command Modifiers and Options
call Command Examples
check
check Command Syntax
check Command Modifiers and Options
check Command Examples
coverage
database
database Command Syntax
database Command Modifiers and Options
Opening a Database
Setting a Database As the Default
Displaying Information about Databases
Disabling a Database
Enabling a Database
Starting a New Incremental SHM Database File
Closing a Database
database Command Examples
deposit
Depositing Values to Vectors
deposit Command Syntax
deposit Command Modifiers and Options
deposit Command Examples
describe
describe Command Syntax
describe Command Modifiers and Options
describe Command Examples
drivers
drivers Command Syntax
drivers Command Modifiers and Options
drivers Command Report Format
drivers Command Examples
dumpsaif
dumpsaif Command Syntax
dumpsaif Command Options
Limitations
dumpsaif Command Examples
exit
exit Command Syntax
exit Command Modifiers and Options
exit Command Examples
finish
finish Command Syntax
finish Command Modifiers and Options
finish Command Examples
fmibkpt
fmibkpt Command Syntax
fmibkpt Command Modifiers and Options
force
Forcing Values to Vectors
force Command Syntax
force Command Modifiers and Options
force Command Examples
help
help Command Syntax
help Command Modifiers and Options
help Command Examples
history
history Command Syntax
history Command Options
history Command Examples
input
input Command Syntax
input Command Modifiers and Options
input Command Examples
loopvar
loopvar Command Syntax
loopvar Command Modifiers and Options
loopvar Command Examples
memory
VHDL Array Object
Memory Image File
memory Command Syntax
memory Command Modifiers and Options
Loading VHDL Memory
Dumping VHDL Memory
memory Command Examples
omi
omi Command Syntax
omi Command Modifiers and Options
Displaying Information
Issuing Commands
omi Command Examples
pause
pause Command Syntax
pause Command Options
pause Command Examples
probe
probe Command Syntax
probe Command Modifiers and Options
Creating a Probe
Deleting a Probe
Disabling a Probe
Enabling a Probe
Saving a Script to Re-Create Probes
Displaying Information about Probes
probe Command Examples
process
process Command Syntax
process Command Modifiers and Options
process Command Examples
release
release Command Syntax
release Command Modifiers and Options
release Command Examples
reset
reset Command Syntax
reset Command Modifiers and Options
reset Command Examples
restart
restart Command Syntax
restart Command Modifiers and Options
restart Command Examples
run
run Command Syntax
run Command Modifiers and Options
run Command Examples
save
save Command Syntax
save Command Modifiers and Options
save Command Examples
scope
scope Command Syntax
scope Command Modifiers and Options
scope Command Examples
simvision
simvision Command Syntax
simvision Command Options
simvision Command Examples
sn
sn Command Syntax
source
source Command Syntax
source Command Modifiers and Options
source Command Examples
stack
stack Command Syntax
stack Command Modifiers and Options
stack Command Examples
status
status Command Syntax
status Command Modifiers and Options
status Command Examples
stop
stop Command Syntax
stop Command Modifiers and Options
Creating a Breakpoint
Deleting a Breakpoint
Disabling a Breakpoint
Enabling a Breakpoint
Displaying Information about Breakpoints
stop Command Examples
Tcl Expressions as Arguments
strobe
strobe Command Syntax
strobe Command Modifiers and Options
strobe Command Examples
task
task Command Syntax
task Command Modifiers and Options
task Command Examples
time
time Command Syntax
time Command Modifiers and Options
time Command Examples
value
value Command Syntax
value Command Modifiers and Options
value Command Examples
version
version Command Syntax
version Command Modifiers and Options
version Command Examples
where
where Command Syntax
where Command Modifiers and Options
where Command Examples
Verilog-XL and NC-Verilog Simulator Interactive Debug Commands
Using the SimVision Analysis Environment
Maximizing Simulation Performance
Coding Style Guidelines
General Guidelines
Recommended Verilog Coding Practices
Coding Styles to Avoid
Refining the Testbench Strategy
Use C and Tcl
Use $readmemb or $readmemh for Vectors
Use $test$plusargs for Conditional Code
Create Self-Checking Tests
Avoiding Unnecessary Recompilation
Run the Parser in Update Mode (ncvlog -update)
Eliminate Cross-File Inheritance
Use One Module per File
Avoid Modules in `include Files
Avoid Compile-Time Conditional Code
Using Command-Line Options
Options That Improve Performance
Options That Degrade Performance
Using the Profiler to Identify and Eliminate Simulation Bottlenecks
Stream Counts
Most Active Modules
Stream Type Summary Counts
Using the VHDL Source Profiler
Limitations
Example Output
Changing Page Size Parameters for ncsim on HP-UX
Timing Checks
Overview
Timing Checks
$setup
$hold
$setuphold
$width
$period
$skew
$timeskew
$fullskew
$recovery
$removal
$recrem
$nochange
Using Edge-Control Specifiers
Using Notifiers
Enabling Timing Checks with Conditioned Events
Negative Timing Check Limits in $setuphold and $recrem
Effects of Delayed Signals on Timing Checks
Explicitly Defining Delayed Signals
Calculation of Delayed Signals and Limit Modification
Glitch Suppression
Filtering Out Negative Timing Checks or Warning Messages
Adjusting Timing Limits for Invalid Timing Check Timing Windows
Effects of Delayed Signals on Path Delays
Restrictions
Exception Handling
Timing Violation Messages
SDF Annotation of Timing Checks
Referencing Verilog HDL Source Constructs
$setuphold Timing Checks
Interconnect and Module Path Delays
Interconnect Delays
Default Interconnect Delays
Interconnect Delays and -intermod_path
Pulse Handling
SDF Annotation of Interconnect Delays
PLI Annotation of Interconnect Delays
Module Path Delays
Specify Blocks
Describing Module Paths
Establishing Full or Parallel Connection Paths
Assigning Delays to Module Paths
Selecting a Delay When Multiple Delays Are Specified for a Path
Specify Properties for Module Path Delays
Mixing Module Path Delays and Distributed Delays
Strength Changes on Path Inputs
Driving Wired Logic Outputs
Simulating Path Outputs That Drive Other Path Outputs
Enhancing Path Delay Accuracy
Restrictions
Examples
SDF Annotation of Module Path Delays
SDF Timing Annotation
VITAL SDF Annotation
Compiling the SDF File
Writing an SDF Command File
Specifying an SDF Command File
Controlling SDF Annotator Output
Multi-Source Interconnect Delays During VITAL SDF Annotation
Command-Line Options that Affect SDF Annotation
Verilog SDF Annotation
Overview of Verilog SDF Annotation
Annotating with $sdf_annotate
Using an SDF Command File
Using a Configuration File
Controlling SDF Annotator Output
Command-Line Options that Affect SDF Annotation
SDF Annotation for Mixed-Language Designs
Utilities
VHDL Configuration File Generator
Configuration Generator Command Syntax
Configuration File Generator Options
Search Order for Selecting Bindings
Limitations
Example Command Lines
ncdc
ncdc Command Syntax
ncdc Command Options
Limitations
Example ncdc Command Lines
ncexport
ncexport Command Syntax
ncexport Command Options
Example ncexport Command Lines
Example
ncgentb
ncgentb Command Syntax
ncgentb Command Options
Example ncgentb Command Lines
Example
Issues and Limitations
nchelp
nchelp Command Syntax
nchelp Command Options
Example nchelp Command Lines
ncls
Listing Objects
ncls Command Syntax
ncls Command Options
Example ncls Command Lines
Object Types Listed by ncls
ncmirror
nc_mirror
nc_deposit
nc_force
nc_release
Example
Restrictions
ncpack
ncpack Command Syntax
ncpack Command Options
Example ncpack Command Lines
ncprep
ncprep Command Syntax
ncprep Command Options
Example ncprep Run
Example ncprep Output Files
Verilog-XL Command-Line Options Translation
Using Interactive Debugging Commands
PLI Tasks
SDF Annotation
Troubleshooting
ncprotect
Restrictions
ncprotect Command Syntax
ncprotect Command Options
Example ncprotect Command Lines
Protecting IP Using Default Parameters
Protecting IP with User-Defined Algorithms and Keys
Protection of Verilog and Verilog AMS Designs
Protection of VHDL and VHDL AMS Designs
ncrm
ncrm Command Syntax
ncrm Command Options
Example ncrm Command Lines
ncsdfc
ncsdfc Command Syntax
ncsdfc Command Options
Example ncsdfc Command Lines
ncshell
ncshell Command Syntax
ncshell Command Options
The Foreign Attribute
Importing LMSFI Models into VHDL
Importing SWIFT Models into VHDL
Importing FMI Models into VHDL
ncsuffix
ncsuffix Command Syntax
ncsuffix Command Options
Example ncsuffix Command Lines
ncupdate
ncupdate Command Syntax
ncupdate Command Options
Example ncupdate Command Lines
shellgen
shellgen Command Syntax
shellgen Command Options
simvisdbutil
The Programming Language Interface (PLI)
Importing Foreign Models
The SmartModel SWIFT Interface
Using the SmartModel SWIFT Interface with NC-Verilog
Integrating SmartModel Library Models with NC-Verilog on UNIX
Integrating SmartModel Library Models with NC-Verilog on Windows NT
Running SmartModel Library Models with NC-Verilog
The Hardware Modeling Interface (LMSI)
Using LMG Hardware Models with NC-Verilog
Integrating the LMG Hardware Modeling Interface with NC-Verilog
Running LMG Hardware Models with NC-Verilog
Specifying the Delay Mode for LMG Hardware Models
The Open Model Interface (OMI)
Integrating OMI Models
Generating a Model Shell
Integrating an OMI Model into a Verilog Design
Integrating an OMI Model into a VHDL Design
Modifying a Model Shell
Simulating a Design With Imported OMI Models
Simulating OMI Models Controlled by C++ Model Managers
Co-Simulation with the Palladium™ Design Verification System
Overview
Advantages of Simulation Acceleration
Co-Simulation
Documentation
Basics of Tcl
Overview
Tcl Basics
Comments
Tcl Variables
Variable Substitution
Tcl Commands
Command Substitution
Backslash Substitution
Quoting Words in a Command
Extensions to Tcl
Value Substitution
The @ Character and Escaped Names
Expression Evaluation
Verilog Expressions
VHDL Expressions
Tcl Functions for Type Conversion
Enabling Tk in the NC-Verilog Simulator
SDF File Syntax
Overview
SDF File Conventions
Identifiers
Operator Precedence
OVI Standard 3.0 SDF Keywords
SDF File Keyword Constructs
DELAYFILE Keyword
CELL Keyword and Constructs
CELLTYPE Keyword
INSTANCE Keyword
INCLUDE Keyword
DELAY Keyword and Constructs
ABSOLUTE Keyword
INCREMENT Keyword
IOPATH Keyword
COND Keyword
CONDELSE Keyword
RETAIN Keyword
PORT Keyword
INTERCONNECT Keyword
NETDELAY Keyword
DEVICE Keyword
PATHPULSE Keyword
PATHPULSEPERCENT Keyword
TIMINGCHECK Keyword and Constructs
COND Keyword
SETUP Keyword
HOLD Keyword
SETUPHOLD Keyword
RECOVERY Keyword
REMOVAL Keyword
RECREM Keyword
SKEW Keyword
WIDTH Keyword
PERIOD Keyword
NOCHANGE Keyword
TIMINGENV Keyword and Constructs
PATHCONSTRAINT Keyword
PERIODCONSTRAINT Keyword
SKEWCONSTRAINT Keyword
SUM Keyword
DIFF Keyword
ARRIVAL Keyword
DEPARTURE Keyword
SLACK Keyword
WAVEFORM Keyword
OVI SDF Specification Version Differences
SDF Version 1.* Constructs
SDF Version 2.* Constructs
SDF Version 3.* Constructs
SDF File Examples
Example 1
Example 2
Example 3
System Task Support in the NC-Verilog Simulator
Example Tcl Script for $countdrivers
Example Tcl Script for $display
The $readmemb and $readmemh System Tasks
Example Tcl Script for $readmem
Example Tcl Script for $reset_count
Example Tcl Script for $reset_value
Example PLI Routine for $test$plusargs
Example Tcl Script for $showscopes
Randomization and Constraints Extensions
Randomization System Tasks
$vr_keep_only()
$vr_keep_out()
$vr_set_weight()
$vr_constraint()
$vr_soft_constraint()
$vr_set_mode()
$vr_reset_distribution()
$vr_set_global_seed()
$vr_set_seed()
$vr_next()
$vr_next_bias()
$vr_disable_randomization()
$vr_enable_randomization()
$vr_display()
Performance Considerations
Glossary
Index
Cadence® NC-Verilog® Simulator Help
Product Version 5.6
November 2005
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NC-Verilog Simulator Help
Contents
1
Running the NC-Verilog Simulator
Overview of the NC-Verilog Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Native Compiled Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
The Interleaved Native Compiled Code (INCA) Architecture . . . . . . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Language Support
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Requirements
Setting Up Your Design Environment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Environment Setup Files
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PATH and Library Path Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Single-Step Invocation With ncverilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Multi-Step Invocation (Library-Based Mode)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
64-Bit NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Platform Support
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Running the 64-Bit Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Libraries and Snapshots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PLI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Functional Differences Between 32-bit and 64 bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Simulator Library Databases
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Simulating Large Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
About Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Invoking the Documentation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Printing Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Searching Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Getting Help on Commands to Run Tools
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Getting Help on Simulator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Getting Help on Tool Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
November 2005
3
Product Version 5.6
NC-Verilog Simulator Help
Return Codes for Error Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Other Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3
Using NCLaunch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4
Running NC-Verilog with the ncverilog Command. . . . . . . . . . . . . . . . . . . . . . . . . . 56
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
How ncverilog Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ncverilog Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ncverilog Command Options
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Plus Options for NC-Verilog Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Verilog-XL Command-Line Options Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Verilog-XL Dash (-) Option Translation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Verilog-XL Plus (+) Option Translation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Example ncverilog Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Mapping of Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Updating Design Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Using +ncuid+ to Run in Regression Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Using -R and -r to Simulate a Snapshot
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Using -R to Simulate a Snapshot Multiple Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Using -r to Simulate a Saved Snapshot
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PLI Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Using $test$plusargs to Selectively Perform Annotations . . . . . . . . . . . . . . . . . . . . . 98
Specifying Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Turning Off SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Controlling SDF Annotator Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
November 2005
4
Product Version 5.6
NC-Verilog Simulator Help
5
Modeling Your Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Arrays of Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Instance Array Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Array Range Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Ports of Instance Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Differing Instances in an Array
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Hierarchical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
NC-Verilog Restrictions to the IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Arrays of Instances and Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Randomization and Constraints Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Verilog IEEE Std 1364-2001 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Comma-Separated Sensitivity List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Combinational Logic Sensitivity Token . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Variable Declaration with Initial Value Assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . 113
Combined Port and Data Type Declarations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Input and Output Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Signed Arithmetic Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Re-Entrant Tasks and Recursive Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
File I/O Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PLA System Task Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
‘ifndef and ‘elsif Conditional Compilation Compiler Directives . . . . . . . . . . . . . . . . . 129
Parameter Value Assignment by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
$value$plusargs System Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Disabling Implicit Net Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Indexed Vector Part-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Power Operator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Local Parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Implicit Nets with Continuous Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Automatic Width Extension of X and Z Constants beyond 32 Bits . . . . . . . . . . . . . . 137
Line and File Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Generate Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Multi-Dimensional Arrays and Arrays of Net Data Types . . . . . . . . . . . . . . . . . . . . . 154
November 2005
5
Product Version 5.6
NC-Verilog Simulator Help
Bit-Selects and Part-Selects within Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Verilog Configurations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Sized and Typed Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SystemVerilog Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Loading Stimulus from an ASCII File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Syntax
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Data File Format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
$loadStimFileX Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
$loadStrobeFileX/$strobeStimX Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Loading Scan Chain Elements
repeat Loop Expression Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6
Setting Up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
The Library.Cell:View Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
The cds.lib File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
The Work Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
cds.lib Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
cds.lib Syntax Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Example cds.lib File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Binding One Library to Multiple Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Debugging cds.lib Files
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
The hdl.var File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
hdl.var Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
hdl.var Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
hdl.var Syntax Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Example hdl.var File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Debugging hdl.var Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
The setup.loc File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
setup.loc Syntax Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
November 2005
6
Product Version 5.6
NC-Verilog Simulator Help
Directory Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7
Compiling Verilog Source Files with ncvlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ncvlog Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
ncvlog Command Options
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Example ncvlog Command Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
hdl.var Variables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Conditionally Compiling Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Controlling the Compilation of Design Units into Library.Cell:View . . . . . . . . . . . . . . . . 245
Compiling without Setup Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
The LIB_MAP and VIEW_MAP Variables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
The -libmap Command-Line Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
The WORK and VIEW Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
The -work and -view Command-Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
The -specificunit Command-Line Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
The `worklib and `view Compiler Directives
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Mapping of Modules Defined within `include Files . . . . . . . . . . . . . . . . . . . . . . . . . . 256
. . . . 258
cds.lib Files that Map Multiple Logical Names to the Same Physical Directory
Defining Macros on the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
8
Elaborating the Design with ncelab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
ncelab Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
VHDL Only Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Verilog Only Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
AMS Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
NC-SC Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
November 2005
7
Product Version 5.6
NC-Verilog Simulator Help
ncelab Command Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Example ncelab Command Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
hdl.var Variables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
How Modules and UDPs Are Resolved during Elaboration . . . . . . . . . . . . . . . . . . . . . . 351
The Default Binding Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Default Configuration Using a Library Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
The -binding Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
The `uselib Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Using a Verilog Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Enabling Read, Write, or Connectivity Access to Simulation Objects . . . . . . . . . . . . . . 377
Regression Mode and Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Regression Mode and PLI/VPI/VHPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Regression Mode and the SimVision Debug Environment
. . . . . . . . . . . . . . . . . . . . 380
Using -access to Specify Read/Write/Connectivity Access . . . . . . . . . . . . . . . . . . . 381
Using -afile to Include an Access File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Generating an Access File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Guidelines for Access Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Disabling Timing in Selected Portions of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Selecting a Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Delay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Reasons to Select a Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Setting a Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Timescales and Simulation Time Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Overriding Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Delay Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Decompiling with Delay Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Macro Module Expansion and Delay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Summary of Delay Mode Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Setting Pulse Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Global Pulse Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Pulse Control for Specific Modules and Module Paths . . . . . . . . . . . . . . . . . . . . . . . 411
Pulse Filtering Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
November 2005
8
Product Version 5.6
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