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AR8031datasheet.pdf
General Description
Features
AR8031 Functional Block Diagram
Revision History
Table of Contents
1. Pin Descriptions
1.1 Power-on Strapping Pins
1.1.1 Mode Definition
2. Functional Description
2.2 Modes of Operation
2.2.1 Operation Mode, Copper
2.2.2 Operation Mode, Fiber
2.2.3 Operation Mode, Media Converter
2.2.4 Operation Mode, Auto-Media Detect (Combo)
2.3 Transmit Functions
2.4 Receive Functions
2.4.1 Decoder Modes
2.4.2 Analog to Digital Converter
2.4.3 Echo Canceller
2.4.4 NEXT Canceller
2.4.5 Baseline Wander Canceller
2.4.6 Digital Adaptive Equalizer
2.4.7 Auto-Negotiation
2.4.8 Smartspeed Function
2.4.9 Automatic MDI/MDIX Crossover
2.4.10 Polarity Correction
2.5 Loopback Modes
2.5.1 Digital Loopback
2.5.2 External Cable Loopback
2.5.3 Remote PHY Loopback
2.6 Cable Diagnostic Test
2.7 Fiber Mode Support
2.7.1 IEEE 802.3 Remote Fault Indication Support
2.7.2 Fault Propagation
2.8 LED Interface
2.9 Power Supplies
2.10 Management Interface
2.11 Timing Sychronization
2.11.1 Synchronous Ethernet - Physical Layer Timing Synchronization
2.12 Atheros Green EthosTM
2.12.1 Low Power Modes
2.12.2 Shorter Cable Power Mode
2.12.3 Hibernation Mode
2.13 IEEE 802.3az and Energy Efficient Ethernet
2.14 IEEE 802.3az Energy Efficient Ethernet
2.14.1 IEEE 802.3az LPI Mode
2.14.2 Atheros SmartEEE
2.15 Wake On LAN (WoL)
3. Electrical Characteristics
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 RGMII Characteristics
3.4 SerDes and SGMII Characteristics
3.5 MDIO Timing
3.6 MDIO/MDC DC Characteristic
3.7 Clock Characteristics
3.8 Power Pin Current Consumption
3.9 Typical Power Consumption Parameters
3.10 Power-on Sequence, Reset and Clock
3.10.1 Power-on Sequence
3.10.2 Reset and Clock Timing
3.11 Digital Pin Design Guide
4. Register Descriptions
4.1 Register Summary
4.2 MII Registers
4.2.1 Control Register - Copper Page
4.2.2 Control - Fiber Page
4.2.3 Status Register - Copper Page
4.2.4 Status Register - Fiber Page
4.2.5 PHY Identifier
4.2.6 PHY Identifier2
4.2.7 Auto-Negotiation Advertisement Register - Copper Page
4.2.8 Auto-Negotiation Advertisement Register - Fiber Page
4.2.9 Link Partner Ability Register - Copper Page
4.2.10 Link Partner Ability Register - Fiber Page
4.2.11 Auto-Negotiation Expansion Register - Copper Page
4.2.12 Auto-Negotiation Expansion Register - Fiber Page
4.2.13 Next Page Transmit Register - Copper Page
4.2.14 Next Page Transmit Register - Fiber Page for 1000 BASE-X, SGMII
4.2.15 Link Partner Next Page Register - Copper Page
4.2.16 Link Partner Next Page Register - Fiber Page for 1000 BASE-X, SGMII
4.2.17 1000 BASE-T Control Register
4.2.18 1000 BASE-T Status Register
4.2.19 MMD Access Control Register
4.2.20 MMD Access Address Data Register
4.2.21 Extended Status Register
4.2.22 Function Control Register
4.2.23 PHY-Specific Status Register - Copper Page
4.2.24 PHY-Specific Status Register - Fiber Page
4.2.25 Interrupt Enable Register
4.2.26 Interrupt Status Register
4.2.27 Smart Speed Register
4.2.28 Cable Diagnostic Tester (CDT) Control Register
4.2.29 LED Control
4.2.30 Manual LED Override Register
4.2.31 Copper/Fiber Status Register
4.2.32 Cable Diagnostic Tester Status Register
4.2.33 Debug Port (Address offset set)
4.2.34 Debug Port2 (R/W port)
4.2.35 Chip Configure Register
4.3 Debug Register Descriptions
4.3.1 Analog Test Control
4.3.2 SerDes Test and System Mode Control
4.3.3 100BASE-TX Test Mode Select
4.3.4 Hib Control and Auto-Negotiation Test Register
4.3.5 External Loopback Selection
4.3.6 Test Configuration for 10BASE-T
4.3.7 Power Saving Control
4.4 MDIO Interface Register
4.4.1 PCS Control
4.4.2 PCS Status
4.4.3 EEE Capability
4.4.4 EEE Wake Error Counter
4.4.5 P1588 Control Register
4.4.6 P1588 RX_seqid
4.4.7 P1588 rx_sourcePort_identity
4.4.8 P1588 rx_sourcePort_identity
4.4.9 P1588 rx_sourcePort_identity
4.4.10 P1588 rx_sourcePort_identity
4.4.11 P1588 rx_sourcePort_identity
4.4.12 P1588 rx_time_stamp
4.4.13 P1588 rx_time_stamp
4.4.14 P1588 rx_time_stamp
4.4.15 P1588 rx_time_stamp
4.4.16 P1588 rx_time_stamp
4.4.17 P1588 Rx_frac_nano
4.4.18 P1588 Rx_frac_nano
4.4.19 P1588 Tx_seqid
4.4.20 P1588 tx_sourcePort_Identity
4.4.21 P1588 tx_sourcePort_Identity
4.4.22 P1588 tx_sourcePort_Identity
4.4.23 P1588 tx_sourcePort_Identity
4.4.24 P1588 tx_sourcePort_Identity
4.4.25 P1588 tx_sourcePort_Identity
4.4.26 P1588 tx_timestamp
4.4.27 P1588 tx_timestamp
4.4.28 P1588 tx_time_stamp
4.4.29 P1588 tx_time_stamp
4.4.30 P1588 tx_time_stamp
4.4.31 P1588 Tx_frac_nano
4.4.32 P1588 tx_frac_nano
4.4.33 P1588 Orgin_Correction_o
4.4.34 P1588 Orgin_Correction_o
4.4.35 P1588 Orgin_Correction_o
4.4.36 P1588 Orgin_Correction_o
4.4.37 P1588 Ingress_trig_time_o
4.4.38 P1588 Ingress_trig_time_o
4.4.39 P1588 Ingress_trig_time_o
4.4.40 P1588 Ingress_trig_time_o
4.4.41 P1588 Tx_latency_o
4.4.42 P1588 Inc_value_o
4.4.43 P1588 Inc_value_o
4.4.44 P1588 Nano_offset_o
4.4.45 P1588 Nano_offset_o
4.4.46 P1588 Sec_offset_o
4.4.47 P1588 Sec_offset_o
4.4.48 P1588 Sec_offset_o
4.4.49 P1588 Real_time_i
4.4.50 P1588 Real_time_i
4.4.51 P1588 Real_time_i
4.4.52 P1588 Real_time_i
4.4.53 P1588 Real_time_i
4.4.54 P1588 Rtc_frac_nano_i
4.4.55 P1588 Rtc_frac_nano_i
4.4.56 Wake-on-LAN Internal Address 1
4.4.57 Wake-on-LAN Internal Address 2
4.4.58 Wake-on-LAN Internal Address 3
4.4.59 Rem_phy_lpbk
4.4.60 SmartEEE Control 1
4.4.61 SmartEEE Control 2
4.4.62 SmartEEE control 3
4.4.63 Auto-Negotiation Control 1
4.4.64 Auto-Negotiation Status
4.4.65 Auto-Negotiation XNP Transmit
4.4.66 Auto-Negotiation XNP transmit1
4.4.67 Auto-Negotiation XNP Transmit2
4.4.68 Auto-Negotiation LP XNP Ability
4.4.69 Auto-Negotiation LP XNP Ability1
4.4.70 Auto-Negotiation LP XNP ability2
4.4.71 EEE Advertisement
4.4.72 EEE LP advertisement
4.4.73 EEE Ability Auto-negotiation Result
4.4.74 SGMII Control Register 1
4.4.75 SGMII Control Register 2
4.4.76 SGMII Control Register 3
4.4.77 CLK_25M Clock Select
4.4.78 1588 Clock Select
5. Package Dimensions
6. Ordering Information
7. Topside Marking
AR8031 Integrated 10/100/1000 Mbps Ethernet
Transceiver
Data Sheet
August 2011
Version 1.1
General Description
The AR8031 is part of the Arctic family of
devices — which includes the AR8031, AR8033,
and AR8035. The AR8031 is Atheros’ 4th
generation, single port, 10/100/1000 Mbps, Tri-
speed Ethernet PHY. It supports both RGMII
and SGMII interfaces to the MAC.
The AR8031 provides a low power, low BOM
(Bill of Materials) cost solution for
comprehensive applications including
enterprise, carrier and home networks such as
CPE, home gateway, enterprise switch, carrier
switch/router, mobile base station and base
station controller, optical module and media
converter, industry automation and
measurement.
The AR8031 integrates Atheros Green ETHOS®
power saving technologies and significantly
saves power not only during the work time,
but also overtime. Atheros Green ETHOS®
power savings include ultra-low power in
cable unplugged mode or port power down
mode, and automatic optimized power saving
based on cable length. The AR8031 also
supports IEEE 802.3az EEE standard (Energy
Efficient Ethernet) and Atheros proprietary
SmartEEE. SmartEEE allows legacy MAC/SoC
devices without 802.3az support to function as
a complete 802.3az system. Further, the AR8031
supports Wake-on-LAN (WoL) feature to be
able to help manage and regulate total system
power requirements.
The AR8031 embeds CDT (Cable Diagnostics
Test) technology on-chip which allows
customers to measure cable length, detect the
cable status, and identify remote and local PHY
malfunctions, bad or marginal patch cord
segments or connectors. Some of the possible
problems that can be detected include opens,
shorts, cable impedance mismatch, bad
connectors, termination mismatch, and a bad
transformer.
The AR8031 requires only a single, 3.3V power
supply. On-chip regulators provide all the
other required voltages. It integrates the
termination R/C circuitry on both the MAC
interfaces (RGMII/SGMII) and the serial
resistors for the line side.
The AR8031 device also incorporates a 1.25
GHz SerDes. This interface can be connected
directly to a fiber-optic transceiver for 1000
BASE-X /100 BASE-FX mode or to MAC
device for SGMII interface.
The AR8031 supports both 1588v2 and
synchronous Ethernet to offer a complete time
synchronization solution to meet the next
generation network requirements. The key new
features supported by the device are:
n Clock synchronization between slave and
grandmaster by the exchange of PTP
packets. Supports IEEE 1588v2 by offering a
1588 paket parser, accurate time-stamping
and insertion to support both one-step and
two-step clock modes
n Supports both IEEE 1588v2 and
Synchronous Ethernet by offering recovered
clock output from data on the network-line
side.
The AR8031 supports IEEE 802.3az Energy
Efficient Ethernet (EEE) standard. The key
features supported by the device are:
n 10 BASE-Te PHY uses reduced transmit
amplitude.
n 100 BASE-TX and 1000 BASE-T use Low
Power Idle (LPI) mode to turn off unused
analog and digital blocks to save power
while data traffic is idle.
Features
n 10/100/1000 BASE-T IEEE 802.3 compliant
n Supports 1000 BASE-T PCS and auto-
negotiation with next page support
n Supports RGMII and/or SGMII interfaces
to MAC devices
n Supports Fiber and Copper combo mode
when MAC interface works in RGMII mode
n Supports additional IEEE 1000 BASE-X and
100 BASE-FX with Integrated SerDes
n RGMII timing modes support internal delay
and external delay on Rx path
© 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,
Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The
Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
• 1
COMPANY CONFIDENTIAL
n Automatic channel swap (ACS)
n Automatic MDI/MDIX crossover
n Automatic polarity correction
n IEEE 802.3u compliant Auto-Negotiation
n Jumbo Frame support up to 10KB (full
duplex)
n Multiple loopback modes for diagnostics
n Robust Surge Protection with ±750 V/
differential mode and ±4 kV/common
mode
n Cable Diagnostic Test (CDT)
n Single power supply: 3.3V, optional for
external regulator for core voltage
n 6mm x 6mm, 48-pin QFN package
n Industry temperature (I-temp) option
available.
n Supports Atheros Green ETHOS® power
saving modes with internal automatic DSP
power saving scheme
n Supports IEEE 802.3az (Energy Efficient
Ethernet)
n Supports SmartEEE which allows MAC/
SoC devices withoug 802.3az support to
function as the complete 802.3az system
n Supports Wake-on-LAN (WoL) to detect
magic packet and notify the sleeping system
to wake up
n Fully integrated digital adaptive equalizers,
echo cancellers, and Near End Crosstalk
(NEXT) cancellers
n Supports Synchronous Ethernet with
selectable recovered clock output
n Robust Cable Discharge Event (CDE)
protection of ±6 kV
n Error-free operation over up to 140 meters
of CAT5 cable
AR8031 Functional Block Diagram
DAC
Waveshape
Filter
TRD[0:3]
Hybrid
Circut
PMA
PGA
ADC
AGC
Echo
Canceller
Next
Canceller
Feed
Forward
Equalizer
Timing and
Phase
Recovery
Decision
Feedback
Equalizer
Trellis
Decoder
Deskewer
Sync-E
Auto-
Negotiation
MII Management
Registers
1588v2
DLL
Symbol
Encoder
RGMII
RGMII
SGMII/
SerDes
Symbol
Decoder
Serial
Interface
PCS
2 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver
2 August 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Revision History
Date
2010/11/15
2011/4/14
2011/8/29
Revision
0.1
1.0
1.1
Revsion Details
First draft
General Description
n Overall update for revision from MPW to mass production
n Block diagram: add SYNC-E and 1588v2 block
Pin Descriptions
n RXD [3:0], RX_DV pin damping resistor 22ohm requirement is deleted.
n RST pin type change from "IH" to "I,” mass production chip does not have
internal weak PU
n INT, WOL_INT from "I/O active high" change to "D active low" need an
external PU
n Power on strapping LED_ACT from "1.1V/1.2V selection" to "PHY
ADDRESS [2]".
n LED_ACT/LED_LINK1000/LED_LINK10_100 from internal weak "PD"
change to internal weak "PU".
Functional Descriptions
n 2.2.4 Mode definition adds work mode"1011" combo mode.
Electrical Characteristics
n 3.1 Absolute Maximum Rating: update CDM max
n 3.2 Recommeded Operating Condition: update Tj max
n 3.7 Clock Characteristics: update values in Table 3-13 Recommended Crystal
Parameters
n Update Table 3-11 MDIO AC Characteristic to add tmdelay row
Register
n 4.2.29LED Control (0x18): update register bit definitions
n 4.2.30 Manual LED Override (0x19): new register
Topside Marking
n Add topside marking illustration
Electrical Characteristics
n 3.2 Recommended Operation Conditions: delete DVDDL/AVDDL, JA; add
VDDH_REG, JT, AVDDL/DVDDL (industrial and commercial); add
thermal conditions
n 3.6 change title from MDIO DC Charateristics to MDIO/MDC DC...; change
VIH min value and VIL max value
n 3.7 table 3-14: change Jitterpk-pk max value to 100
n 3.11 Digital pin design guide (new)
Registers
n 4.2.3 Status Register – Copper page, change bit[8] reset value to always 1
n 4.3.4 Hib control and auto-neg test register: change bit[12], [6:5] to reserved
n 4.3.5 External loopback selection, change bit[0] to R/W
n 4.3.7 Power saving control (new)
n 4.4.75 SGMII Control register 2 (new)
n 4.4.76 SGMII Control register 3(new)
n 4.4.78 1588 RTC clock select register (new)
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver 3
August 2011 3
4 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver
4 August 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR8031 Functional Block Diagram .............. 2
Revision History ............................................. 3
Table of Contents ............................................ 5
1 Pin Descriptions ............................ 9
1.1 Power-on Strapping Pins ...................... 13
1.1.1 Mode Definition .......................... 14
2 Functional Description ............... 15
2.2 Modes of Operation ............................... 16
2.2.1 Operation Mode, Copper .......... 16
2.2.2 Operation Mode, Fiber ............... 16
2.2.3 Operation Mode, Media Converter
17
2.2.4 Operation Mode, Auto-Media
Detect (Combo) ........................... 17
2.3 Transmit Functions ................................ 18
2.4 Receive Functions .................................. 18
2.4.1 Decoder Modes ........................... 18
2.4.2 Analog to Digital Converter ...... 18
2.4.3 Echo Canceller ............................. 18
2.4.4 NEXT Canceller .......................... 18
2.4.5 Baseline Wander Canceller ....... 18
2.4.6 Digital Adaptive Equalizer ....... 18
2.4.7 Auto-Negotiation ........................ 19
2.4.8 Smartspeed Function ................. 19
2.4.9 Automatic MDI/MDIX Crossover
19
2.4.10 Polarity Correction ..................... 19
2.5 Loopback Modes .................................... 19
2.5.1 Digital Loopback ......................... 19
2.5.2 External Cable Loopback ........... 19
2.5.3 Remote PHY Loopback .............. 20
2.6 Cable Diagnostic Test ............................ 20
2.7 Fiber Mode Support .............................. 20
2.7.1 IEEE 802.3 Remote Fault Indication
Support ......................................... 20
2.7.2 Fault Propagation ....................... 21
2.8 LED Interface .......................................... 21
2.9 Power Supplies ....................................... 22
2.10 Management Interface .......................... 24
2.11 Timing Sychronization ......................... 26
2.11.1 Synchronous Ethernet — Physical
Layer Timing Synchronization . 29
2.12 Atheros Green EthosTM ...................... 30
2.12.1 Low Power Modes ..................... 30
2.12.2 Shorter Cable Power Mode ....... 30
2.12.3 Hibernation Mode ...................... 30
2.13 IEEE 802.3az and Energy Efficient
Ethernet 30
2.14 IEEE 802.3az Energy Efficient Ethernet 30
2.14.1 IEEE 802.3az LPI Mode .............. 30
2.14.2 Atheros SmartEEE ...................... 31
2.15 Wake On LAN (WoL) .......................... 32
3 Electrical Characteristics ............33
3.1 Absolute Maximum Ratings ................ 33
3.2 Recommended Operating Conditions 33
3.3 RGMII Characteristics ........................... 34
3.4 SerDes and SGMII Characteristics ...... 37
3.5 MDIO Timing ......................................... 39
3.6 MDIO/MDC DC Characteristic .......... 39
3.7 Clock Characteristics ............................. 40
3.8 Power Pin Current Consumption ....... 41
3.9 Typical Power Consumption Parameters
41
3.10 Power-on Sequence, Reset and Clock 44
3.10.1 Power-on Sequence .................... 44
3.10.2 Reset and Clock Timing ............. 44
3.11 Digital Pin Design Guide ..................... 44
4 Register Descriptions ..................47
4.1 Register Summary ................................. 47
4.2 MII Registers .......................................... 47
4.2.1 Control Register — Copper Page 49
4.2.2 Control — Fiber Page ................. 50
4.2.3 Status Register — Copper Page 51
4.2.4 Status Register — Fiber Page .... 53
4.2.5 PHY Identifier ............................. 54
4.2.6 PHY Identifier2 ........................... 55
4.2.7 Auto-Negotiation Advertisement
Register — Copper Page ........... 55
4.2.8 Auto-Negotiation Advertisement
Register — Fiber Page ................ 57
4.2.9 Link Partner Ability Register —
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver 5
August 2011 5
Copper Page ................................ 58
4.2.10 Link Partner Ability Register —
Fiber Page .................................... 59
4.2.11 Auto-Negotiation Expansion
Register — Copper Page ............ 60
4.2.12 Auto-Negotiation Expansion
Register — Fiber Page ................ 61
4.2.13 Next Page Transmit Register —
Copper Page ................................ 62
4.2.14 Next Page Transmit Register —
Fiber Page for 1000 BASE-X, SGMII
62
4.2.15 Link Partner Next Page Register —
Copper Page ................................ 63
4.2.16 Link Partner Next Page Register —
Fiber Page for 1000 BASE-X, SGMII
64
4.2.17 1000 BASE-T Control Register .. 64
4.2.18 1000 BASE-T Status Register ..... 66
4.2.19 MMD Access Control Register . 67
4.2.20 MMD Access Address Data
Register ......................................... 67
4.2.21 Extended Status Register ........... 68
4.2.22 Function Control Register ......... 68
4.2.23 PHY-Specific Status Register —
Copper Page ................................ 69
4.2.24 PHY-Specific Status Register —
Fiber Page .................................... 71
4.2.25 Interrupt Enable Register .......... 72
4.2.26 Interrupt Status Register ............ 73
4.2.27 Smart Speed Register ................. 75
4.2.28 Cable Diagnostic Tester (CDT)
Control Register .......................... 76
4.2.29 LED Control ................................. 76
4.2.30 Manual LED Override Register 77
4.2.31 Copper/Fiber Status Register ... 78
4.2.32 Cable Diagnostic Tester Status
Register ......................................... 79
4.2.33 Debug Port (Address offset set) 80
4.2.34 Debug Port2 (R/W port) ............ 80
4.2.35 Chip Configure Register ............ 80
4.3 Debug Register Descriptions ................ 83
4.3.1 Analog Test Control ................... 83
4.3.2 SerDes Test and System Mode
Control .......................................... 83
4.3.3 100BASE-TX Test Mode Select .. 84
4.3.4 Hib Control and Auto-Negotiation
Test Register ................................ 85
4.3.5 External Loopback Selection ..... 85
4.3.6 Test Configuration for 10BASE-T
85
4.3.7 Power Saving Control ................ 86
4.4 MDIO Interface Register ....................... 87
4.4.1 PCS Control ................................. 90
4.4.2 PCS Status .................................... 90
4.4.3 EEE Capability ............................ 91
4.4.4 EEE Wake Error Counter .......... 91
4.4.5 P1588 Control Register .............. 92
4.4.6 P1588 RX_seqid ........................... 93
4.4.7 P1588 rx_sourcePort_identity ... 93
4.4.8 P1588 rx_sourcePort_identity ... 93
4.4.9 P1588 rx_sourcePort_identity ... 93
4.4.10 P1588 rx_sourcePort_identity ... 94
4.4.11 P1588 rx_sourcePort_identity ... 94
4.4.12 P1588 rx_time_stamp ................. 94
4.4.13 P1588 rx_time_stamp ................. 94
4.4.14 P1588 rx_time_stamp ................. 95
4.4.15 P1588 rx_time_stamp ................. 95
4.4.16 P1588 rx_time_stamp ................. 95
4.4.17 P1588 Rx_frac_nano ................... 95
4.4.18 P1588 Rx_frac_nano ................... 96
4.4.19 P1588 Tx_seqid ........................... 96
4.4.20 P1588 tx_sourcePort_Identity ... 96
4.4.21 P1588 tx_sourcePort_Identity ... 96
4.4.22 P1588 tx_sourcePort_Identity ... 97
4.4.23 P1588 tx_sourcePort_Identity ... 97
4.4.24 P1588 tx_sourcePort_Identity ... 97
4.4.25 P1588 tx_sourcePort_Identity ... 97
4.4.26 P1588 tx_timestamp ................... 98
4.4.27 P1588 tx_timestamp ................... 98
4.4.28 P1588 tx_time_stamp ................. 98
4.4.29 P1588 tx_time_stamp ................. 98
4.4.30 P1588 tx_time_stamp ................. 98
4.4.31 P1588 Tx_frac_nano ................... 99
4.4.32 P1588 tx_frac_nano ..................... 99
4.4.33 P1588 Orgin_Correction_o ........ 99
4.4.34 P1588 Orgin_Correction_o ...... 100
4.4.35 P1588 Orgin_Correction_o ...... 100
4.4.36 P1588 Orgin_Correction_o ...... 100
4.4.37 P1588 Ingress_trig_time_o ...... 100
4.4.38 P1588 Ingress_trig_time_o ...... 100
4.4.39 P1588 Ingress_trig_time_o ...... 101
6 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver
6 August 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
4.4.76 SGMII Control Register 3 ........ 112
4.4.77 CLK_25M Clock Select ............ 112
4.4.78 1588 Clock Select ...................... 113
5 Package Dimensions .................115
6 Ordering Information ...............117
7 Topside Marking .......................117
4.4.40 P1588 Ingress_trig_time_o ...... 101
4.4.41 P1588 Tx_latency_o .................. 101
4.4.42 P1588 Inc_value_o .................... 102
4.4.43 P1588 Inc_value_o .................... 102
4.4.44 P1588 Nano_offset_o ................ 102
4.4.45 P1588 Nano_offset_o ................ 102
4.4.46 P1588 Sec_offset_o .................... 103
4.4.47 P1588 Sec_offset_o .................... 103
4.4.48 P1588 Sec_offset_o .................... 103
4.4.49 P1588 Real_time_i ..................... 103
4.4.50 P1588 Real_time_i ..................... 103
4.4.51 P1588 Real_time_i ..................... 104
4.4.52 P1588 Real_time_i ..................... 104
4.4.53 P1588 Real_time_i ..................... 104
4.4.54 P1588 Rtc_frac_nano_i ............. 104
4.4.55 P1588 Rtc_frac_nano_i ............. 105
4.4.56 Wake-on-LAN Internal Address 1
105
4.4.57 Wake-on-LAN Internal Address 2
105
4.4.58 Wake-on-LAN Internal Address 3
105
4.4.59 Rem_phy_lpbk .......................... 106
4.4.60 SmartEEE Control 1 .................. 106
4.4.61 SmartEEE Control 2 .................. 106
4.4.62 SmartEEE control 3 ................... 107
4.4.63 Auto-Negotiation Control 1 .... 107
4.4.64 Auto-Negotiation Status .......... 108
4.4.65 Auto-Negotiation XNP Transmit .
108
4.4.66 Auto-Negotiation XNP transmit1
108
4.4.67 Auto-Negotiation XNP Transmit2
109
4.4.68 Auto-Negotiation LP XNP Ability
109
4.4.69 Auto-Negotiation LP XNP Ability1
109
4.4.70 Auto-Negotiation LP XNP ability2
109
4.4.71 EEE Advertisement .................. 110
4.4.72 EEE LP advertisement .............. 110
4.4.73 EEE Ability Auto-negotiation
Result .......................................... 111
4.4.74 SGMII Control Register 1 ........ 111
4.4.75 SGMII Control Register 2 ........ 112
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver 7
August 2011 7
8 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver
8 August 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
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