UVM cookbook.pdf

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Testbench Architecture

Connections to DUT Interfaces

Configuring a Test Environment

Analysis Components & Techniques

End Of Test Mechanisms

Sequences

Testbench Acceleration throughCo-Emulation

Debug of SV and UVM

UVM Connect - SV-SystemC interoperability

UVM Express - step by step improvement

Appendix - Deployment

Appendix - Coding Guidelines

Appendix - Glossary of Terms

Verification Academy Cookbook Online Methodology Documentation from the Mentor Graphics Verification Methodology Team Contact VMDOC@mentor.com http://verificationacademy.com

Table of Contents Articles Introduction Cookbook/Introduction Cookbook/Acknowledgements Testbench Architecture Testbench Testbench/Build Testbench/Blocklevel Testbench/IntegrationLevel Component Agent Phasing Factory UsingFactoryOverrides SystemVerilogPackages Connections to DUT Interfaces Connections SVCreationOrder Connect/SystemVerilogTechniques ParameterizedTests Connect/Virtual Interface Config/VirtInterfaceConfigDb Connect/VirtInterfacePackage Connect/VirtInterfaceConfigPkg Connect/TwoKingdomsFactory DualTop VirtInterfaceFunctionCallChain BusFunctionalModels ProtocolModules Connect/AbstractConcrete 0 0 1 2 2 9 19 29 39 42 48 53 56 62 65 65 71 73 75 78 86 90 93 97 103 106 108 111 115

Connect/AbstractConcreteConfigDB Configuring a Test Environment Configuration Resources/config db Config/Params Package Config/ConfiguringSequences ResourceAccessForSequences MacroCostBenefit Analysis Components & Techniques Analysis AnalysisPort AnalysisConnections MonitorComponent Predictors Scoreboards MetricAnalyzers PostRunPhases Matlab/Integration End Of Test Mechanisms EndOfTest Objections Sequences Sequences Sequences/Items Transaction/Methods Sequences/API Connect/Sequencer Driver/Sequence API Sequences/Generation Sequences/Overrides Sequences/Virtual Sequences/VirtualSequencer 118 126 126 131 134 139 142 145 146 146 149 152 158 161 163 170 172 175 183 183 185 188 188 193 195 200 204 206 213 221 223 231

Sequences/Hierarchy Sequences/SequenceLibrary Driver/Use Models Driver/Unidirectional Driver/Bidirectional Driver/Pipelined Sequences/Arbitration Sequences/Priority Sequences/LockGrab Sequences/Slave Stimulus/Signal Wait Stimulus/Interrupts Sequences/Stopping Sequences/Layering Register Abstraction Layer Registers Registers/Specification Registers/Adapter Registers/Integrating Registers/Integration Registers/RegisterModelOverview Registers/ModelStructure Registers/QuirkyRegisters Registers/ModelCoverage Registers/BackdoorAccess Registers/Generation Registers/StimulusAbstraction Registers/MemoryStimulus Registers/SequenceExamples Registers/BuiltInSequences Registers/Configuration Registers/Scoreboarding Registers/FunctionalCoverage 237 242 246 247 250 255 267 276 277 284 290 294 301 302 308 308 315 317 321 327 332 334 344 349 354 357 358 370 375 382 386 389 395

Testbench Acceleration through Co-Emulation Emulation Emulation/SeparateTopLevels Emulation/SplitTransactors Emulation/BackPointers Emulation/DefiningAPI Emulation/Example Emulation/Example/APBDriver Emulation/Example/SPIAgent Emulation/Example/TopLevel Debug of SV and UVM BuiltInDebug Reporting/Verbosity UVM/CommandLineProcessor UVM Connect - SV-SystemC interoperability UvmConnect UvmConnect/Connections UvmConnect/Conversion UvmConnect/CommandAPI UVM Express - step by step improvement UvmExpress UvmExpress/DUT UvmExpress/BFM UvmExpress/WritingBfmTests UvmExpress/FunctionalCoverage UvmExpress/ConstrainedRandom Appendix - Deployment OVM2UVM OVM2UVM/DeprecatedCode OVM2UVM/SequenceLibrary OVM2UVM/Phasing 401 401 404 410 415 419 422 430 435 441 444 444 455 460 464 464 466 468 472 476 476 481 485 490 498 503 516 516 527 528 530

OVM2UVM/ConvertPhaseMethods UVC/UvmVerificationComponent Package/Organization Appendix - Coding Guidelines SV/Guidelines UVM/Guidelines Appendix - Glossary of Terms Doc/Glossary Datestamp: 535 537 548 555 555 569 579 579 - This document is a snapshot of dynamic content from the Online Methodology Cookbook - Created from http://verificationacademy.com/uvm-ovm on Wed, 04 Sep 2013 09:48:38 UTC

Introduction 0 Cookbook/Introduction Universal Verification Methodology (UVM) The Accellera UVM standard was built on the principle of cooperation between EDA vendors and customers; this was made possible by the strong foundation of knowledge and experience that was donated to the standardization effort in the form of the existing OVM code base and contributions from VMM. The result is a hybrid of technologies that originated in Mentor's AVM, Mentor & Cadence's OVM, Verisity's eRM, and Synopsys's VMM-RAL, tried and tested with our respective customers, along with several new technologies such as Resources, TLM2 and Phasing, all developed by Mentor and others to form UVM as we know it. Combined, these features provide a powerful, flexible technology and methodology to help you create scalable, reusable, and interoperable testbenches. With the OVM at its core, the UVM already embodies years of object-oriented design and methodology experience, all of which can be applied immediately to a UVM project. When we commenced work on UVM, Mentor set out to capture documentation of our existing OVM methodology at a fine level of granularity. In the process, we realized that learning a new library and methodology needed to be a dynamic and interactive experience, preferably consumed in small, easily digested spoonfuls. To reinforce each UVM and OVM concept or best practice, we developed many realistic, focused code examples. The end result is the UVM/OVM Online Methodology Cookbook, whose recipes can be adapted and applied in many different ways by our field experts, customers, and partners alike. The book you are holding contains excerpts from this online resource, covering many aspects of the UVM and OVM. Check out our UVM website to learn much more, and join others in finding out how you can leverage the UVM in your specific applications. Find us online at http:/ / verificationacademy. com/ cookbook''' UVM/OVM Documentation - Copyright (c) 2012 Mentor Graphics Corporation - http://verificationacademy.com/uvm-ovm

Cookbook/Acknowledgements 1 Cookbook/Acknowledgements UVM/OVM Cookbook Authors: • Gordon Allan • Mike Baird • Rich Edelman • Adam Erickson • Michael Horn • Mark Peryer • Adam Rose • Kurt Schwartz We acknowledge the valuable contributions of all our extended team of contributors and reviewers, and those who help deploy our methodology ideas to our customers, including: Alain Gonier, Allan Crone, Bahaa Osman, Dave Rich, Eric Horton, Gehan Mostafa, Graeme Jessiman, Hans van der Schoot, Hager Fathy, Jennifer Adams, John Carroll, John Amouroux, Jason Polychronopoulos, John Stickley, Nigel Elliot, Peet James, Ray Salemi, Shashi Bhutada, Tim Corcoran, and Tom Fitzpatrick. UVM/OVM Documentation - Copyright (c) 2012 Mentor Graphics Corporation - http://verificationacademy.com/uvm-ovm

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