KLMxGxxETx-B041(eMMC5.1 e·MMC).pdf

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Samsung eMMC Product family

1.0 PRODUCT LIST

2.0 KEY FEATURES

3.0 PACKAGE CONFIGURATIONS

3.1 153 Ball Pin Configuration

3.1.1 11.5mm x 13mm x 0.8mm Package Dimension [8GB /16GB]

3.1.2 11.5mm x 13mm x 0.8mm Package Dimension [32GB]

3.1.3 11.5mm x 13mm x 1.0mm Package Dimension [64GB]

3.2 Product Architecture

4.0 HS400 mode

5.0 New eMMC5.1 Features

5.1 Overview

5.2 Command Queuing

5.2.1 CMD Set Description

5.2.2 New Response : QSR (Queue Status Register)

5.2.3 Send Status : CMD13

5.2.4 Mechanism of CMD Queue operation

5.2.5 CMD Queue Register description

5.3 Enhanced Strobe Mode

5.4 RPMB Throughput improve

5.5 Secure Write Protection

6.0 Technical Notes

6.1 S/W Algorithm

6.1.1 Partition Management

6.1.1.1 Enhanced Partition (Area)

6.1.2 Boot operation

6.1.3 User Density

6.1.4 Auto Power Saving Mode

6.1.5 Performance

7.0 REGISTER VALUE

7.1 OCR Register

7.2 CID Register

7.2.1 Product name table (In CID Register)

7.3 CSD Register

7.4 Extended CSD Register

8.0 AC PARAMETER

8.1 Timing Parameter

8.2 Previous Bus Timing Parameters for DDR52 and HS200 mode are defined by JEDEC standard

8.3 Bus Timing Specification in HS400 mode

8.3.1 HS400 Device Input Timing

8.3.2 HS400 Device Output Timing

8.4 Bus signal levels

8.4.1 Open-drain mode bus signal level

8.4.2 Push-pull mode bus signal level eMMC

9.0 DC PARAMETER

9.1 Active Power Consumption during operation

9.2 Standby Power Consumption in auto power saving mode and standby state.

9.3 Sleep Power Consumption in Sleep State

9.4 Supply Voltage

9.5 Bus Signal Line Load

SAMSUNG CONFIDENTIAL Rev. 1.21 Jul. 2017 KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 Samsung eMMC Product family eMMC 5.1 Specification compatibility datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2017 Samsung Electronics Co., Ltd. All rights reserved - 1 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 Revision History datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC Revision No. History 0.0 1.0 1.1 1.2 1. Initial issue 1. Customer sample 1. 8GB is added (Customer sample) 1. Typo correction 1.21 1. Typo correction Draft Date Aug. 22, 2016 Nov. 15,2016 Dec. 12,2016 Jan. 26, 2017 Jul. 10, 2017 Remark Target Final Final Final Final Editor S.M.Lee S.M.Lee S.M.Lee S.M.Lee S.M.Lee IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 2 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 Table Of Contents datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC 1.0 PRODUCT LIST..........................................................................................................................................................4 2.0 KEY FEATURES.........................................................................................................................................................4 3.0 PACKAGE CONFIGURATIONS .................................................................................................................................5 3.1 153 Ball Pin Configuration ....................................................................................................................................... 5 3.1.1 11.5mm x 13mm x 0.8mm Package Dimension [8GB /16GB] .......................................................................... 6 3.1.2 11.5mm x 13mm x 0.8mm Package Dimension [32GB] ................................................................................... 6 3.1.3 11.5mm x 13mm x 1.0mm Package Dimension [64GB] ................................................................................... 7 3.2 Product Architecture ................................................................................................................................................ 8 4.0 HS400 mode...............................................................................................................................................................9 5.0 New eMMC5.1 Features .............................................................................................................................................10 5.1 Overview.................................................................................................................................................................. 10 5.2 Command Queuing ................................................................................................................................................. 10 5.2.1 CMD Set Description......................................................................................................................................... 10 5.2.2 New Response : QSR (Queue Status Register) .............................................................................................. 10 5.2.3 Send Status : CMD13 ...................................................................................................................................... 10 5.2.4 Mechanism of CMD Queue operation............................................................................................................... 11 5.2.5 CMD Queue Register description ..................................................................................................................... 11 5.3 Enhanced Strobe Mode........................................................................................................................................... 11 5.4 RPMB Throughput improve ..................................................................................................................................... 11 5.5 Secure Write Protection........................................................................................................................................... 12 6.0 Technical Notes ..........................................................................................................................................................13 6.1 S/W Algorithm.......................................................................................................................................................... 13 6.1.1 Partition Management ....................................................................................................................................... 13 6.1.1.1 Enhanced Partition (Area) .......................................................................................................................... 13 6.1.2 Boot operation................................................................................................................................................... 13 6.1.3 User Density...................................................................................................................................................... 14 6.1.4 Auto Power Saving Mode.................................................................................................................................. 15 6.1.5 Performance...................................................................................................................................................... 15 7.0 REGISTER VALUE.....................................................................................................................................................16 7.1 OCR Register .......................................................................................................................................................... 16 7.2 CID Register ............................................................................................................................................................ 16 7.2.1 Product name table (In CID Register) ............................................................................................................... 16 7.3 CSD Register........................................................................................................................................................... 17 7.4 Extended CSD Register .......................................................................................................................................... 18 8.0 AC PARAMETER........................................................................................................................................................23 8.1 Timing Parameter .................................................................................................................................................... 23 8.2 Previous Bus Timing Parameters for DDR52 and HS200 mode are defined by JEDEC standard.......................... 23 8.3 Bus Timing Specification in HS400 mode ............................................................................................................... 24 8.3.1 HS400 Device Input Timing .............................................................................................................................. 24 8.3.2 HS400 Device Output Timing............................................................................................................................ 25 8.4 Bus signal levels...................................................................................................................................................... 26 8.4.1 Open-drain mode bus signal level..................................................................................................................... 26 8.4.2 Push-pull mode bus signal level eMMC ............................................................................................................ 26 9.0 DC PARAMETER .......................................................................................................................................................27 9.1 Active Power Consumption during operation .......................................................................................................... 27 9.2 Standby Power Consumption in auto power saving mode and standby state......................................................... 27 9.3 Sleep Power Consumption in Sleep State............................................................................................................... 27 9.4 Supply Voltage ........................................................................................................................................................ 27 9.5 Bus Signal Line Load............................................................................................................................................... 28 IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 3 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 datasheet INTRODUCTION SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC SAMSUNG eMMC is an embedded MMC solution designed in a BGA package form. eMMC operation is identical to a MMC device and therefore is a sim- ple read and write to memory using MMC protocol v5.1 which is a industry standard. eMMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF or VCC) whereas 1.8V or 3V dual supply voltage (VDD or VCCQ) is supported for the MMC controller. SAMSUNG eMMC supports HS400 in order to improve sequential bandwidth, especially sequential read performance. There are several advantages of using eMMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host. Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to faster product development as well as faster times to market. The embedded flash management software or FTL(Flash Transition Layer) of eMMC manages Wear Leveling, Bad Block Management and ECC. The FTL supports all features of the Samsung NAND flash and achieves optimal performance. 1.0 PRODUCT LIST [Table 1] Product List Capacities eMMC Part ID 8 GB 16 GB 32 GB 64 GB KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 NAND Flash Type User Density (%) 64Gb x 1 128Gb x 1 128Gb x 2 128Gb x 4 91.0% 2.0 KEY FEATURES  embedded MultiMediaCard Ver. 5.1 compatible. Power System - Interface power : VDD (1.70V ~ 1.95V or 2.7V ~ 3.6V) - Memory power : VDDF (2.7V ~ 3.6V) Package size Pin Configuration 11.5mm x 13mm x 0.8mm 153FBGA 11.5mm x 13mm x 1.0mm  SAMSUNG eMMC supports features of eMMC5.1 which are defined in JEDEC Standard - Major Supported Features : HS400, Field Firmware Update, Cache, Command Queuing, Enhanced Strobe Mode,  Secure Write Protection, Partition types. - Non-supported Features : Large Sector Size (4KB)  Backward compatibility with previous MultiMediaCard system specification (1bit data bus, multi-eMMC systems)  Data bus width : 1bit (Default), 4bit and 8bit  MMC I/F Clock Frequency : 0 ~ 200MHz MMC I/F Boot Frequency : 0 ~ 52MHz  Temperature : Operation (-25C ~ 85C), Storage without operation (-40C ~ 85C)  Power : Interface power → VCCQ(1.70V ~ 1.95V) , Memory power → VCC (2.7V ~ 3.6V) IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 4 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC 3.0 PACKAGE CONFIGURATIONS 3.1 153 Ball Pin Configuration [Table 2] 153 Ball Information Ball-side down view NC 1 2 3 DAT0 4 DAT1 5 DAT2 6 Vss 7 RFU 8 9 10 11 12 13 14 DAT3 DAT4 DAT5 DAT6 DAT7 VDDI Vss VDD RFU VDDF Vss RFU RFU RFU RFU VDDF Vss Data Strobe Vss RFU RFU Vss VDDF RSTN RFU RFU Vss VDDF RFU VDD CMD CLK Vss VDD Vss VDD Vss VDD Vss RFU RFU A B C D E F G H J K L M N P Pin NO A3 A4 A5 B2 B3 B4 B5 B6 K5 C6 M4 N4 P3 P5 E6 F5 J10 K9 C2 M5 H5 M6 J5 A6 C4 E7 G5 H10 K8 N2 N5 P4 P6 Name DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 RSTN VCCQ VCCQ VCCQ VCCQ VCCQ VCC VCC VCC VCC VDDI CMD Data Strobe CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Figure 1. 153-FBGA  CLK : Clock input  Data Strobe : Data Strobe is generated from eMMC to host. In HS400 mode, read data and CRC response are synchronized with Data Strobe.  CMD : A bidirectional signal used for device initialization and command transfers. Command operates in two modes, open-drain for initialization and push-pull for fast command transfer.  DAT0-7 : Bidirectional data channels. It operates in push-pull mode.  RST_n : H/W reset signal pin  VCC : Supply voltage for flash memory  VCCQ : Supply voltage for memory controller  VDDi : Internal power node to stabilize regulator output to controller core logics  VSS : Ground connections  RFU : Reserved for future use , do not use for any usage IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 5 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC 3.1.1 11.5mm x 13mm x 0.8mm Package Dimension [8GB /16GB] 11.50±0.10 0.08 MAX 11.50±0.10 0.50 x 13 = 6.50 11 4 7 6 5 89 14 1312 10 #A1 INDEX MARK A B 3 2 1 #A1 (Datum A) . 0 1 0 ± 0 0 3 1 . . 0 1 0 ± 0 0 3 1 . (Datum B) 5 2 3 . A B C D E F G H J K L M N P 0.15 M A B 153-0.30±0.05  0.21±0.05 0.70±0.10 0 5 . 0 . 0 5 6 = 3 1 x 0 5 . . 0 1 0 ± 0 0 3 1 . 0 3.25 0.50 BOTTOM VIEW TOP VIEW 3.1.2 11.5mm x 13mm x 0.8mm Package Dimension [32GB] Figure 2. 11.5mm x 13mm x 0.8mm Package Dimension 11.50±0.10 11.50±0.10 0.08 MAX 0.50 x 13 = 6.50 11 4 7 6 5 89 14 1312 10 #A1 INDEX MARK A B 3 2 1 . 0 5 6 = 3 1 x 0 5 . 0 . 0 1 0 ± 0 0 . 3 1 #A1 (Datum A) . 0 1 0 ± 0 0 . 3 1 . 0 1 0 ± 0 0 . 3 1 (Datum B) 5 2 . 3 A B C D E F G H J K L M N P 0.15 M A B 153-0.30±0.05  0.21±0.05 0.72±0.08 0 5 . 0 3.25 0.50 BOTTOM VIEW TOP VIEW Figure 3. 11.5mm x 13mm x 0.8mm Package Dimension IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 6 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC 3.1.3 11.5mm x 13mm x 1.0mm Package Dimension [64GB] 11.50±0.10 0.08 MAX 11.50±0.10 0.50 x 13 = 6.50 11 4 7 6 5 89 14 1312 10 #A1 INDEX MARK A B 3 2 1 #A1 (Datum A) . 0 1 0 ± 0 0 3 1 . . 0 1 0 ± 0 0 3 1 . (Datum B) 5 2 3 . A B C D E F G H J K L M N P 0.15 M A B 153-0.30±0.05  0.21±0.05 0.92±0.08 TOP VIEW 0 5 . 0 . 0 5 6 = 3 1 x 0 5 . . 0 1 0 ± 0 0 3 1 . 0 3.25 0.50 BOTTOM VIEW Figure 4. 11.5mm x 13mm x 1.0mm Package Dimension IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 7 -

KLM8G1GETF-B041 KLMAG1JETD-B041 KLMBG2JETD-B041 KLMCG4JETD-B041 datasheet SAMSUNG CONFIDENTIAL Rev. 1.21 eMMC 3.2 Product Architecture - eMMC consists of NAND Flash and Controller. VCCQ is for Controller power and VCC is for flash power VCC VCCQ RESET CReg Data Strobe CLK CMD DAT[7:0] l k c o B O / I C M M Control Signal Data Bus Memory l k c o B O / I D N A N Core Regulator VDDi Core Logic Block MMC Controller Figure 5. eMMC Block Diagram IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. - 8 -

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