Xilinx系列FPGA板间高速通信实现.pdf

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Using FPGAs to Design Gigabit Serial Backplanes April 17, 2002

Outline •System Design Trends •Serial Backplanes Architectures •Building Serial Backplanes with FPGAs A1 - 2

Key System Design Trends •Need for …. –Easy Scalability of Performance –Extremely High Availability –Flexible Architecture –Use of Standards • Rapid Time to Market • Reduces Costs A1 - 3

Merging Communications & Computers • Communications Systems have serial backplanes • Computers moving to serial backplanes Database servers Application servers 1U Web servers Ethernet Switches “Bladed Server”, PICMG 2.16 Internet A1 - 4

Serial Standards • Serial Standards – Fiber Channel 1 Gbps – Ethernet 1 Gbps – InfiniBand 2.5 Gbps • Parallel Standards Going Serial – PCI => 3GIO – RapidIO => Serial RapidIO – ATA => Serial ATA • Channel Bonded Serial Standards – XAUI 10 Gigabit Ethernet (4 x 3.125 Gbps) 3GIO 3GIO A1 - 5

Serial Connectivity = Higher Bandwidth & Fewer Pins 2 3 4 5 1 50 Example - PCI: 32-bit x 33MHz = 1 Gbps, Shared among 5 clients 250 total pins 1 2 3 4 5 4 Virtex-II Pro System: 2.5 Gbps x 4 x 5 = 50 Gbps 80 total pins Each Client has 2.5 Gbps guaranteed to every other Client 50x higher bandwidth with less than 1/3 of the pins RJG A1 - 6

Serial Link Rates •OC-768 •OC-192 •10GE •FC-10x •SxI-5 •3GIO •Infiniband •Rapid IO •OC-48 •GigE •FC-2x •FC •OC-12 2000 2002 2004 Mainstream Deployment 2006 A1 - 7 40G 10G 3.125G 1.25G 622M ) . c e s r e p s t i b ( s e t a R k n L i 155M •OC-3 1998

Serial Topologies Switched Full Mesh PICMG 2.16 PICMG 2.2 PICMG 3.x A1 - 8

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Xilinx系列FPGA板间高速通信实现.pdf

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