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PSpice for Circuit Theory and Electronic Devices-Paul Tobin[清晰原版....pdf
Cover
Title Page
Copyright Page
Contents
Preface
CHAPTER 1: Semiconductor Diodes
1.1 Introduction
1.2 Semiconductor Materials: Ge, Si, and GaAs
1.3 Covalent Bonding and Intrinsic Materials
1.4 Energy Levels
1.5 n-Type and p-Type Materials
1.6 Semiconductor Diode
1.7 Ideal Versus Practical
1.8 Resistance Levels
1.9 Diode Equivalent Circuits
1.10 Transition and Diffusion Capacitance
1.11 Reverse Recovery Time
1.12 Diode Specification Sheets
1.13 Semiconductor Diode Notation
1.14 Diode Testing
1.15 Zener Diodes
1.16 Light-Emitting Diodes
1.17 Summary
1.18 Computer Analysis
CHAPTER 2: Diode Applications
2.1 Introduction
2.2 Load-Line Analysis
2.3 Series Diode Configurations
2.4 Parallel and Series–Parallel Configurations
2.5 AND/OR Gates
2.6 Sinusoidal Inputs; Half-Wave Rectification
2.7 Full-Wave Rectification
2.8 Clippers
2.9 Clampers
2.10 Networks with a dc and ac Source
2.11 Zener Diodes
2.12 Voltage-Multiplier Circuits
2.13 Practical Applications
2.14 Summary
2.15 Computer Analysis
CHAPTER 3: Bipolar Junction Transistors
3.1 Introduction
3.2 Transistor Construction
3.3 Transistor Operation
3.4 Common-Base Configuration
3.5 Common-Emitter Configuration
3.6 Common-Collector Configuration
3.7 Limits of Operation
3.8 Transistor Specification Sheet
3.9 Transistor Testing
3.10 Transistor Casing and Terminal Identification
3.11 Transistor Development
3.12 Summary
3.13 Computer Analysis
CHAPTER 4: DC Biasing—BJTs
4.1 Introduction
4.2 Operating Point
4.3 Fixed-Bias Configuration
4.4 Emitter-Bias Configuration
4.5 Voltage-Divider Bias Configuration
4.6 Collector Feedback Configuration
4.7 Emitter-Follower Configuration
4.8 Common-Base Configuration
4.9 Miscellaneous Bias Configurations
4.10 Summary Table
4.11 Design Operations
4.12 Multiple BJT Networks
4.13 Current Mirrors
4.14 Current Source Circuits
4.15 pnp Transistors
4.16 Transistor Switching Networks
4.17 Troubleshooting Techniques
4.18 Bias Stabilization
4.19 Practical Applications
4.20 Summary
4.21 Computer Analysis
CHAPTER 5: BJT AC Analysis
5.1 Introduction
5.2 Amplification in the AC Domain
5.3 BJT Transistor Modeling
5.4 The r[sub(e)] Transistor Model
5.5 Common-Emitter Fixed-Bias Configuration
5.6 Voltage-Divider Bias
5.7 CE Emitter-Bias Configuration
5.8 Emitter-Follower Configuration
5.9 Common-Base Configuration
5.10 Collector Feedback Configuration
5.11 Collector DC Feedback Configuration
5.12 Effect of R[sub(L)] and R[sub(s)]
5.13 Determining the Current Gain
5.14 Summary Tables
5.15 Two-Port Systems Approach
5.16 Cascaded Systems
5.17 Darlington Connection
5.18 Feedback Pair
5.19 The Hybrid Equivalent Model
5.20 Approximate Hybrid Equivalent Circuit
5.21 Complete Hybrid Equivalent Model
5.22 Hybrid π Model
5.23 Variations of Transistor Parameters
5.24 Troubleshooting
5.25 Practical Applications
5.26 Summary
5.27 Computer Analysis
CHAPTER 6: Field-Effect Transistors
6.1 Introduction
6.2 Construction and Characteristics of JFETs
6.3 Transfer Characteristics
6.4 Specification Sheets (JFETs)
6.5 Instrumentation
6.6 Important Relationships
6.7 Depletion-Type MOSFET
6.8 Enhancement-Type MOSFET
6.9 MOSFET Handling
6.10 VMOS and UMOS Power and MOSFETs
6.11 CMOS
6.12 MESFETs
6.13 Summary Table
6.14 Summary
6.15 Computer Analysis
CHAPTER 7: FET Biasing
7.1 Introduction
7.2 Fixed-Bias Configuration
7.3 Self-Bias Configuration
7.4 Voltage-Divider Biasing
7.5 Common-Gate Configuration
7.6 Special Case V[Sub(GS)][Sub(Q)] = 0 V
7.7 Depletion-Type MOSFETs
7.8 Enhancement-Type MOSFETs
7.9 Summary Table
7.10 Combination Networks
7.11 Design
7.12 Troubleshooting
7.13 p-Channel FETs
7.14 Universal JFET Bias Curve
7.15 Practical Applications
7.16 Summary
7.17 Computer Analysis
CHAPTER 8: FET Amplifiers
8.1 Introduction
8.2 JFET Small-Signal Model
8.3 Fixed-Bias Configuration
8.4 Self-Bias Configuration
8.5 Voltage-Divider Configuration
8.6 Common-Gate Configuration
8.7 Source-Follower (Common-Drain) Configuration
8.8 Depletion-Type MOSFETs
8.9 Enhancement-Type MOSFETs
8.10 E-MOSFET Drain-Feedback Configuration
8.11 E-MOSFET Voltage-Divider Configuration
8.12 Designing FET Amplifier Networks
8.13 Summary Table
8.14 Effect of R[sub(L)] and R[sub(sig)]
8.15 Cascade Configuration
8.16 Troubleshooting
8.17 Practical Applications
8.18 Summary
8.19 Computer Analysis
CHAPTER 9: BJT and JFET Frequency Response
9.1 Introduction
9.2 Logarithms
9.3 Decibels
9.4 General Frequency Considerations
9.5 Normalization Process
9.6 Low-Frequency Analysis—Bode Plot
9.7 Low-Frequency Response—BJT Amplifier with R[sub(L)]
9.8 Impact of R[sub(s)] on the BJT Low-Frequency Response
9.9 Low-Frequency Response—FET Amplifier
9.10 Miller Effect Capacitance
9.11 High-Frequency Response—BJT Amplifier
9.12 High-Frequency Response—FET Amplifier
9.13 Multistage Frequency Effects
9.14 Square-Wave Testing
9.15 Summary
9.16 Computer Analysis
CHAPTER 10: Operational Amplifiers
10.1 Introduction
10.2 Differential Amplifier Circuit
10.3 BiFET, BiMOS, and CMOS Differential Amplifier Circuits
10.4 Op-Amp Basics
10.5 Practical Op-Amp Circuits
10.6 Op-Amp Specifications—DC Offset Parameters
10.7 Op-Amp Specifications—Frequency Parameters
10.8 Op-Amp Unit Specifications
10.9 Differential and Common-Mode Operation
10.10 Summary
10.11 Computer Analysis
CHAPTER 11: Op-Amp Applications
11.1 Constant-Gain Multiplier
11.2 Voltage Summing
11.3 Voltage Buffer
11.4 Controlled Sources
11.5 Instrumentation Circuits
11.6 Active Filters
11.7 Summary
11.8 Computer Analysis
CHAPTER 12: Power Amplifiers
12.1 Introduction—Definitions and Amplifier Types
12.2 Series-Fed Class A Amplifier
12.3 Transformer-Coupled Class A Amplifier
12.4 Class B Amplifier Operation
12.5 Class B Amplifier Circuits
12.6 Amplifier Distortion
12.7 Power Transistor Heat Sinking
12.8 Class C and Class D Amplifiers
12.9 Summary
12.10 Computer Analysis
CHAPTER 13: Linear-Digital ICs
13.1 Introduction
13.2 Comparator Unit Operation
13.3 Digital–Analog Converters
13.4 Timer IC Unit Operation
13.5 Voltage-Controlled Oscillator
13.6 Phase-Locked Loop
13.7 Interfacing Circuitry
13.8 Summary
13.9 Computer Analysis
CHAPTER 14: Feedback and Oscillator Circuits
14.1 Feedback Concepts
14.2 Feedback Connection Types
14.3 Practical Feedback Circuits
14.4 Feedback Amplifier—Phase and Frequency Considerations
14.5 Oscillator Operation
14.6 Phase-Shift Oscillator
14.7 Wien Bridge Oscillator
14.8 Tuned Oscillator Circuit
14.9 Crystal Oscillator
14.10 Unijunction Oscillator
14.11 Summary
14.12 Computer Analysis
CHAPTER 15: Power Supplies (Voltage Regulators)
15.1 Introduction
15.2 General Filter Considerations
15.3 Capacitor Filter
15.4 RC Filter
15.5 Discrete Transistor Voltage Regulation
15.6 IC Voltage Regulators
15.7 Practical Applications
15.8 Summary
15.9 Computer Analysis
CHAPTER 16: Other Two-Terminal Devices
16.1 Introduction
16.2 Schottky Barrier (Hot-Carrier) Diodes
16.3 Varactor (Varicap) Diodes
16.4 Solar Cells
16.5 Photodiodes
16.6 Photoconductive Cells
16.7 IR Emitters
16.8 Liquid-Crystal Displays
16.9 Thermistors
16.10 Tunnel Diodes
16.11 Summary
CHAPTER 17: pnpn and Other Devices
17.1 Introduction
17.2 Silicon-Controlled Rectifier
17.3 Basic Silicon-Controlled Rectifier Operation
17.4 SCR Characteristics and Ratings
17.5 SCR Applications
17.6 Silicon-Controlled Switch
17.7 Gate Turn-Off Switch
17.8 Light-Activated SCR
17.9 Shockley Diode
17.10 Diac
17.11 Triac
17.12 Unijunction Transistor
17.13 Phototransistors
17.14 Opto-Isolators
17.15 Programmable Unijunction Transistor
17.16 Summary
Appendix A: Hybrid Parameters—Graphical Determinations and Conversion Equations (Exact and Approximate)
A.1 Graphical Determination of the h-Parameters
A.2 Exact Conversion Equations
A.3 Approximate Conversion Equations
Appendix B: Ripple Factor and Voltage Calculations
B.1 Ripple Factor of Rectifier
B.2 Ripple Voltage of Capacitor Filter
B.3 Relation of V[sub(dc)] and V[sub(m)] to Ripple r
B.4 Relation of V[sub(r)](rms) and V[sub(m)] to Ripple r
B.5 Relation Connecting Conduction Angle, Percentage Ripple, and I[sub(peak)] /I[sub(dc)] for Rectifier-Capacitor Filter Circuits
Appendix C: Charts and Tables
Appendix D: Solutions to Selected Odd-Numbered Problems
Index
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
Z
SIGNIFICANT EQUATIONS
Semiconductor Diodes
1
k = 1.38 * 10
PD = VD ID, TC = (⌬VZ >VZ)>(T1 - T0) * 100%>⬚C
W = QV, 1 eV = 1.6 * 10
-23 J/K, VK ⬵ 0.7 V (Si), VK ⬵ 0.3 V(Ge), VK ⬵ 1.2 V (GaAs), RD = VD>ID, rd = 26 mV>ID, rav = ⌬Vd>⌬Id 兩 pt. to pt.,
-19 J, ID = Is (eVD>nVT - 1), VT = kT>q, TK = TC + 273⬚,
Diode Applications
2
full-wave: Vdc = 0.636Vm
Silicon: VK ⬵ 0.7 V, germanium: VK ⬵ 0.3 V, GaAs: VK ⬵ 1.2 V; half-wave: Vdc = 0.318Vm;
Bipolar Junction Transistors
3
aac = ⌬IC>⌬IE, ICEO = ICBO>(1 - a), bdc = IC>IB, bac = ⌬IC>⌬IB, a = b>(b + 1), b = a>(1 - a), IC = bIB, IE = (b + 1)IB,
PCmax
+ ICOminority, IC ⬵ IE, VBE = 0.7 V, adc = IC>IE, IC = aIE + ICBO,
IE = IC + IB, IC = ICmajority
= VCEIC
In general: VBE = 0.7 V, IC ⬵ IE, IC = bIB; fixed-bias: IB = (VCC - VBE)>RB,VCE = VCC - ICRC,
DC Biasing—BJTs
= VCC>RC; emitter-stabilized: IB = (VCC - VBE)>(RB + (b + 1)RE), Ri = (b + 1)RE, VCE = VCC - IC(RC + RE),
= VCC>(RC + RE); voltage-divider: exact: RTh = R1 储 R2, ETh = R2VCC>(R1 + R2), IB = (ETh - VBE)>(RTh + (b + 1)RE),
4
ICsat
ICsat
VCE = VCC - IC(RC + RE), approximate: bRE Ú 10R2, VB = R2VCC>(R1 + R2), VE = VB - VBE, IC ⬵ IE = VE>RE; voltage-feedback:
IB = (VCC - VBE)>(RB + b(RC + RE)); common-base: IB = (VEE - VBE)>RE; switching transistors: ton = tr + td, toff = ts + tf;
stability: S(ICO) = ⌬IC>⌬ICO; fixed-bias: S(ICO) = b + 1; emitter-bias: S(ICO) = (b + 1)(1 + RB>RE)>(1 + b + RB>RE);
voltage-divider: S(ICO) = (b + 1)(1 + RTh>RE)>(1 + b + RTh>RE); feedback-bias: S(ICO) = (b + 1)(1 + RB>RC)>(1 + b + RB>RC),
S(VBE) = ⌬IC>⌬VBE; fixed-bias: S(VBE) = - b>RB; emitter-bias: S(VBE) = - b>(RB + (b + 1)RE); voltage-divider: S(VBE) =
- b>(RTh + (b + 1)RE); feedback bias: S(VBE) = - b>(RB + (b + 1)RC), S(b) = ⌬IC>⌬b; fixed-bias: S(b) = IC1
emitter-bias: S(b) = IC1(1 + RB>RE)> (b1(1 + b2 + RB>RE)); voltage-divider: S(b) = IC1(1 + RTh>RE)>(b1(1 + b2 + RTh>RE));
feedback-bias: S(b) = IC1(1 + RB>RC)>(b1(1 + b2 + RB>RC)), ⌬IC = S(ICO) ⌬ICO + S(VBE) ⌬VBE + S(b) ⌬b
>b1;
BJT AC Analysis
re = 26 mV>IE; CE fixed-bias: Zi ⬵ bre, Zo ⬵ RC, Av = -RC>re; voltage-divider bias: Zi = R1 储 R2 储 bre, Zo ⬵ RC,
5
Av = -RC>re; CE emitter-bias: Zi ⬵ RB 储 bRE, Zo ⬵ RC, Av ⬵ -RC>RE; emitter-follower: Zi ⬵ RB 储 bRE, Zo ⬵ re, Av ⬵ 1;
common-base: Zi ⬵ RE 储 re, Zo ⬵ RC, Av ⬵ RC>re; collector feedback: Zi ⬵ re>(1>b + RC>RF), Zo ⬵ RC 储 RF, Av = -RC>re; collector
>(RL + Ro), Ai = -Av Zi>RL;
dc feedback: Zi ⬵ RF1
effect of source impedance: Vi = RiVs>(Ri + Rs), Avs
impedance: Av = RLAvNL
connection: Av = Av1Av2; Darlington connection: bD = b1b2; emitter-follower configuration: IB = (VCC - VBE)>(RB + bDRE),
IC ⬵ IE ⬵ bDIB, Zi = RB 储 b1b2RE, Ai = bDRB>(RB + bDRE), Av ⬵ 1, Zo = re1
Zi⬘ = b1(re1
Zi = RB 储 Zi⬘, Zi⬘ = b1re1
>(Ri + Rs), Is = Vs>(Rs + Ri); combined effect of load and source
= -Avs(Rs + Ri)>RL; cascode
+ b2re2), Ai = bD(R1 储 R2)>(R1 储 R2 + Zi⬘), Av = bDRC>Zi⬘, Zo = RC 储 ro2; feedback pair: IB1
储 bre, Zo ⬵ RC 储 RF2, Av = -(RF2
>(RL + Ro), Avs
+ b1b2RC, Ai = - b1b2RB>(RB + b1b2RC) Av = b2RC>(re + b2RC) ⬵ 1, Zo ⬵ re1
>b2 + re2; basic amplifier configuration: Zi = R1 储 R2 储 Zi⬘,
= (VCC - VBE1)>(RB + b1b2RC),
= (Ri>(Ri + Rs))(RL>(RL + Ro))AvNL, Ai = -Av Ri>RL, Ais
储 RC)>re; effect of load impedance: Av = RLAvNL
= RiAvNL
>b2 .
Field-Effect Transistors
6
ID = IDSS>2 (if VGS ⬵ 0.3 VP), PD = VDSID, rd = ro>(1 - VGS>VP)2; MOSFET: ID = k(VGS - VT)2, k = ID(on) >(VGS(on) - VT)2
IG = 0 A, ID = IDSS(1 - VGS>VP)2, ID = IS , VGS = VP (1 - 2ID>IDSS), ID = IDSS>4 (if VGS = VP>2),
FET Biasing
Fixed-bias: VGS = -VGG, VDS = VDD - IDRD; self-bias: VGS = -IDRS, VDS = VDD - ID(RS + RD), VS = IDRS;
7
voltage-divider: VG = R2VDD>(R1 + R2), VGS = VG - ID RS, VDS = VDD - ID(RD + RS); common-gate configuration: VGS = VSS - IDRS,
VDS = VDD + VSS - ID(RD + RS); special case: VGSQ
= IDSS, VDS = VDD - IDRD, VD = VDS, VS = 0 V. enhancement-type
MOSFET: ID = k(VGS - VGS(Th))2, k = ID(on)>(VGS(on) - VGS(Th))2; feedback bias: VDS = VGS, VGS = VDD - IDRD; voltage-divider:
VG = R2VDD>(R1 + R2), VGS = VG - IDRS; universal curve: m = 0VP 0 >IDSSRS, M = m * VG> 0VP 0 , VG = R2VDD>(R1 + R2)
= 0 V: IIQ
FET Amplifiers
gm = yfs = ⌬ID>⌬VGS, gm0 = 2IDSS >兩VP兩, gm = gm0(1 - VGS>VP), gm = gm0 1ID>IDSS, rd = 1>yos =
8
⌬VDS>⌬ID 0 VGS= constant; fixed-bias: Zi = RG, Zo ⬵ RD, Av = -gmRD; self-bias (bypassed R s ): Zi = RG, Zo ⬵ RD, Av = -gmRD; self-bias
(unbypassed R s ): Zi = RG, Zo = RD, Av ⬵ -gmRD>(1 + gmRs); voltage-divider bias: Zi = R1 储 R2, Zo = RD, Av = -gmRD; source follower:
Zi = RG, Zo = RS 储 1>gm, Av ⬵ gmRS>(1 + gmRS); common-gate: Zi = RS 储 1>gm, Zo ⬵ RD, Av = gmRD; enhancement-type MOSFETs:
- VGS(Th)); drain-feedback configuration: Zi ⬵ RF>(1 + gmRD), Zo ⬵ RD, Av ⬵ -gmRD; voltage-divider bias: Zi = R1 储 R2 ,
gm = 2k(VGSQ
Zo ⬵ RD, Av ⬵ -gmRD.
+ GdB2
+ g+ GdBn PoHPF
BJT and JFET Frequency Response
= 0.5Pomid, BW = f1 - f2; low frequency (BJT): fLS
= GdB1
= 1>2p(Ro + RL)CC, fLE = 1>2pReCE, Re = RE 储 (R⬘s>b + re), R⬘s = Rs 储 R1 储 R2, FET: fLG
= 1>2p(Ro + RL)CC , fLS
9
log10ab = log10 a + log10 b, GdB = 10 log10 P2>P1, GdBm = 10 log10 P2>1 mW兩600 ⍀, GdB = 20 log10 V2>V1,
GdBT
fLC
fLC
high frequency (BJT): fHi
RTho
Ci = CWi
multistage: f ⬘1 = f1> 221>n - 1, f ⬘2 = (221>n - 1)f2; square-wave testing: fHi
fLo
+ Cbe + (1 - Av)Cbc, fHo
+ Cce + CMo, fb ⬵ 1>2pbmidre(Cbe + Cbc), fT = bmid fb; FET: fHi
= (1 - Av)Cgd fHo
= 1>2pReqCS, Req = RS 储 1>gm(rd ⬵ ⬁ ⍀); Miller effect: CMi
= RC 储 RL 储 ro, Co = CWo
+ Cgs + CMi, CMi
= Rs 储 R1 储 R2 储 Ri, Ci = Cwi
= RD 储 RL 储 rd, Co = CWo
= 1>2pRThoCo, RTho
= 1>2pRThiCi, RThi
= (P>p)fs
= 1>2p(Rs + Ri)Cs,
= 1>2p(Rsig + Ri)CG,
= (1 - Av)Cf, CMo
= (1 - 1>Av)Cf;
logea = 2.3 log10a, log101 = 0, log10 a>b = log10a - log10b, log101>b = -log10b,
= 1>2pRThoCo,
= 1>2pRThiCi, RThi
+ Cds + CMo; CMO
= Rsig 储 RG,
= (1 - 1>Av)Cgd ;
= 0.35>tr, % tilt = P% = ((V - V⬘)>V ) * 100%,
Operational Amplifiers
10
noninverting amplifier: Vo>V1 = 1 + Rf >R1; unity follower: Vo = V1; summing amplifier: Vo = -[(Rf>R1)V1 + (Rf>R2)V2 + (Rf>R3)V3];
integrator: vo(t) = -(1>R1C1) 1v1dt
CMRR = Ad>Ac; CMRR(log) = 20 log10(Ad>Ac); constant-gain multiplier: Vo>V1 = -Rf >R1;
Op-Amp Applications
11
Vo = -[(Rf>R1)V1 + (Rf>R2)V2 + (Rf>R3)V3]; high-pass active filter: foL = 1>2pR1C1; low-pass active filter: foH = 1>2pR1C1
Constant-gain multiplier: A = - Rf>R1; noninverting: A = 1 + Rf>R1: voltage summing:
CE>RC rms
CRC = V 2
C>2)RC = V 2
C>8)RC = V 2
Power Amplifiers
Pi = VCCICQ
= VCEIC>2 = (I 2
= VCEIC>8 = (I 2
CE>(2RC) peak
CE>(8RC) peak@to@peak
12
Power in:
power out: Po = VCEIC = I 2
effi ciency: %h = (Po>Pi) * 100%; maximum effi ciency: Class A, series-fed ⫽ 25%; Class A, transformer-coupled ⫽ 50%; Class B,
push-pull ⫽ 78.5%; transformer relations: V2>V1 = N2>N1 = I1>I2, R2 = (N2>N1)2R1; power output: Po = [(VCE max
(IC max
PQ = P2Q>2 = (Pi - Po)>2; maximum Po = V 2
distortion (% THD) = 2D2
PD = (TJ - TA)>(uJC + uCS + uSA)
- IC min )]>8; class B power amplifi er: Pi = VCC3(2>p)Ipeak4; Po = V 2
CC>2RL; maximum Pi = 2V 2
L(peak)>(2RL); %h = (p>4)3VL(peak)>VCC4 * 100%;
CC>pRL; maximum P2Q = 2V 2
CC>p2RL; % total harmonic
4 + g * 100%; heat-sink: TJ = PDuJA + TA, uJA = 40⬚C/W (free air);
- VCE min )
2 + D2
3 + D2
Linear-Digital ICs
13
555 oscillator: f = 1.44(RA + 2RB)C; 555 monostable: Thigh = 1.1RAC; VCO: fo = (2>R1C1)[(V
locked loop (PLL): fo = 0.3>R1C1, fL = {8 fo>V, fC = {(1>2p)22pfL >(3.6 * 103)C2
Ladder network: Vo = [(D0 * 20 + D1 * 21 + D2 * 22 + g + Dn * 2n)>2n]Vref;
+ - VC)>V
+
]; phase-
Feedback and Oscillator Circuits
Af = A>(1 + bA); series feedback; Zif = Zi(1 + bA); shunt feedback: Zif = Zi>(1 + bA);
14
voltage feedback: Zof = Zo>(1 + bA); current feedback; Zof = Zo(1 + bA); gain stability: dAf>Af = 1>(兩1 + bA兩)(dA>A); oscillator;
bA = 1; phase shift: f = 1>2pRC16, b = 1>29, A 7 29; FET phase shift: 兩A兩 = gmRL, RL = RDrd>(RD + rd); transistor phase shift:
f = (1>2pRC)[1> 26 + 4(RC>R)], hfe 7 23 + 29(RC>R) + 4(R>RC); Wien bridge: R3>R4 = R1>R2 + C2>C1, fo = 1>2p1R1C1R2C2;
tuned: fo = 1>2p 1LCeq, Ceq = C1C2>(C1 + C2), Hartley: Leq = L1 + L2 + 2M, fo = 1>2p 1LeqC
Power Supplies (Voltage Regulators)
Filters: r = Vr(rms)>Vdc * 100%, V.R. = (VNL - VFL)>VFL * 100%, Vdc = Vm - Vr(p@p)>2,
15
Vr(rms) = Vr(p@p)>213, Vr(rms) ⬵ (Idc>413)(Vdc>Vm); full-wave, light load Vr(rms) = 2.4Idc>C, Vdc = Vm - 4.17Idc>C, r =
(2.4IdcCVdc) * 100% = 2.4>RLC * 100%, Ipeak = T>T1 * Idc; RC filter: V⬘dc = RL Vdc> (R + RL), XC = 2.653>C(half@wave), XC =
1.326>C (full@wave), V⬘r(rms) = (XC> 2R2 + X2
Vref(1 + R2>R1) + IadjR2
C); regulators: IR = (INL - IFL)>IFL * 100%, VL = VZ(1 + R1>R2), Vo =
Other Two-Terminal Devices
16
W = hf, l = v>f, 1 lm = 1.496 * 10
Varactor diode: CT = C(0)>(1 + 兩Vr>VT 兩)n, TCC
-10 W, 1 Å = 10
-10 m, 1 fc = 1 lm>ft2 = 1.609 * 10
-9 W>m2
= (⌬C>Co(T1 - T0)) * 100%; photodiode:
17
h = RB1
pnpn and Other Devices
>(RB1
+ RB2)兩 IE = 0 , VP = hVBB + VD; phototransistor: IC ⬵ hfeIl; PUT: h = RB1
>(RB1
+ RB2),VP = hVBB + VD
Diac: VBR1
= VBR2
{ 0.1 VBR2 UJT: RBB = (RB1
+ RB2)兩 IE = 0, VRB1
= hVBB兩IE = 0,
Electronic
Devices and
Circuit Theory
Eleventh Edition
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Library of Congress Cataloging-in-Publication Data
Boylestad, Robert L.
Electronic devices and circuit theory / Robert L. Boylestad, Louis Nashelsky.—11th ed.
p. cm.
ISBN 978-0-13-262226-4
1. Electronic circuits. 2. Electronic apparatus and appliances.
TK7867.B66 2013
621.3815—dc23
I. Nashelsky, Louis.
II. Title.
10 9 8 7 6 5 4 3 2 1
2011052885
ISBN 10: 0-13-262226-2
ISBN 13: 978-0-13-262226-4
DEDICATION
To Else Marie, Alison and Mark, Eric and Rachel, Stacey and Jonathan,
and our eight granddaughters: Kelcy, Morgan, Codie, Samantha, Lindsey,
Britt, Skylar, and Aspen.
To Katrin, Kira and Thomas, Larren and Patricia, and our six grandsons:
Justin, Brendan, Owen, Tyler, Colin, and Dillon.
This page intentionally left blank
PREFACE
The preparation of the preface for the 11th edition resulted in a bit of reflection on the 40
years since the first edition was published in 1972 by two young educators eager to test
their ability to improve on the available literature on electronic devices. Although one may
prefer the term semiconductor devices rather than electronic devices, the first edition was
almost exclusively a survey of vacuum-tube devices—a subject without a single section in
the new Table of Contents. The change from tubes to predominantly semiconductor devices
took almost five editions, but today it is simply referenced in some sections. It is interest-
ing, however, that when field-effect transistor (FET) devices surfaced in earnest, a number
of the analysis techniques used for tubes could be applied because of the similarities in the
ac equivalent models of each device.
We are often asked about the revision process and how the content of a new edition is
defined. In some cases, it is quite obvious that the computer software has been updated,
and the changes in application of the packages must be spelled out in detail. This text
was the first to emphasize the use of computer software packages and provided a level
of detail unavailable in other texts. With each new version of a software package, we
have found that the supporting literature may still be in production, or the manuals lack
the detail for new users of these packages. Sufficient detail in this text ensures that a
student can apply each of the software packages covered without additional instruc-
tional material.
The next requirement with any new edition is the need to update the content reflecting
changes in the available devices and in the characteristics of commercial devices. This
can require extensive research in each area, followed by decisions regarding depth of
coverage and whether the listed improvements in response are valid and deserve recog-
nition. The classroom experience is probably one of the most important resources for
defining areas that need expansion, deletion, or revision. The feedback from students
results in marked-up copies of our texts with inserts creating a mushrooming copy of the
material. Next, there is the input from our peers, faculty at other institutions using the
text, and, of course, reviewers chosen by Pearson Education to review the text. One
source of change that is less obvious is a simple rereading of the material following the
passing of the years since the last edition. Rereading often reveals material that can be
improved, deleted, or expanded.
For this revision, the number of changes far outweighs our original expectations. How-
ever, for someone who has used previous editions of the text, the changes will probably
be less obvious. However, major sections have been moved and expanded, some 100-plus
problems have been added, new devices have been introduced, the number of applications
has been increased, and new material on recent developments has been added through-
out the text. We believe that the current edition is a significant improvement over the
previous editions.
As instructors, we are all well aware of the importance of a high level of accuracy
required for a text of this kind. There is nothing more frustrating for a student than to
work a problem over from many different angles and still find that the answer differs
from the solution at the back of the text or that the problem seems undoable. We were
pleased to find that there were fewer than half a dozen errors or misprints reported since
v
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