LPDDR4X jedec SPEC.pdf

发布时间：2022-05-29 发布人：admin 分类：说明书资料大小：1.17M 资料格式：pdf 举报版权申诉

weixin_42123935-10388604-4744300845387052199.pdf-第1页.png

第1页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第2页.png

第2页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第3页.png

第3页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第4页.png

第4页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第5页.png

第5页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第6页.png

第6页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第7页.png

第7页 / 共42页

weixin_42123935-10388604-4744300845387052199.pdf-第8页.png

第8页 / 共42页

JESD209-4-1

Contents

1 Scope

2 Package Ballout and Pin Definition

2.1 Pad Order

2.2 Single Channel Pad Order

2.3 LPDDR4X packages

2.3.1 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 mm pitch) – Using MO-317A

2.3.2 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A

2.3.3 200-ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311

2.3.4 432-ball x64 HDI Discrete Package, 0.50 mm x 0.50 mm (MO-313)

2.3.5 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276

2.3.6 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276

2.4 Pad Definition and Description

2.5 Mode Register Definition

3 Command Definitions and Timing Diagrams

3.1 Pull Up/Pull Down Driver Characteristics and Calibration

3.2 ODT Mode Register and ODT Characteristics

3.3 On Die Termination for DQ, DQS and DMI

3.4 Output Driver and Termination Register Temperature and Voltage Sensitivity

4 AC and DC Operating Conditions

4.1 Recommended DC Operating Conditions for low voltage

4.2 Single Ended Output Slew Rate

4.3 Differential Output Slew Rate

5 VREF Specifications

5.1 CA Internal VREF Specifications

6 Power-up, Initialization and Power-off Procedure

7 ODT Mode Register and ODT State Table

8 Core Timing

Standards Improvement Form

JEDEC STANDARD Addendum No. 1 to JESD209-4 - Low Power Double Data Rate 4X (LPDDR4X) JESD209-4-1 JANUARY 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by ©JEDEC Solid State Technology Association 2017 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved

PLEASE! DON’T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information.

JEDEC Standard No. 209-4-1 Addendum No. 1 to JESD209-4 - LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) Contents 1 2 Scope ................................................................................................................................. 1 Package ballout and Pin Definition ................................................................................. 2 2.1 Pad Order ........................................................................................................................... 2 2.2 Single Channel Pad Order ................................................................................................. 3 2.3 LPDDR4X packages ........................................................................................................... 4 2.3.1 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 mm pitch) – Using MO-317A ............. 4 2.3.2 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A ................................. 5 2.3.3 200-ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311 .................................. 6 2.3.4 432-ball x64 HDI Discrete Package, 0.50 mm x 0.50 mm (MO-313) .................................. 7 2.3.5 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276 .............................. 10 2.3.6 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276 ................................... 11 2.3.7 254 ball e•MMC MCP One Channel FBGA (top view) using MO-276 .............................. 10 2.4 Pad Definition and Description ......................................................................................... 13 2.5 Mode Register Definition .................................................................................................. 14 3 Command Definitions and Timing Diagrams ............................................................... 23 3.1 Pull Up/Pull Down Driver Characteristics and Calibration ............................................... 23 3.2 ODT Mode Register and ODT Characteristics ................................................................ 23 3.3 On Die Termination for DQ, DQS and DMI ...................................................................... 25 3.4 Output Driver and Termination Register Temperature and Voltage Sensitivity ............... 27 4 AC and DC Operating Conditions ................................................................................. 28 4.1 Recommended DC Operating Conditions for low voltage ................................................ 28 4.2 Single Ended Output Slew Rate ....................................................................................... 28 4.3 Differential Output Slew Rate ........................................................................................... 29 5 VREF Specifications ......................................................................................................... 30 5.1 CA Internal VREF Specifications ......................................................................................... 30 5.2 DQ Internal VREF Specifications ........................................................................................ 30 6 7 8 Power-up, Initialization and Power-off Procedure ....................................................... 30 ODT Mode Register and ODT State Table .................................................................... 33 Core Timing ..................................................................................................................... 34 -i-

JEDEC Standard No. 209-4-1 Tables Contents (cont’d) Table 1 Pad Definition and Description ...................................................................................... 13 Table 2 Mode Register Assignment in LPDDR4 SDRAM .......................................................... 14 Table 3 VREF Settings for Range[0] and Range[1] ...................................................................... 18 Table 4 VREF Settings for Range[0] and Range[1] ...................................................................... 20 Table 5 LPDDR4X Byte Mode Device (MR11 OP[6:4]  000B Case) ....................................... 22 Table 6 Pull-down Driver Characteristics, with ZQ Calibration .................................................. 23 Table 7 Terminated Pull-Up Characteristics, with ZQ Calibration .............................................. 23 Table 8 Terminated Valid Calibration Points .............................................................................. 23 Table 9 ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/-1% over the entire operating temperature range after a proper ZQ calibration. ....................................................... 24 Table 10 ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/-1% over the entire operating temperature range after a proper ZQ calibration. ....................................................... 26 Table 11 Output Driver and Termination Register Sensitivity Definition .................................... 27 Table 12 Output Driver and Termination Register Temperature and Voltage Sensitivity .......... 27 Table 13 Recommended DC Operating Conditions ................................................................... 28 Table 14 Output Slew Rate (single-ended) for 0.6 V VDDQ ......................................................... 28 Table 15 Differential Output Slew Rate for 0.6 V VDDQ ............................................................... 29 Table 16 CA Internal VREF Specifications ................................................................................... 30 Table 17 DQ Internal VREF Specifications .................................................................................. 29 Table 18 MRS defaults settings ................................................................................................. 30 Table 19 Command Bus ODT State .......................................................................................... 33 Table 20 Core Timing ................................................................................................................ 34 Figures Figure 1 On Die Termination for CA .......................................................................................... 23 Figure 2 On Die Termination ...................................................................................................... 25 Figure 3 Single Ended Output Slew Rate Definition .................................................................. 28 Figure 4 Differential Output Slew Rate Definition ...................................................................... 29 -ii-

JEDEC Standard No. 209-4-1 Page 1 Addendum No. 1 to JESD209-4 - LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) (From JEDEC Board Ballot JCB-16-49, formulated under the cognizance of the JC-42.6 Subcommittee on Low Power Memories.) 1 Scope This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard. This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption.

JEDEC Standard No. 209-4-1 Page 2 2 Package Ballout and Pin Definition 2.1 Pad Order CA1_A CA0_A VDD2 Ch. A Top 41 VDD2 VDD2 1 42 CKE_A VSS 2 43 CS_A VDD1 3 44 VSS VDD2 4 45 VSS 5 46 6 VSSQ 47 7 DQ8_A 48 ODT(ca)_A 8 VDDQ 49 VSS 9 DQ9_A 50 VDD1 10 VSSQ 51 VSSQ 11 DQ10_A 52 DQ7_A 12 VDDQ 53 VDDQ 13 DQ11_A 54 DQ6_A 14 VSSQ 15 DQS1_t_A 55 VSSQ 16 DQS1_c_A 56 DQ5_A 57 VDDQ 17 VDDQ 58 DQ4_A 18 DMI1_A 59 19 VSSQ VSSQ 60 DMI0_A 20 DQ12_A 61 21 VDDQ VDDQ 62 DQS0_c_A 22 DQ13_A 63 DQS0_t_A 23 VSSQ 64 24 DQ14_A 65 25 VDDQ 66 26 DQ15_A 67 27 VSSQ 68 28 69 29 VDDQ 70 VDD2 30 71 VDD1 31 72 32 VSS 73 33 CA5_A 74 34 CA4_A 75 35 VDD2 76 36 CA3_A 77 37 CA2_A Ch. A Bottom 38 39 CK_c_A 40 CK_t_A Ch. A Top VSSQ DQ3_A VDDQ DQ2_A VSSQ DQ1_A VDDQ DQ0_A VSSQ VSS VDD2 VDD1 VSS VDD2 VSS ZQ Ch. B Top 141 VDD2 101 VDD2 142 CKE_B 102 VSS 143 CS_B 103 VDD1 144 VSS 104 VDD2 145 CA1_B 105 VSS 146 CA0_B 106 VSSQ 147 VDD2 107 DQ8_B 148 ODT(ca)_B 108 VDDQ 149 VSS 109 DQ9_B 150 VDD1 110 VSSQ 151 VSSQ 111 DQ10_B 152 DQ7_B 112 VDDQ 153 VDDQ 113 DQ11_B 154 DQ6_B 114 VSSQ 115 DQS1_t_B 155 VSSQ 116 DQS1_c_B 156 DQ5_B 153 VDDQ 117 VDDQ 158 DQ4_B 118 DMI1_B 159 VSSQ 119 VSSQ 160 DMI0_B 120 DQ12_B 161 VDDQ 121 VDDQ 162 DQS0_c_B 122 DQ13_B 163 DQS0_t_B 123 VSSQ 164 VSSQ 124 DQ14_B 165 DQ3_B 125 VDDQ 166 VDDQ 126 DQ15_B 167 DQ2_B 127 VSSQ 168 VSSQ 128 RESET_n 169 DQ1_B 129 VDDQ 170 VDDQ 130 VDD2 171 DQ0_B 131 VDD1 172 VSSQ 132 VSS 173 133 CA5_B VSS 174 VDD2 134 CA4_B 175 VDD1 135 VDD2 176 136 CA3_B VSS 177 VDD2 137 CA2_B Ch. B Bottom 138 139 CK_c_B 140 CK_t_B Ch. B Top VSS NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes. NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads. NOTE 3 VDDQ pads ((#12,#21,#57,#66,#112,#121,#157 and #166) may be individually assigned to either VDDQ or VDD2. Please refer to vendor specification.

分享到：

赞收藏

资料库

LPDDR4X jedec SPEC.pdf

相关推荐

开发技术

热门标签

最新资料