底层译码器程序：library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity display is port(temp : in std_logic_vector(3 downto 0); led7s : out std_logic_vector(6 downto 0) ); end display; architecture mm of display is begin process (temp) begin case temp is when "0000" => led7s<="0111111"; when "0001" => led7s<="0000110"; when "0010" => led7s<="1011011"; when "0011" => led7s<="1001111"; when "0100" => led7s<="1100110"; when "0101" => led7s<="1101101"; when "0110" => led7s<="1111101"; when "0111" => led7s<="0000111"; when "1000" => led7s<="1111111"; when "1001" => led7s<="1101111"; when "1010" => led7s<="1110111"; when "1011" => led7s<="1111100"; when "1100" => led7s<="0111001"; when "1101" => led7s<="1011110"; when "1110" => led7s<="1111001"; when "1111" => led7s<="1110001"; when others => null; end case; end process; end mm; 顶层程序： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count60 is port(clk : in std_logic; clr : in std_logic; spk : out std_logic; p1,p2: out std_logic_vector(6 downto 0) ); end count60; architecture mm of count60 is component display port(temp : in std_logic_vector(3 downto 0); led7s : out std_logic_vector(6 downto 0) 

); end component; signal count : std_logic_vector(7 downto 0); signal p_temp1,p_temp2 : std_logic_vector(3 downto 0); signal rest,outclk,clk1 : std_logic; begin process(clk) variable count1 : integer range 0 to 255; begin if (clk'event and clk='1') then if count1<128 then count1:=count1+1; else count1:=0; outclk<= not outclk; end if; end if; clk1<=outclk and rest; end process； process(clk1,clr) begin if clr='1' then count<="00000000"; rest<='1'; elsif rising_edge(clk1) then if count(3 downto 0)="1001" then count(3 downto 0)<="0000"; count(7 downto 4)<=count(7 downto 4)+1; else count(3 downto 0)<=count(3 downto 0)+1; end if; if count="01011001" then count<="00000000"; spk<=clk; end if; end if; end process; u1 : display port map(count(3 downto 0),p1); u2 : display port map(count(7 downto 4),p2); end mm; 实验总结：通过本次实验，我能够熟悉的使用系统时钟进行分频，将分频后的时 钟运用于其他模块中。同时更加熟练的运用计数器模块和译码显示模块。