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2019.06VCS SystemC User Guide.pdf
Contents
Introduction
Supported Topologies
Supported Platforms
Installing VG GNU Package
VCS Extensions to SystemC Library
Supported Macros
VCSSYSTEMC
SNPS_REGISTER_SC_MAIN
SNPS_REGISTER_SC_MODULE
Compilation Flow
SystemC Only Designs
Use Model
Supporting Designs With Donut Topologies
Enabling Unified Hierarchy for VCS and SystemC
Using Unified Hierarchy Elaboration
Value Added by –sysc=unihier Option
Using the –sysc=show_sc_main Switch
SystemC Unified Hierarchy Flow Limitations
Combining SystemC With Verilog Configurations
Verilog-on-Top, SystemC and/or VHDL Down
Compiling a Verilog/SystemC Design
Compiling a Verilog/SystemC+VHDL Design
SystemC-on-Top, Verilog and/or VHDL Down
Compiling a SystemC/Verilog Design
Compiling a SystemC/Verilog+VHDL Design
Limitations
Considerations for Export DPI Tasks
Use syscan -export_DPI [function-name]
Use syscan -export_DPI [Verilog-file]
Use Stubs File
Considerations for Export DPI_SC Tasks
Static and Dynamic Linking
Static Linking in VCS
Dynamic Linking in VCS (For C/C++ Files)
Dynamic Linking in VCS (For SystemC Files)
LD_LIBRARY_PATH Environment Variable
Using -Mlib and -Mdir Options
Incremental Compile of SystemC Source Files
Full Build From Scratch
Full Incremental Build
Partial Build With Object Files
Partial Build With Shared Libraries
Updating the Shared Library
Using Different Libraries
Partial Build Invoked With VCS
Partial Build If Only One Shared Library is Updated
Adding or Deleting SC Source Files in Shared Library
Changing From a Shared Library Back to Object Files
Dependency Checking of SystemC Source Files
Default Setting
Example
Example
Example
Shared Library Flow
Compiling and Linking the SystemC Source Files
Using Makefiles
Generating an SC/HDL Interface model
Using the SNPS_SYSC_MODULE_EXPORT Macro
Support for syscan in Parallel Build Environment
Limitations
Elaboration Scheme
Improving Compilation Speed Using Precompiled C++ Headers
Introduction to Precompiled Header Files
Using Precompiled Header Files
Usage Example
Invoking the Creation of Precompiled Header Files
Limitations
Limitations of GNU Precompiled Header Files
Limitations of syscan -prec Option
Limitations of Using -prec With Path
Limitations of Sharing Precompiled Header Files
Modeling SystemC Designs With SCV
SCV Library in VCS
Use Model
msglog Extensions for Transaction Recording With SCV in VCS
Use Model
Using a Customized SystemC Installation
Compatibility with OSCI SystemC
Compiling Source Files
Limitations
Controlling TimeScale and Resolution
Setting TimeScale/Resolution of Verilog/VHDL Kernel
Setting TimeScale/Resolution of SystemC Kernel
Automatic Adjustment of Time Resolution
Adding a Main Routine for Verilog-On-Top Designs
Support for AMS With SystemC Design
Use Model
Usage Example
Compile Flow Limitations
Simulation Flow
Specifying Runtime Options to the SystemC Simulation
Controlling Simulation From sc_main
Elaboration and Simulation Callbacks
Effect on end_of_simulation Callbacks
Enabling E115 Check in VCS Co-Simulation Interface
Delta-Cycles
Using HDL and SystemC Sync Loops
Coarse-Grained Sync Loop (blocksync)
Fine-Grained Sync Loop (deltasync)
Simulation Differences Between blocksync and deltasync Loop
Increasing Stack and Stack Guard Size
Increasing Stack Size
Increasing Stack Guard Size
Guidelines to Diagnose Stack Overrun
Using POSIX Threads or Quickthreads
Generating Profile Reports for SystemC Designs
Time Profiling
Enabling Time Profiling at Compile-Time
Using Time Profiling at Runtime
Memory Profiling
Enabling Memory Profiling at Compile-Time
Using Memory Profiling at Runtime
Profiler Example
Profile Report Limitations
Viewing SystemC sc_report_handler Messages from Log File
Debugging SystemC Simulation Errors
Debugging SystemC Kernel Errors
Troubleshooting Elaboration Errors
Troubleshooting Simulation Errors
Function cbug_stop_here()
Limitations
Diagnosing Quickthread Issues
RTL Interface Model
Instantiating SystemC Inside Verilog Design
Use Model
Input Files Required
Generating Verilog/VHDL Wrappers for SystemC Modules
Creating Verilog/VHDL Wrapper from SystemC Header File
Supported Port Data Types
Example
Use Model
DWARF Based SystemC Front-End
Use Model
Limitation
Compiling Interface Models with acc_user.h and vhpi_user.h
Instantiating Verilog/VHDL Inside SystemC
Usage Model
Input Files Required
Generating SystemC Wrapper for Verilog Modules
Generating SystemC Wrapper for VHDL Designs
Generating SystemC Wrapper for Verilog Models (Alternative Use Model)
Example
Use Model
Instantiating SystemC Inside VHDL Design
Use Model
Input Files Required
Example
Use Model
Support for Multiple-Top Topology
Usage Model
Limitations
Using OPT Interface-Based Communication Using OPT Interface-Based Communication (-sysc=opt_if)
Limitations
Using Direct Programming Interface-Based Communication (-sysc=dpi_if)
Limitations
Adding Delays in SystemC or HDL Interface Models
Use Model
Limitations
Using Port Mapping File
Default Type Mapping
Automatic Generation of Portmap File
Modifying the Port Mapping File Manually
Using Data Type Mapping File
Support for Ports of Floating-Point Data Types for SC/ HDL Interface Models
Use Model
Extensions to Port Map File
Limitations
Support for Floating-Point Data Type Double in SystemC/HDL Interface Model
Use Mode
SystemC down interface modules
Verilog-down interface modules
Limitations
Support for Enumeration Type in SystemC/HDL Interface Models
Use Model
For example:
Limitations
Instantiating HDL module With Multiple Ports in SystemC Design
Use Model
Using the Port Map File
Execution of the Portmap File
Automatic Generation of Portmap File
Type Specification and Attributes in the Portmap File
Limitation
Using Parameters in Verilog/VHDL and SystemC
Parameters in Verilog
Parameters in VHDL
Parameters in SystemC
Verilog-on-Top, SystemC-Down
VHDL-on-Top, SystemC-Down
SystemC-on-Top, Verilog/VHDL-Down
Namespace
Parameter Specification as VCS Elaboration Arguments
Debug
Limitations
Transaction Level Interface Model
Transaction Level Interface
Interface Definition File
Instantiation and Binding
Supported Data Types of Formal Arguments
Miscellaneous
Generation of TLI Adaptors
TLI Adaptors
Connecting SystemVerilog VMM with SystemC TLM 2.0
SV Producer (vmm_channel) => SC Consumer (TLM 2.0)
SV Producer (vmm_tlm) => SC Consumer (TLM 2.0)
SV Producer (vmm_tlm analysis port) => SC Consumer (TLM2.0 Analysis Subscriber)
SC Producer (TLM 2.0) => SV Consumer (vmm_channel)
SC Producer (TLM 2.0) => SV Consumer (vmm_tlm)
SC Producer (TLM 2.0 Analysis Parent) => SV Consumer (vmm_tlm Analysis Subscriber)
User-Defined Payload
Connecting System Verilog UVM with SystemC TLM 2.0
SV Producer (UVM TLM) => SC Consumer (TLM 2.0)
SC Producer (TLM 2.0) => SV Consumer (UVM TLM)
SV Producer (UVM Analysis Port) => SC Consumer (TLM 2.0 Analysis Subscriber)
SC Producer (TLM 2.0 Analysis Parent) => SV Consumer (UVM TLM Analysis Subscriber)
VMM TLM Communication Examples
Example 1
Example 2
Example 3
Example 4
Example 5
Example 6
Example 7
Example 8
Example 9
Example 10
UVM TLM Communication Examples
uvm_tlm_blocking Example
uvm_tlm_nonblocking Example
uvm_tlm_analysis Example
Aligning Messages in VMM/UVM With SystemC sc_report()
Aligning VMM and SystemC Messages
Use Model
Changing Message Alignment Settings
Mapping SystemC to VMM Severities
Filtering Messages
Limitations
Aligning UVM and SystemC Messages
Use Model
Mapping SystemC to UVM Severities
Accessing UVM Report Object of SystemC Instance
TLI Direct Access
Accessing SystemC Members from SystemVerilog
TLI Adaptor
Instantiating TLI Adaptor in SV
Direct Variable Access
Calling SystemC Member Function
Arguments of Type char* Used in Blocking Member Functions
Supported Data Types
SC_FIFO
Non-SystemC Classes
Sub-Classes
Name Clashes
Error Handling
Compile Flow
Support for $call_systemc_func API in TLI Flow
Use Model
Usage Example
Limitations
Creating a TLI Adapter by Simplifying the Compile Flow
Use Model
Rules for TLI File/Syntax
Debug Flow
Accessing Struct or Class Members of a SystemC Module From SystemVerilog
TLI Enhancements for Providing Access to SystemC/ C++ Class Members From SystemVerilog
TLI Input File Extensions
Invoking the Pack or Unpack Adaptor Code Generation
Limitations
Accessing Verilog Variables From SystemC
Usage Model
Access Functions
Supported Data Types
Usage Example
Type Conversion Mechanism
Accessing SystemC Members From SystemVerilog Using the tli_get_ or tli_set_ Functions
Using the tli_get_ and tli_set_ Functions
Prototypes of tli_get_ and tli_set_ Functions
Supported Data Types
Member Variables
Type Conversion Mechanism
Compile Flow
Accessing SystemVerilog Functions and Tasks From SystemC
Usage Model
Function Declaration Hierarchy
Passing Arguments
Supported Types
Usage Example
Compile Flow
Usage Guidelines
Limitations
Generating C++ Struct Definition From SystemVerilog Class Definition
Use Model for Generating C++ Struct From SystemVerilog Class
Data Type Conversion From SystemVerilog to C++
Example for Generating C++ Struct From SystemVerilog Class
Limitations
Exchanging Data Between SystemVerilog and SystemC Using Byte Pack/Unpack
Use Model
Supported Data Types
Unsupported Data Types
Mapping of SystemC/C++ and SystemVerilog Data Types
Usage Examples
Using Pack and Unpack Functions
Using Code Generator
Support for TLI Adapter in a Package
Use Model
Usage Example
Support for Importing SV Functions
Use Model
Usage Example
Limitations
Support TLI Adapter With svOpenArrayHandle for DPI Import Function
Use Model
Usage Example
Limitations
Index
VCS® SystemC User GuideP-2019.06-SP1, September 2019Verification ContinuumTM
iiCopyright Notice and Proprietary Information© 2019 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Third-Party Software NoticesVCS® and configurations of VCS includes or is bundled with software licensed to Synopsys under free or open-source licenses. For additional information regarding Synopsys's use of free and open-source software, refer to the third_party_notices.txt file included within the /doc directory of the installed VCS software.Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them.DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.TrademarksSynopsys and certain Synopsys product names are trademarks of Synopsys, as set forth athttps://www.synopsys.com/company/legal/trademarks-brands.html.All other product or company names may be trademarks of their respective owners.Free and Open-Source Software Licensing NoticesIf applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.Third-Party LinksAny links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content.www.synopsys.com
iiiFeedbackFeedbackContents1.IntroductionSupported Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Installing VG GNU Package. . . . . . . . . . . . . . . . . . . . . . . . . .1-3VCS Extensions to SystemC Library. . . . . . . . . . . . . . . . . . . . . .1-4Supported Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6VCSSYSTEMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7SNPS_REGISTER_SC_MAIN. . . . . . . . . . . . . . . . . . . . . . . .1-7SNPS_REGISTER_SC_MODULE . . . . . . . . . . . . . . . . . . . .1-82.Compilation FlowSystemC Only Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3Supporting Designs With Donut Topologies . . . . . . . . . . . . . . . .2-4Enabling Unified Hierarchy for VCS and SystemC . . . . . . . . . . .2-6Using Unified Hierarchy Elaboration . . . . . . . . . . . . . . . . . . .2-6
ivFeedbackFeedbackValue Added by –sysc=unihier Option . . . . . . . . . . . . . . .2-9Using the –sysc=show_sc_main Switch . . . . . . . . . . . . . . . .2-10SystemC Unified Hierarchy Flow Limitations. . . . . . . . . . . . .2-11Combining SystemC With Verilog Configurations. . . . . . . . . . . .2-12Verilog-on-Top, SystemC and/or VHDL Down. . . . . . . . . . . .2-12Compiling a Verilog/SystemC Design. . . . . . . . . . . . . . . .2-14Compiling a Verilog/SystemC+VHDL Design. . . . . . . . . .2-15SystemC-on-Top, Verilog and/or VHDL Down. . . . . . . . . . . .2-15Compiling a SystemC/Verilog Design. . . . . . . . . . . . . . . .2-17Compiling a SystemC/Verilog+VHDL Design. . . . . . . . . .2-18Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18Considerations for Export DPI Tasks. . . . . . . . . . . . . . . . . . . . . .2-19Use syscan -export_DPI [function-name] . . . . . . . . . . . . . . .2-19Use syscan -export_DPI [Verilog-file] . . . . . . . . . . . . . . . . . .2-20Use Stubs File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21Static and Dynamic Linking. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-22Static Linking in VCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23Dynamic Linking in VCS (For C/C++ Files) . . . . . . . . . . . . . .2-24Dynamic Linking in VCS (For SystemC Files). . . . . . . . . . . .2-26LD_LIBRARY_PATH Environment Variable. . . . . . . . . . . . . .2-26Using -Mlib and -Mdir Options. . . . . . . . . . . . . . . . . . . . . . . . . . .2-26Incremental Compile of SystemC Source Files. . . . . . . . . . . . . .2-27Full Build From Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28Full Incremental Build . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28Partial Build With Object Files . . . . . . . . . . . . . . . . . . . . . . . .2-30
vFeedbackFeedbackPartial Build With Shared Libraries . . . . . . . . . . . . . . . . . . . .2-31Updating the Shared Library . . . . . . . . . . . . . . . . . . . . . .2-32Using Different Libraries. . . . . . . . . . . . . . . . . . . . . . . . . .2-32Partial Build Invoked With VCS . . . . . . . . . . . . . . . . . . . .2-33Partial Build If Only One Shared Library is Updated . . . .2-33Adding or Deleting SC Source Files in Shared Library . .2-34Changing From a Shared Library Back to Object Files . .2-34Dependency Checking of SystemC Source Files . . . . . . . . .2-34Default Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-35Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-35Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-36Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-37Shared Library Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38Compiling and Linking the SystemC Source Files. . . . . . . . .2-39Using Makefiles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-41Generating an SC/HDL Interface model . . . . . . . . . . . . . . . .2-42Using the SNPS_SYSC_MODULE_EXPORT Macro . . . . . .2-42Support for syscan in Parallel Build Environment. . . . . . . . . . . .2-43Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-43Elaboration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-44Improving Compilation Speed Using Precompiled C++ Headers2-47Introduction to Precompiled Header Files . . . . . . . . . . . . . . .2-48Using Precompiled Header Files. . . . . . . . . . . . . . . . . . . . . .2-48Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-50Invoking the Creation of Precompiled Header Files. . . . . . . .2-50Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-51
viFeedbackFeedbackLimitations of GNU Precompiled Header Files. . . . . . . . .2-52Limitations of syscan -prec Option. . . . . . . . . . . . . . . . . .2-52Limitations of Using -prec With Path . . . . . . . . . . . . . . . .2-53Limitations of Sharing Precompiled Header Files . . . . . .2-54Modeling SystemC Designs With SCV . . . . . . . . . . . . . . . . . . . .2-55SCV Library in VCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-55Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56msglog Extensions for Transaction Recording With SCV in VCS2-57Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57Using a Customized SystemC Installation . . . . . . . . . . . . . . . . .2-58Compatibility with OSCI SystemC . . . . . . . . . . . . . . . . . . . . .2-60Compiling Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61Controlling TimeScale and Resolution . . . . . . . . . . . . . . . . . . . .2-61Setting TimeScale/Resolution of Verilog/VHDL Kernel . . . . .2-62Setting TimeScale/Resolution of SystemC Kernel. . . . . . . . .2-62Automatic Adjustment of Time Resolution. . . . . . . . . . . . . . .2-63Adding a Main Routine for Verilog-On-Top Designs . . . . . . . . . .2-65Support for AMS With SystemC Design . . . . . . . . . . . . . . . . . . .2-66Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-66Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-67Compile Flow Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-673.Simulation FlowSpecifying Runtime Options to the SystemC Simulation. . . . . . .3-2
viiFeedbackFeedbackControlling Simulation From sc_main . . . . . . . . . . . . . . . . . . . . .3-2Elaboration and Simulation Callbacks. . . . . . . . . . . . . . . . . .3-6Effect on end_of_simulation Callbacks . . . . . . . . . . . . . . . . .3-7Enabling E115 Check in VCS Co-Simulation Interface. . . . . . . .3-8Delta-Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10Using HDL and SystemC Sync Loops. . . . . . . . . . . . . . . . . .3-11Coarse-Grained Sync Loop (blocksync). . . . . . . . . . . . . .3-11Fine-Grained Sync Loop (deltasync) . . . . . . . . . . . . . . . .3-12Simulation Differences Between blocksync and deltasync Loop3-14Increasing Stack and Stack Guard Size . . . . . . . . . . . . . . . . . . .3-19Increasing Stack Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19Increasing Stack Guard Size. . . . . . . . . . . . . . . . . . . . . . . . .3-20Guidelines to Diagnose Stack Overrun . . . . . . . . . . . . . . . . .3-21Using POSIX Threads or Quickthreads. . . . . . . . . . . . . . . . . . . .3-22Generating Profile Reports for SystemC Designs. . . . . . . . . . . .3-23Time Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24Enabling Time Profiling at Compile-Time. . . . . . . . . . . . .3-24Using Time Profiling at Runtime. . . . . . . . . . . . . . . . . . . .3-24Memory Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26Enabling Memory Profiling at Compile-Time . . . . . . . . . .3-26Using Memory Profiling at Runtime . . . . . . . . . . . . . . . . .3-26Profiler Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27Profile Report Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32Viewing SystemC sc_report_handler Messages from Log File. .3-33
viiiFeedbackFeedbackDebugging SystemC Simulation Errors. . . . . . . . . . . . . . . . . . . .3-33Debugging SystemC Kernel Errors . . . . . . . . . . . . . . . . . . . .3-34Troubleshooting Elaboration Errors . . . . . . . . . . . . . . . . .3-34Troubleshooting Simulation Errors. . . . . . . . . . . . . . . . . .3-37Function cbug_stop_here() . . . . . . . . . . . . . . . . . . . . . . .3-39Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-41Diagnosing Quickthread Issues. . . . . . . . . . . . . . . . . . . . . . .3-414.RTL Interface ModelInstantiating SystemC Inside Verilog Design. . . . . . . . . . . . . . . .4-2Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4Generating Verilog/VHDL Wrappers for SystemC Modules. .4-5Creating Verilog/VHDL Wrapper from SystemC Header File4-12Supported Port Data Types . . . . . . . . . . . . . . . . . . . . . . . . . .4-13Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-15Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17DWARF Based SystemC Front-End . . . . . . . . . . . . . . . . . . .4-18Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20Compiling Interface Models with acc_user.h and vhpi_user.h4-21Instantiating Verilog/VHDL Inside SystemC . . . . . . . . . . . . . . . .4-23Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25Generating SystemC Wrapper for Verilog Modules. . . . . . . .4-26Generating SystemC Wrapper for VHDL Designs. . . . . . . . .4-27
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