1 General Description
1.1 Features
1.2 System block diagram
2 Pin Descriptions
2.1 Pinout diagram
2.2 Pin descriptions
3 Functional Description
3.1 Basic switch function
3.1.1 Lookup engine
3.1.2 Automatic address learning
3.1.3 Automatic address aging
3.1.4 Flow control
3.1.5 ARL table
3.1.6 Mirroring
3.2 QoS
3.2.1 Scheduling
3.2.2 Ingress rate limit
3.2.3 Egress rate limit
3.2.4 Head-of-line blocking
3.3 VLAN
3.3.1 Port-based VLAN
3.3.2 802.1q VLANs
3.3.3 VLAN security
3.3.4 Port isolation
3.3.5 Leaky VLAN
3.3.6 VLAN translation
3.3.7 VLAN translation table
3.3.8 Egress mode
3.3.9 VLAN table
3.4 ACL
3.4.1 ACL rule
3.4.2 Action definition
3.4.3 MAC pattern
3.4.4 IPv4 pattern
3.4.5 IPv6 pattern
3.4.6 Window pattern
3.4.7 Enhanced MAC pattern
3.4.8 Enhanced MAC pattern mask
3.5 IGMP/MLD snooping
3.5.1 IEEE 802.3 reserved group addresses filtering control
3.5.2 802.1x
3.5.3 Forwarding unknown
3.5.4 MAC limit
3.6 Atheros header
3.6.1 Transmit
3.6.2 Receive
3.6.3 Header for read/write register
3.7 MIB/statistics counters
3.8 LED control
3.9 EEPROM programming format
3.10 MDC/MDIO access
3.11 HNAT
3.11.1 Basic NAT table
3.11.2 NAPT entry
3.11.3 Router MAC address
3.11.4 ARP entry
3.12 IEEE 802.3az and energy efficient Ethernet
3.12.1 IEEE 802.3az LPI mode
3.13 Memory map
4 Electrical Characteristics
4.1 Absolute maximum ratings
4.2 Recommended operating conditions
4.3 RGMII/GMII characteristics
4.4 Power-on strapping
4.4.1 Power-on-reset timing
4.5 AC timing
4.5.1 XTAL/OSC timing
4.5.2 MII timing
4.5.3 GMII timing
4.5.4 RGMII timing
4.5.5 SPI timing
4.5.6 MDIO timing
4.6 Typical power consumption parameters
5 Register Descriptions
5.1 Register address space (offset range: 0x0000–0x0E98)
5.2 Global control registers (offset range: 0x0000–0x00E0)
5.2.1 MASK_CTRL
5.2.2 PORT0_PAD_CTRL
5.2.3 PORT5_PAD_CTRL
5.2.4 PORT6_PAD_CTRL
5.2.5 PWS_REG
5.2.6 GLOBAL_INT0
5.2.7 GLOBAL_INT1
5.2.8 GLOBAL_INT0_MASK
5.2.9 GLOBAL_INT1_MASK
5.2.10 MODULE_EN
5.2.11 MIB
5.2.12 INTERFACE_HIGH_ADDR
5.2.13 MDIO master control
5.2.14 BIST_CTRL
5.2.15 BIST_RECOVER
5.2.16 SERVICE_TAG
5.2.17 LED_CTRL0
5.2.18 LED_CTRL1
5.2.19 LED_CTRL2
5.2.20 LED_CTRL3
5.2.21 GOL_MAC_ADDR0
5.2.22 GOL_MAC_ADDR1
5.2.23 MAX_FRAME_SIZE
5.2.24 PORT0_STATUS
5.2.25 PORT1_STATUS
5.2.26 PORT2_STATUS
5.2.27 PORT3_STATUS
5.2.28 PORT4_STATUS
5.2.29 PORT5_STATUS
5.2.30 PORT6_STATUS
5.2.31 HEADER_CTRL
5.2.32 PORT0_HEADER_CTRL
5.2.33 PORT1_HEADER_CTRL
5.2.34 PORT2_HEADER_CTRL
5.2.35 PORT3_HEADER_CTRL
5.2.36 PORT4_HEADER_CTRL
5.2.37 PORT5_HEADER_CTRL
5.2.38 PORT6_HEADER_CTRL
5.2.39 SGMII_CTRL
5.3 EEE control registers (offset range: 0x0100–0x0168)
5.3.1 EEE_CTRL
5.3.2 EEE_LOC_VALUE_1
5.3.3 EEE_REM_VALUE_1
5.3.4 EEE_RES_VALUE_1
5.3.5 EEE_LOC_VALUE_2
5.3.6 EEE_REM_VALUE_2
5.3.7 EEE_RES_VALUE_2
5.3.8 EEE_LOC_VALUE_3
5.3.9 EEE_REM_VALUE_3
5.3.10 EEE_RES_VALUE_3
5.3.11 EEE_LOC_VALUE_4
5.3.12 EEE_REM_VALUE_4
5.3.13 EEE_RES_VALUE_4
5.3.14 EEE_LOC_VALUE_5
5.3.15 EEE_REM_VALUE_5
5.3.16 EEE_RES_VALUE_5
5.4 Parser control registers (offset range: 0x0200–0x0270)
5.4.1 NORMALIZE_CTRL0
5.4.2 NORMALIZE_CTRL1
5.4.3 NORMALIZE_LEN_CTRL
5.4.4 FRAM_ACK_CTRL0
5.4.5 FRAM_ACK_CTRL1
5.4.6 WIN_RULE_CTRL0
5.4.7 WIN_RULE_CTRL1
5.4.8 WIN_RULE_CTRL2
5.4.9 WIN_RULE_CTRL3
5.4.10 WIN_RULE_CTRL4
5.4.11 WIN_RULE_CTRL5
5.4.12 WIN_RULE_CTRL6
5.4.13 WIN_RULE_CTRL7
5.4.14 WIN_RULE_CTRL8
5.4.15 WIN_RULE_CTRL9
5.4.16 WIN_RULE_CTRL10
5.4.17 WIN_RULE_CTRL11
5.4.18 WIN_RULE_CTRL12
5.4.19 WIN_RULE_CTRL13
5.4.20 TRUNK_HASH_EN
5.5 ACL register (offset range: 0x0400–0x0454)
5.5.1 ACL_FUNC0
5.5.2 ACL_FUNC1
5.5.3 ACL_FUNC2
5.5.4 ACL_FUNC3
5.5.5 ACL_FUNC4
5.5.6 ACL_FUNC5
5.5.7 VLAN_TRANS_TEST
5.5.8 PORT0_VLAN_CTRL0
5.5.9 PORT0_VLAN_CTRL1
5.5.10 PORT1_VLAN_CTRL0
5.5.11 PORT1_VLAN_CTRL1
5.5.12 PORT2_VLAN_CTRL0
5.5.13 PORT2_VLAN_CTRL1
5.5.14 PORT3_VLAN_CTRL0
5.5.15 PORT3_VLAN_CTRL1
5.5.16 PORT4_VLAN_CTRL0
5.5.17 PORT4_VLAN_CTRL1
5.5.18 PORT5_VLAN_CTRL0
5.5.19 PORT5_VLAN_CTRL1
5.5.20 PORT6_VLAN_CTRL0
5.5.21 PORT6_VLAN_CTRL1
5.5.22 IPV4_PRI_BASE_ADDR
5.5.23 IPV4_PRI_BASE_ADDR_MASK
5.6 Lookup register (offset range: 0x0600–0x0718)
5.6.1 ATU_DATA0
5.6.2 ATU_DATA1
5.6.3 ATU_DATA2
5.6.4 ATU_FUNC_REG
5.6.5 VTU_FUNC_REG0
5.6.6 VTU_FUNC_REG1
5.6.7 ARL_CTRL
5.6.8 GLOBAL_FW_CTRL0
5.6.9 GLOBAL_FW_CTRL1
5.6.10 GOL_LEARN_LIMIT
5.6.11 TOS_PRI_MAP_REG0
5.6.12 TOS_PRI_MAP_REG1
5.6.13 TOS_PRI_MAP_REG2
5.6.14 TOS_PRI_MAP_REG3
5.6.15 TOS_PRI_MAP_REG4
5.6.16 TOS_PRI_MAP_REG5
5.6.17 TOS_PRI_MAP_REG6
5.6.18 TOS_PRI_MAP_REG7
5.6.19 VLAN_PRI_MAP_REG0
5.6.20 LOOP_CHECK_RESULT
5.6.21 PORT0_LOOKUP_CTRL
5.6.22 PORT0_PRI_CTRL
5.6.23 PORT0_LEARN_LIMIT
5.6.24 PORT1_LOOKUP_CTRL
5.6.25 PORT1_PRI_CTRL
5.6.26 PORT1_LEARN_LIMIT
5.6.27 PORT2_LOOKUP_CTRL
5.6.28 PORT2_PRI_CTRL
5.6.29 PORT2_LEARN_LIMIT
5.6.30 PORT3_LOOKUP_CTRL
5.6.31 PORT3_PRI_CTRL
5.6.32 PORT3_LEARN_LIMIT
5.6.33 PORT4_LOOKUP_CTRL
5.6.34 PORT4_PRI_CTRL
5.6.35 PORT4_LEARN_LIMIT
5.6.36 PORT5_LOOKUP_CTRL
5.6.37 PORT5_PRI_CTRL
5.6.38 PORT5_LEARN_LIMIT
5.6.39 PORT6_LOOKUP_CTRL
5.6.40 PORT6_PRI_CTRL
5.6.41 PORT6_LEARN_LIMIT
5.6.42 GOL_TRUNK_CTRL0
5.6.43 GOL_TRUNK_CTRL1
5.6.44 GOL_TRUNK_CTRL2
5.6.45 ACL_FWD_SRC_FLTR_CTRL0
5.6.46 ACL_FWD_SRC_FLTR_CTRL1
5.6.47 ACL_FWD_SRC_FLTR_CTRL2
5.7 QM register (offset range: 0x0800–0x0B70)
5.7.1 GLOBAL_FLOW_THD
5.7.2 QM_CTRL_REG
5.7.3 WAN_QUEUE_MAP_REG
5.7.4 LAN_QUEUE_MAP_REG
5.7.5 PORT0_WRR_CTRL
5.7.6 PORT1_WRR_CTRL
5.7.7 PORT2_WRR_CTRL
5.7.8 PORT3_WRR_CTRL
5.7.9 PORT4_WRR_CTRL
5.7.10 PORT5_WRR_CTRL
5.7.11 PORT6_WRR_CTRL
5.7.12 PORT0_EG_RATE_CTRL0
5.7.13 PORT0_EG_RATE_CTRL1
5.7.14 PORT0_EG_RATE_CTRL2
5.7.15 PORT0_EG_RATE_CTRL3
5.7.16 PORT0_EG_RATE_CTRL4
5.7.17 PORT0_EG_RATE_CTRL5
5.7.18 PORT0_EG_RATE_CTRL6
5.7.19 PORT0_EG_RATE_CTRL7
5.7.20 PORT1_EG_RATE_CTRL0
5.7.21 PORT1_EG_RATE_CTRL1
5.7.22 PORT1_EG_RATE_CTRL2
5.7.23 PORT1_EG_RATE_CTRL3
5.7.24 PORT1_EG_RATE_CTRL4
5.7.25 PORT1_EG_RATE_CTRL5
5.7.26 PORT2_EG_RATE_CTRL0
5.7.27 PORT2_EG_RATE_CTRL1
5.7.28 PORT2_EG_RATE_CTRL2
5.7.29 PORT2_EG_RATE_CTRL3
5.7.30 PORT2_EG_RATE_CTRL4
5.7.31 PORT2_EG_RATE_CTRL5
5.7.32 PORT3_EG_RATE_CTRL0
5.7.33 PORT3_EG_RATE_CTRL1
5.7.34 PORT3_EG_RATE_CTRL2
5.7.35 PORT3_EG_RATE_CTRL3
5.7.36 PORT3_EG_RATE_CTRL4
5.7.37 PORT3_EG_RATE_CTRL5
5.7.38 PORT4_EG_RATE_CTRL0
5.7.39 PORT4_EG_RATE_CTRL1
5.7.40 PORT4_EG_RATE_CTRL2
5.7.41 PORT4_EG_RATE_CTRL3
5.7.42 PORT4_EG_RATE_CTRL4
5.7.43 PORT4_EG_RATE_CTRL5
5.7.44 PORT5_EG_RATE_CTRL0
5.7.45 PORT5_EG_RATE_CTRL1
5.7.46 PORT5_EG_RATE_CTRL2
5.7.47 PORT5_EG_RATE_CTRL3
5.7.48 PORT5_EG_RATE_CTRL4
5.7.49 PORT5_EG_RATE_CTRL5
5.7.50 PORT5_EG_RATE_CTRL6
5.7.51 PORT5_EG_RATE_CTRL7
5.7.52 PORT6_EG_RATE_CTRL0
5.7.53 PORT6_EG_RATE_CTRL1
5.7.54 PORT6_EG_RATE_CTRL2
5.7.55 PORT6_EG_RATE_CTRL3
5.7.56 PORT6_EG_RATE_CTRL4
5.7.57 PORT6_EG_RATE_CTRL5
5.7.58 PORT6_EG_RATE_CTRL6
5.7.59 PORT6_EG_RATE_CTRL7
5.7.60 PORT0_HOL_CTRL0
5.7.61 PORT0_HOL_CTRL1
5.7.62 PORT1_HOL_CTRL0
5.7.63 PORT1_HOL_CTRL1
5.7.64 PORT2_HOL_CTRL0
5.7.65 PORT2_HOL_CTRL1
5.7.66 PORT3_HOL_CTRL0
5.7.67 PORT3_HOL_CTRL1
5.7.68 PORT4_HOL_CTRL0
5.7.69 PORT4_HOL_CTRL1
5.7.70 PORT5_HOL_CTRL0
5.7.71 PORT5_HOL_CTRL1
5.7.72 PORT6_HOL_CTRL0
5.7.73 PORT6_HOL_CTRL1
5.7.74 PORT0_FLOW_THD
5.7.75 PORT1_FLOW_THD
5.7.76 PORT2_FLOW_THD
5.7.77 PORT3_FLOW_THD
5.7.78 PORT4_FLOW_THD
5.7.79 PORT5_FLOW_THD
5.7.80 PORT6_FLOW_THD
5.7.81 ACL_POLICY_MODE
5.7.82 ACL_COUNTER_MODE
5.7.83 ACL_CNT_RESET
5.7.84 ACL_RATE_CTRL0_0
5.7.85 ACL_RATE_CTRL1_0
5.7.86 ACL_RATE_CTRL0_1
5.7.87 ACL_RATE_CTRL1_1
5.7.88 ACL_RATE_CTRL0_2
5.7.89 ACL_RATE_CTRL1_2
5.7.90 ACL_RATE_CTRL0_3
5.7.91 ACL_RATE_CTRL1_3
5.7.92 ACL_RATE_CTRL0_4
5.7.93 ACL_RATE_CTRL1_4
5.7.94 ACL_RATE_CTRL0_5
5.7.95 ACL_RATE_CTRL1_5
5.7.96 ACL_RATE_CTRL0_6
5.7.97 ACL_RATE_CTRL1_6
5.7.98 ACL_RATE_CTRL0_7
5.7.99 ACL_RATE_CTRL1_7
5.7.100 ACL_RATE_CTRL0_8
5.7.101 ACL_RATE_CTRL1_8
5.7.102 ACL_RATE_CTRL0_9
5.7.103 ACL_RATE_CTRL1_9
5.7.104 ACL_RATE_CTRL0_10
5.7.105 ACL_RATE_CTRL1_10
5.7.106 ACL_RATE_CTRL0_11
5.7.107 ACL_RATE_CTRL1_11
5.7.108 ACL_RATE_CTRL0_12
5.7.109 ACL_RATE_CTRL1_12
5.7.110 ACL_RATE_CTRL0_13
5.7.111 ACL_RATE_CTRL1_13
5.7.112 ACL_RATE_CTRL0_14
5.7.113 ACL_RATE_CTRL1_14
5.7.114 ACL_RATE_CTRL0_15
5.7.115 ACL_RATE_CTRL1_15
5.7.116 ACL_RATE_CTRL0_16
5.7.117 ACL_RATE_CTRL1_16
5.7.118 ACL_RATE_CTRL0_17
5.7.119 ACL_RATE_CTRL1_17
5.7.120 ACL_RATE_CTRL0_18
5.7.121 ACL_RATE_CTRL0_18
5.7.122 ACL_RATE_CTRL0_19
5.7.123 ACL_RATE_CTRL1_19
5.7.124 ACL_RATE_CTRL0_20
5.7.125 ACL_RATE_CTRL1_20
5.7.126 ACL_RATE_CTRL0_21
5.7.127 ACL_RATE_CTRL1_21
5.7.128 ACL_RATE_CTRL0_22
5.7.129 ACL_RATE_CTRL1_22
5.7.130 ACL_RATE_CTRL0_23
5.7.131 ACL_RATE_CTRL1_23
5.7.132 ACL_RATE_CTRL0_24
5.7.133 ACL_RATE_CTRL1_24
5.7.134 ACL_RATE_CTRL0_25
5.7.135 ACL_RATE_CTRL1_25
5.7.136 ACL_RATE_CTRL0_26
5.7.137 ACL_RATE_CTRL1_26
5.7.138 ACL_RATE_CTRL0_27
5.7.139 ACL_RATE_CTRL1_27
5.7.140 ACL_RATE_CTRL0_28
5.7.141 ACL_RATE_CTRL1_28
5.7.142 ACL_RATE_CTRL0_29
5.7.143 ACL_RATE_CTRL1_29
5.7.144 ACL_RATE_CTRL0_30
5.7.145 ACL_RATE_CTRL1_30
5.7.146 ACL_RATE_CTRL0_31
5.7.147 ACL_RATE_CTRL1_31
5.7.148 PORT0_ING_RATE_CTRL0
5.7.149 PORT0_ING_RATE_CTRL1
5.7.150 PORT0_ING_RATE_CTRL2
5.7.151 PORT1_ING_RATE_CTRL0
5.7.152 PORT1_ING_RATE_CTRL1
5.7.153 PORT1_ING_RATE_CTRL2
5.7.154 PORT2_ING_RATE_CTRL0
5.7.155 PORT2_ING_RATE_CTRL1
5.7.156 PORT2_ING_RATE_CTRL2
5.7.157 PORT3_ING_RATE_CTRL0
5.7.158 PORT3_ING_RATE_CTRL1
5.7.159 PORT3_ING_RATE_CTRL2
5.7.160 PORT4_ING_RATE_CTRL0
5.7.161 PORT4_ING_RATE_CTRL1
5.7.162 PORT4_ING_RATE_CTRL2
5.7.163 PORT5_ING_RATE_CTRL0
5.7.164 PORT5_ING_RATE_CTRL1
5.7.165 PORT5_ING_RATE_CTRL2
5.7.166 PORT6_ING_RATE_CTRL0
5.7.167 PORT6_ING_RATE_CTRL1
5.7.168 PORT6_ING_RATE_CTRL2
5.7.169 CPU_GROUP_CTRL
5.8 PKT edit register (offset range: 0x0C00–0x0C80)
5.8.1 PKT_EDIT_CTRL
5.8.2 PORT0_QUEUE_REMAP_REG0
5.8.3 PORT0_QUEUE_REMAP_REG1
5.8.4 PORT1_QUEUE_REMAP_REG0
5.8.5 PORT2_QUEUE_REMAP_REG0
5.8.6 PORT3_QUEUE_REMAP_REG0
5.8.7 PORT4_QUEUE_REMAP_REG0
5.8.8 PORT5_QUEUE_REMAP_REG0
5.8.9 PORT5_QUEUE_REMAP_REG1
5.8.10 PORT6_QUEUE_REMAP_REG0
5.8.11 PORT6_QUEUE_REMAP_REG1
5.8.12 Router default VID register 0
5.8.13 Router default VID register 1
5.8.14 Router default VID register 2
5.8.15 Router default VID register 3
5.8.16 Router egress VLAN mode
5.9 Layer 3 register (offset range: 0x0E00–0x0E98)
5.9.1 HROUTER_CONTROL
5.9.2 HROUTER_PBASED_CONTROL0
5.9.3 HROUTER_PBASED_CONTROL1
5.9.4 HROUTER_PBASED_CONTROL2
5.9.5 WCMP_HASH_TABLE0
5.9.6 WCMP_HASH_TABLE1
5.9.7 WCMP_HASH_TABLE2
5.9.8 WCMP_HASH_TABLE3
5.9.9 WCMP_NHOP_TABLE0
5.9.10 WCMP_NHOP_TABLE1
5.9.11 WCMP_NHOP_TABLE2
5.9.12 WCMP_NHOP_TABLE3
5.9.13 ARP_ENTRY_LOCK_CONTROL
5.9.14 ARP_USED_ACCOUNT
5.9.15 HNAT_CONTROL
5.9.16 NAPT_ENTRY_LOCK_CONTROL0
5.9.17 NAPT_ENTRY_LOCK_CONTROL1
5.9.18 NAPT_USED_ACCOUNT
5.9.19 ENTRY_EDIT_DATA0
5.9.20 ENTRY_EDIT_DATA1
5.9.21 ENTRY_EDIT_DATA2
5.9.22 ENTRY_EDIT_DATA3
5.9.23 ENTRY_EDIT_DATA4
5.9.24 ENTRY_EDIT_DATA5
5.9.25 ENTRY_EDIT_DATA6
5.9.26 ENTRY_EDIT_CONTROL
5.10 PHY control registers
5.10.1 Control register
5.10.2 Status Register
5.10.3 PHY identifier
5.10.4 PHY Identifier 2
5.10.5 Auto-negotiation advertisement register
5.10.6 Link partner ability register
5.10.7 Auto-negotiation expansion register
5.10.8 Next page transmit register
5.10.9 Link partner next page register
5.10.10 1000BASE-T control register
5.10.11 1000BASE-T status register
5.10.12 MMD access control register
5.10.13 MMD access address data register
5.10.14 Extended status register
5.10.15 Function control register
5.10.16 PHY-specific status register
5.10.17 Interrupt enable register
5.10.18 Interrupt status register
5.10.19 Smart speed register
5.10.20 Receive error counter register
5.10.21 Virtual cable tester control register
5.10.22 Virtual cable tester status register
5.10.23 Debug port
5.10.24 Debug port 2 (R/W port)
5.11 Debug register
5.11.1 Analog test control
5.11.2 System mode control
5.11.3 System control mode
5.11.4 HIB control and auto-negotiation test register
5.11.5 RGMII mode selection
5.11.6 Green feature configure register
5.12 MMD3 — PCS register
5.12.1 PCS control1
5.12.2 PCS status1
5.12.3 EEE capability register
5.12.4 EEE wake error counter
5.13 MMD7 — auto-negotiation register
5.13.1 AN package
5.13.2 AN status
5.13.3 AN XNP transmit
5.13.4 AN XNP transmit1
5.13.5 AN XNP transmit 2
5.13.6 AN LP XNP ability
5.13.7 AN LP XNP ability1
5.13.8 AN LP XNP ability2
5.13.9 EEE advertisement
5.13.10 EEE LP advertisement
5.13.11 EEE ability auto-negotiation result
6 Package Dimensions
7 Ordering Information
8 Top-Side Marking