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design complier 中文教程.pdf

发布时间：2022-05-30 发布人：admin 分类：说明书 资料大小：0.93M 资料格式：pdf 举报 版权申诉
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    ADVANCED ASIC CHIP SYNTHESIS
    提纲
    综合的定义
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    ASIC design flow
    DC介绍
    Script 文件
    DC支持的对象、变量、属性
    DC支持的对象、变量、属性
    DC支持的对象、变量、属性
    DC支持的对象、变量、属性
    DC支持的对象、变量、属性
    DC的文件格式及类型
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Synopsys technology library
    Partitioning for synthesis
    Partitioning for synthesis
    Partitioning for synthesis
    Partitioning for synthesis
    Partitioning for synthesis
    综合环境建立
    综合环境建立
    综合环境建立
    综合环境建立
    逻辑综合的过程
    RTL design Entry
    Environment constraints
    Environment constraints
    Environment constraints
    Environment constraints
    Environment constraints
    Environment constraints
    Environment constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    design and clock constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Advanced constraints
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Compilation Strategies
    Optimizing design
    Optimizing design
    Optimizing design
    Optimization design
    Optimization Techniques
    Optimization Techniques
    Optimization Techniques
    Optimization Techniques
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    Design For Test
    LINKS TO LAYOUT AND POST LAYOUT OPTIMIZATION
    Layout的网表生成
    Layout的网表生成
    Layout的网表生成
    Layout的网表生成
    Layout的网表生成
    Layout
    Layout
    Layout
    Layout
    Layout
    Layout
    Layout
    Layout
    EXTRACTION
    EXTRACTION
    POST LAYOUT OPTIMIZATION
    POST LAYOUT OPTIMIZATION
    POST LAYOUT OPTIMIZATION
    POST LAYOUT OPTIMIZATION
    POST LAYOUT OPTIMIZATION
    POST LAYOUT OPTIMIZATION
    Fix Hold-time Violation
    Fix Hold-time Violation
    Fix Hold-time Violation
    Fix Hold-time Violation
    SDF文件的产生
    SDF文件的产生
    SDF文件的产生
    SDF文件的产生
    ADVANCED ASIC CHIP SYNTHESIS
    提纲 综合的定义 ASIC design flow Synopsys Design Compiler的介绍 Synopsys technology library Logic synthesis的过程 Synthesis 和 layout的接口——LTL Post_layout optimization SDF文件的生成
    综合的定义 逻辑综合：决定设计电路逻辑门的相互连接。 逻辑综合的目的：决定电路门级结构、寻求时序和与面积的平 衡、寻求功耗与时序的平衡、增强电路的测试性。 逻辑综合的过程：首先，综合工具分析HDL代码，用一种模型 (GTECH) ，对HDL进行映射，这个模型是与技术库无关的；然后， 在设计者的控制下，对这个模型进行逻辑优化；最后一步，进行 逻辑映射和门级优化，将逻辑根据约束，映射为专门的技术目标 单元库（target cell library）中的cell，形成了综合后的网 表。
    ASIC design flow IP and Library Models Verified RTL Design Constraints Logic Synthesis optimization&scan insertion Static Timing Analysis no Time ok? Floorplan placement, CT Insertion&Global routing Transfer clock tree to DC Formal verification Post global route Static Timing Analysis Time ok? no Detail routing Post-layout Optimization (in-place optimization(IPO)) Static Timing Analysis no Time ok? Tape out
    ASIC design flow 设计举例，tap控制器，已完成代码编写及功能仿真： Tap_controller.v Tap_bypass.v Tap_instruction.v Tap_state.v 完成全部设计还需经过如下几个步骤： Pre_layout Synthesis STA using PrimeTime SDF generation Verification Floorolanning and Routing Post_layout 反标来自layout tool的信息， STA using PrimeTime Post-layout Optimization Fix Hold-Time Violation
    ASIC design flow Initial Setup :建立设计环境，技术库文件及其它设计环境设置。 DC .synopsys_dc.setup 文件 company =“zte corporation”; designer =“name”; technology=“0.25 micron” search_path=search_path+{“.” “/usr/golden/library/std_cells”\ “/usr/golden /library/pads”} target_library ={std_cells_lib.db} link_library ={“*”,std_cells_lib.db,pad_lib.db} symbol_library ={std_cells.sdb,pad_lib.sdb}
    ASIC design flow Synthesis:利用约束完成设计的门及实现及扫描插入 Constrain scripts /* Create real clock if clock port is found */ if (find(port, clk) == {"clk"}) { clk_name = clk create_clock -period clk_period clk } /* Create virtual clock if clock port is not found */ if (find(port, clk) == {}) { clk_name = vclk create_clock -period clk_period -name vclk }
    ASIC design flow Constrain scripts（续） /* Apply default drive strengths and typical loads for I/O ports */ set_load 1.5 all_outputs() set_driving_cell -cell IV all_inputs() /* If real clock, set infinite drive strength */ if (find(port, clk) == {"clk"}) { set_drive 0 clk } /* Apply default timing constraints for modules */ set_input_delay 1.2 all_inputs() -clock clk_name set_output_delay 1.5 all_outputs() -clock clk_name set_clock_skew -minus_uncertainty 0.45 clk_name /* Set operating conditions */ set_operating_conditions WCCOM /* Turn on Auto Wireload selection Library must support this feature */ auto_wire_load_selection = true
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