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00008889-RTL9000AA_AN-VB_Datasheet_DRAFT_V1.4_136293.pdf
1. General Description
2. Features
3. Application Diagram
3.1. General Application Diagram
3.2. PTP Application Diagram
4. Block Diagram
5. Pin Assignments
5.1. RTL9000AA Pin Assignments (QFN-36)
5.2. RTL9000AN Pin Assignments (QFN-36)
6. Pin Descriptions
6.1. Transceiver Interface
6.2. Clock
6.3. MII
6.4. RMII
6.5. RGMII
6.6. LED / PTP Application Interface
6.7. Management Interface
6.8. Power and Ground
6.9. Hardware Strapping Configuration
7. Function Description
7.1. Transmitter
7.2. Receiver
7.3. Operating Modes (OP)
7.3.1. Operating Modes
7.3.2. Operating Mode Transition
7.4. Sleep Mechanism
7.5. Wake-up
7.5.1. Local Wake-up
7.5.2. Remote Wake-up
7.6. Precision Time Protocol (PTP)
7.6.1. Synchronized PTP Clock
7.6.2. Packet Time Stamping
7.6.2.1 One-Step and Hardware-assisted Two-Step Operation
7.6.3. Time Application Interface (TAI)
7.6.4. PTP Function Configuration
7.6.4.1 Enable & Disable PTP Function
7.6.4.2 PTP Synchronization mechanism
7.6.4.3 PTP TAI configuration
7.6.4.4 PTP Reference Clock Input
7.6.5. Flow of PTP Sample
7.6.5.1 802.1AS Two-Step Sample Flow Chart
7.6.5.2 PTPv2 One-Step Sample Flow Chart
7.7. Interrupt
7.8. Hardware Configuration
7.9. MAC/PHY Interface
7.9.1. MII
7.9.2. RMII
7.9.3. RGMII
7.9.4. Management Interface
7.9.5. Register Access
7.9.5.1 Normal Register Access
7.9.5.2 Special Register Access
7.10. Polarity Correction
7.11. Spread Spectrum Clock (SSC)
7.12. Realtek Cable Test Diagnostics (RTCT)
7.12.1. RTCT Method
7.12.2. Cable length Checking Method (in Normal Operating Mode Only)
7.13. Signal Quality Indexes (SQI)
7.13.1. Signal-to-Noise-Ratio (SNR)
7.13.2. Maximum Error
7.14. LED
7.15. UNH IOL Test
7.15.1. Test mode 1
7.15.2. Test mode 2
7.15.3. Test mode 4
7.15.4. Test mode 5
7.15.5. SLAVE Jitter
8. Register Descriptions
8.1. IEEE Standard Register Mapping and Definitions
8.2. General Register Tables
8.2.1. BMCR (Basic Mode Control Register, Page 0x0, Reg 0x00)
8.2.2. BMSR (Basic Mode Status Register, Page 0x0, Reg 0x01)
8.2.3. PHYID1 (PHY Identifier Register 1, Page 0x0, Reg 0x02)
8.2.4. PHYID2 (PHY Identifier Register 2, Page 0x0, Reg 0x03)
8.2.5. PHYCR (PHY Control Register, Page 0x0, Reg 0x09)
8.2.6. PHYSR1 (PHY Status Register 1, Page 0x0, Reg 0x0A)
8.2.7. MACR (MMD Access Control Register, Page 0x0, Reg 0x0D)
8.2.8. MAADR (MMD Access Address Data Register, Page 0x0, Reg 0x0E)
8.2.9. PHYSFR (PHY Status Sub-flag Register, Page 0xa42, Reg 0x10)
8.2.10. RTCTCR (RTCT Control Register, Page 0xa42, Reg 0x11)
8.2.11. GINER (General Interrupt Enable Register, Page 0xa42, Reg 0x12)
8.2.12. GINMR (General Interrupt Mask Register, Page 0xa42, Reg 0x14)
8.2.13. SLPCR (Sleep Control Register, Page 0xa42, Reg 0x15)
8.2.14. LKTCR (Link Timer Control Register, Page 0xa42, Reg 0x16)
8.2.15. PHYCR (PHY Specific Control Register, Page 0xa43, Reg 0x18)
8.2.16. PHYSR2 (PHY Status Register 2, Page 0xa43, Reg 0x1A)
8.2.17. PHYSRAD (PHY SRAM Address Register, Page 0xa43, Reg 0x1B)
8.2.18. PHYSRD (PHY SRAM Data Register, Page 0xa43, Reg 0x1C)
8.2.19. GINSR (General Interrupt Status Register, Page 0xa43, Reg 0x1D)
8.2.20. PAGSR (Page Select Register, Page 0xa43, Reg 0x1F)
8.2.21. GPSFR (General Purpose Sub-flag Register, Page 0xa47, Reg 0x15)
8.2.22. SLPCAP (Sleep Capability Register, Page 0xa5a, Reg 0x14)
8.2.23. SLR (Scrambler Lock Register, Page 0xa60, Reg 0x11)
8.2.24. PCR (Polarity Correction Register, Page 0xa60, Reg 0x14)
8.2.25. LKTR(Link Timer Register, Page 0xa61, Reg 0x10)
8.2.26. SNRR(Signal to Noise Ratio Register, Address 0xa8c0)
8.2.27. MERR(Maximum Error Register, Address 0xa8e0)
8.2.28. CLENR (Cable Length Register, Address 0xa890)
8.2.29. SSCCR (SSC Control Register, Address 0xd012)
8.2.30. RXDVCR (RXDV Control Register, Address 0xd050)
8.2.31. LEDCR (LED Control Register, Address 0xd040)
8.2.32. LED_PTP (LED/PTP_GPIO Select Register, Address 0xd42a)
8.3. PTP Register Tables
8.3.1. PTP_CTL (PTP Control Register, Address 0xe400)
8.3.2. PTP_INER (PTP Interrupt Enable Register, Address 0xe402)
8.3.3. PTP_INSR (PTP Interrupt Status Register, Address 0xe404)
8.3.4. PTP_CLK_CFG (PTP Clock Config Register, Address 0xe410)
8.3.5. PTP_CFG_NS_LO (PTP Time Config Nano-Sec Low Register, Address 0xe412)
8.3.6. PTP_CFG_NS_HI (PTP Time Config Nano-Sec High Register, Address 0xe414)
8.3.7. PTP_CFG_S_LO (PTP Time Config Sec Low Register, Address 0xe416)
8.3.8. PTP_CFG_S_MI (PTP Time Config Sec Mid Register, Address 0xe418)
8.3.9. PTP_ CFG_S_HI (PTP Time Config Sec High Register, Address 0xe41A)
8.3.10. PTP_TAI_CFG (PTP Application I/F Config Register, Address 0xe420)
8.3.11. PTP_TRIG_CFG (PTP Trigger Config Register, Address 0xe422)
8.3.12. PTP_TAI_STA (PTP Application I/F Status Register, Address 0xe424)
8.3.13. PTP_TAI_TS_NS_LO (PTP TAI Timestamp Nano-Sec Low Register, Address 0xe426)
8.3.14. PTP_TAI_TS_NS_HI (PTP TAI Timestamp Nano-Sec High Register, Address 0xe428)
8.3.15. PTP_TAI_TS_S_LO (PTP TAI Timestamp Sec Low Register, Address 0xe42a)
8.3.16. PTP_TAI_TS_S_HI (PTP TAI Timestamp Sec High Register, Address 0xe42c)
8.3.17. PTP_TRX_TS_STA (PTP TxRx Timestamp Status Register, Address 0xe430)
8.3.18. PTP_TRX_TS_INFO (PTP TxRx Timestamp Info Register, Address 0xe440)
8.3.19. PTP_TRX_TS_SH (PTP TxRx Timestamp Source Hash Register, Address 0xe442)
8.3.20. PTP_TRX_TS_SID (PTP TxRx Timestamp Seq ID Register, Address 0xe444)
8.3.21. PTP_ TRX_TS NS_LO (PTP TxRx Timestamp Nano-Sec Low Register, Address 0xe446)
8.3.22. PTP_ TRX_TS NS_HI (PTP TxRx Timestamp Nano-Sec High Register, Address 0xe448)
8.3.23. PTP_ TRX_TS S_LO (PTP TxRx Timestamp Sec Low Register, Address 0xe44a)
8.3.24. PTP_ TRX_TS S_MI (PTP TxRx Timestamp Sec Mid Register, Address 0xe44c)
8.3.25. PTP_ TRX_TS S_HI (PTP TxRx Timestamp Sec High Register, Address 0xe44e)
8.4. OP Register Tables
8.4.1. OPCR1 (OP Control Register 1, Address 0xDC0C)
8.4.2. OPCR2 (OP Control Register 2, Address 0xDD00)
8.4.3. OPCR3 (OP Control Register 3, Address 0xDD02)
8.4.4. OPINSR1 (OP Interrupt Status Register 1, Address 0xDD08)
8.4.5. OPINER1 (OP Interrupt Enable Register 1, Address 0xDD0C)
8.4.6. OPINMR1 (OP Interrupt Mask Register 1, Address 0xDD0E)
8.4.7. OPINSR2 (OP Interrupt Status Register 2, Address 0xDD10)
8.4.8. OPINER2 (OP Interrupt Enable Register 2, Address 0xDD14)
8.4.9. OPINMR2 (OP Interrupt Mask Register 2, Address 0xDD16)
8.4.10. OPINSR3 (OP Interrupt Status Register 3, Address 0xDD18)
8.4.11. OPINER3 (OP Interrupt Enable Register 3, Address 0xDD1C)
8.4.12. OPINMR3 (OP Interrupt Mask Register 3, Address 0xDD1E)
8.4.13. OPCR4 (OP Control Register 4, Address 0xDD20)
9. Power Sequence and Regulators
9.1. Power Sequence
9.2. Reset
10. Characteristics
10.1. Absolute Maximum Ratings
10.2. Recommended Operating Conditions
10.3. Thermal Characteristics
10.4. Power Dissipation
10.5. DC Characteristics
10.6. Over Temperature Protection
10.7. ESD
10.8. Crystal Requirements
10.9. Oscillator/External Clock Requirements
10.10. AC Characteristics
10.10.1. MDC/MDIO Timing
10.10.2. MII Transmission Cycle Timing
10.10.3. MII Reception Cycle Timing
10.10.4. RMII Transmission and Reception Cycle Timing
10.10.5. RGMII Timing Modes
11. Mechanical Dimensions
11.1. Mechanical Dimensions Notes
12. Ordering Information
WITH 100BASE-T1 TRANSCEIVER
INTEGRATED PRECISION AUTOMOTIVE PHY
RTL9000AA-VC
RTL9000AN-VC
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Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
PRELIMINARY DATASHEET
(CONFIDENTIAL: Development Partners Only)
Foton
Rev. 1.4
2017-08-25
COPYRIGHT
RTL9000AA-VC/RTL9000AN-VC
Datasheet
DISCLAIMER
TRADEMARKS
Draft1.2
2017/04/25
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
© 2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
Realtek confidential files
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Moved the 7.11 to 7.13
Revised 7.12. Realtek Cable Test Diagnostics (RTCT)
Revised 7.15 UNH IOL Test
Revised Table 9. Hardware Strapping Configuration
Revised Table15. Configuration Register Definitions
Revised Table 35. LKTCR (Link Timer Control Register, Page 0xa42, Address 0x16)
Added Table 90 Parameter setting for I/O Power Selection
Re-named Figure 11 and 12
Revised 7.4. Sleep Mechanism
Revised 7.11. Spread Spectrum Clock (SSC)
Revised 8.2.26. SSCCR (SSC Control Register, Page 0xd01, Address 0x11)
Revised 10.4. Power Dissipation
Revised 7.13 Realtek Cable Test Diagnostics
Revised 7.15.UNH IOL Test
Revised 8.2.5.PHYCR (PHY Control Register, Address 0x09)
Revised Table 97. Digital IO Characteristics
Revised the 7.3 Wake up
Change the order of Operating Modes, Sleep Mechanism and Wake up as 7.3 Operating
Modes, 7.4 Sleep Mechanism and 7.5 Wake up
Added the MSL and Weight into the 12. Ordering Information
Foton
REVISION HISTORY
Release Date
Revision
Draft 1.0
Draft1.1
2016/12/21
2017/03/21
Summary
Draft First Release
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
ii
Draft Rev 1.4
Release Date
Summary
RTL9000AA-VC/RTL9000AN-VC
Datasheet
Revision
Draft 1.3
2017/05/22
Draft 1.4
2017/08/25
Move PHY FSR to 8.2.9
Revised Figure 30
Revised 7.5.1 Remote Wake-up
Revised Figure 1
Revised 7.9.4. Management Interface
Revised 8.2.1. BMCR (Basic Mode Control Register, Address 0x00)
Revised 9.1. Power Sequence
Revised 9.2. Reset
Revised 1 General Description to claim the difference between RTL9000AA-VC and
RTL9000AN-VC
Revised 5 Pin Assignments
Revised 6.4 RGMII
Revised 6.9 Hardware Strapping Configuration
Revised 6.7 Management Interface
Revised 7.3 Operating Modes
Revised 7.4 Sleep Mechanism
Revised 7.5 Wake-up
Revised 7.6 Precision Time Protocol
Revised 7.8 Hardware Configuration
Revised 7.9.5 Register Access
Revised 7.10 Polarity Correction
Revised 7.12 Realtek Cable Test Diagnostics (RTCT)
Revised 7.13 Signal Quality Indexes
Revised 7.14 LED
Removed 8.1. IEEE Standard Register Mapping and Definitions
Revised 8.2 General Register Tables
Revised 8.3 PTP Register Tables
Revised 8.4 OP Register Tables
Revised 9 Power Sequence and Regulators
Revised 11. Mechanical Dimensions
Added RTL9000AN General Application Diagram in 3.
Added RTL9000AN Pin Assignment in 5.2.
Added RTL9000AN absolute maximum ratings in 10.1.
Added RTL9000AN Recommended Operating Conditions in 10.2.
Added RTL9000AN power dissipation table in 10.4.
Added RTL9000AN DC Characteristics in 10.5.
Added RTL9000AN ESD Criteria in 10.7.
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Foton
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
iii
Draft Rev 1.4
RTL9000AA-VC/RTL9000AN-VC
Datasheet
Table of Contents
3.1.
3.2.
5.1.
5.2.
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
7.1.
7.2.
7.3.
7.6.
7.
4.
5.
6.
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1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
FEATURES ......................................................................................................................................................................... 2
3. APPLICATION DIAGRAM ............................................................................................................................................. 3
GENERAL APPLICATION DIAGRAM .............................................................................................................................. 3
PTP APPLICATION DIAGRAM ....................................................................................................................................... 4
BLOCK DIAGRAM ........................................................................................................................................................... 5
PIN ASSIGNMENTS ......................................................................................................................................................... 6
RTL9000AA PIN ASSIGNMENTS (QFN-36) ................................................................................................................. 6
RTL9000AN PIN ASSIGNMENTS (QFN-36) ................................................................................................................. 7
PIN DESCRIPTIONS ........................................................................................................................................................ 8
TRANSCEIVER INTERFACE ............................................................................................................................................ 8
CLOCK ......................................................................................................................................................................... 8
MII .............................................................................................................................................................................. 8
RMII ............................................................................................................................................................................ 9
RGMII ....................................................................................................................................................................... 10
LED / PTP APPLICATION INTERFACE ......................................................................................................................... 10
MANAGEMENT INTERFACE ........................................................................................................................................ 10
POWER AND GROUND ................................................................................................................................................ 11
HARDWARE STRAPPING CONFIGURATION .................................................................................................................. 12
FUNCTION DESCRIPTION .......................................................................................................................................... 13
TRANSMITTER ............................................................................................................................................................ 13
RECEIVER................................................................................................................................................................... 13
OPERATING MODES (OP) ........................................................................................................................................... 14
7.3.1. Operating Modes .................................................................................................................................................. 14
7.3.2. Operating Mode Transition .................................................................................................................................. 16
7.4.
SLEEP MECHANISM .................................................................................................................................................... 18
7.5. WAKE-UP ................................................................................................................................................................... 21
7.5.1. Local Wake-up ...................................................................................................................................................... 21
7.5.2. Remote Wake-up ................................................................................................................................................... 23
PRECISION TIME PROTOCOL (PTP) ............................................................................................................................ 26
7.6.1.
Synchronized PTP Clock ...................................................................................................................................... 26
7.6.2. Packet Time Stamping .......................................................................................................................................... 27
7.6.3. Time Application Interface (TAI) ......................................................................................................................... 27
7.6.4. PTP Function Configuration ................................................................................................................................ 27
7.6.5. Flow of PTP Sample ............................................................................................................................................. 34
INTERRUPT ................................................................................................................................................................. 42
HARDWARE CONFIGURATION .................................................................................................................................... 45
MAC/PHY INTERFACE .............................................................................................................................................. 46
7.9.1. MII ........................................................................................................................................................................ 46
7.9.2. RMII ..................................................................................................................................................................... 46
7.9.3. RGMII ................................................................................................................................................................... 46
7.9.4. Management Interface .......................................................................................................................................... 46
7.9.5. Register Access ..................................................................................................................................................... 47
7.10.
POLARITY CORRECTION ............................................................................................................................................. 49
7.11.
SPREAD SPECTRUM CLOCK (SSC) ............................................................................................................................. 49
7.12. REALTEK CABLE TEST DIAGNOSTICS (RTCT) ........................................................................................................... 49
RTCT Method .................................................................................................................................................. 49
Foton
7.7.
7.8.
7.9.
7.12.1.
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
iv
Draft Rev 1.4
RTL9000AA-VC/RTL9000AN-VC
Datasheet
7.13.
7.12.2.
7.13.1.
7.13.2.
8.1.
8.2.
7.15.1.
7.15.2.
7.15.3.
7.15.4.
7.15.5.
Cable length Checking Method (in Normal Operating Mode Only) ................................................................ 50
SIGNAL QUALITY INDEXES (SQI)............................................................................................................................... 51
Signal-to-Noise-Ratio (SNR)............................................................................................................................ 51
Maximum Error ............................................................................................................................................... 51
7.14.
LED ........................................................................................................................................................................... 51
7.15. UNH IOL TEST .......................................................................................................................................................... 52
Test mode 1 ...................................................................................................................................................... 52
Test mode 2 ...................................................................................................................................................... 53
Test mode 4 ...................................................................................................................................................... 53
Test mode 5 ...................................................................................................................................................... 53
SLAVE Jitter .................................................................................................................................................... 53
8. REGISTER DESCRIPTIONS ......................................................................................................................................... 54
IEEE STANDARD REGISTER MAPPING AND DEFINITIONS .......................................................................................... 54
GENERAL REGISTER TABLES ..................................................................................................................................... 55
8.2.1. BMCR (Basic Mode Control Register, Page 0x0, Reg 0x00) ............................................................................... 55
8.2.2. BMSR (Basic Mode Status Register, Page 0x0, Reg 0x01)................................................................................... 56
8.2.3. PHYID1 (PHY Identifier Register 1, Page 0x0, Reg 0x02) .................................................................................. 56
8.2.4. PHYID2 (PHY Identifier Register 2, Page 0x0, Reg 0x03) .................................................................................. 56
8.2.5. PHYCR (PHY Control Register, Page 0x0, Reg 0x09) ......................................................................................... 57
8.2.6. PHYSR1 (PHY Status Register 1, Page 0x0, Reg 0x0A) ....................................................................................... 57
8.2.7. MACR (MMD Access Control Register, Page 0x0, Reg 0x0D) ............................................................................ 58
8.2.8. MAADR (MMD Access Address Data Register, Page 0x0, Reg 0x0E) ................................................................ 58
8.2.9. PHYSFR (PHY Status Sub-flag Register, Page 0xa42, Reg 0x10) ....................................................................... 58
RTCTCR (RTCT Control Register, Page 0xa42, Reg 0x11) ............................................................................ 59
8.2.10.
GINER (General Interrupt Enable Register, Page 0xa42, Reg 0x12) ............................................................. 59
8.2.11.
8.2.12.
GINMR (General Interrupt Mask Register, Page 0xa42, Reg 0x14) ............................................................... 60
SLPCR (Sleep Control Register, Page 0xa42, Reg 0x15) ................................................................................ 60
8.2.13.
LKTCR (Link Timer Control Register, Page 0xa42, Reg 0x16)....................................................................... 60
8.2.14.
PHYCR (PHY Specific Control Register, Page 0xa43, Reg 0x18)................................................................... 60
8.2.15.
8.2.16.
PHYSR2 (PHY Status Register 2, Page 0xa43, Reg 0x1A) .............................................................................. 61
PHYSRAD (PHY SRAM Address Register, Page 0xa43, Reg 0x1B) ............................................................... 61
8.2.17.
PHYSRD (PHY SRAM Data Register, Page 0xa43, Reg 0x1C)....................................................................... 61
8.2.18.
GINSR (General Interrupt Status Register, Page 0xa43, Reg 0x1D) .............................................................. 62
8.2.19.
8.2.20.
PAGSR (Page Select Register, Page 0xa43, Reg 0x1F) .................................................................................. 62
GPSFR (General Purpose Sub-flag Register, Page 0xa47, Reg 0x15) ............................................................ 62
8.2.21.
SLPCAP (Sleep Capability Register, Page 0xa5a, Reg 0x14) ......................................................................... 62
8.2.22.
SLR (Scrambler Lock Register, Page 0xa60, Reg 0x11) .................................................................................. 63
8.2.23.
PCR (Polarity Correction Register, Page 0xa60, Reg 0x14) ........................................................................... 63
8.2.24.
8.2.25.
LKTR(Link Timer Register, Page 0xa61, Reg 0x10) ....................................................................................... 63
SNRR(Signal to Noise Ratio Register, Address 0xa8c0) .................................................................................. 63
8.2.26.
MERR(Maximum Error Register, Address 0xa8e0) ........................................................................................ 64
8.2.27.
CLENR (Cable Length Register, Address 0xa890) .......................................................................................... 64
8.2.28.
8.2.29.
SSCCR (SSC Control Register, Address 0xd012) ............................................................................................ 64
RXDVCR (RXDV Control Register, Address 0xd050) ..................................................................................... 64
8.2.30.
LEDCR (LED Control Register, Address 0xd040) .......................................................................................... 64
8.2.31.
8.2.32.
LED_PTP (LED/PTP_GPIO Select Register, Address 0xd42a) ...................................................................... 65
PTP REGISTER TABLES .............................................................................................................................................. 66
8.3.1. PTP_CTL (PTP Control Register, Address 0xe400) ............................................................................................ 66
8.3.2. PTP_INER (PTP Interrupt Enable Register, Address 0xe402) ............................................................................ 66
8.3.3. PTP_INSR (PTP Interrupt Status Register, Address 0xe404) .............................................................................. 67
8.3.4. PTP_CLK_CFG (PTP Clock Config Register, Address 0xe410) ......................................................................... 67
8.3.5. PTP_CFG_NS_LO (PTP Time Config Nano-Sec Low Register, Address 0xe412) .............................................. 68
8.3.6. PTP_CFG_NS_HI (PTP Time Config Nano-Sec High Register, Address 0xe414) .............................................. 68
8.3.7. PTP_CFG_S_LO (PTP Time Config Sec Low Register, Address 0xe416) ........................................................... 68
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Foton
8.3.
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
v
Draft Rev 1.4
RTL9000AA-VC/RTL9000AN-VC
Datasheet
8.4.
8.3.8. PTP_CFG_S_MI (PTP Time Config Sec Mid Register, Address 0xe418) ........................................................... 68
8.3.9. PTP_ CFG_S_HI (PTP Time Config Sec High Register, Address 0xe41A) ......................................................... 68
PTP_TAI_CFG (PTP Application I/F Config Register, Address 0xe420) ....................................................... 69
8.3.10.
PTP_TRIG_CFG (PTP Trigger Config Register, Address 0xe422) ................................................................ 70
8.3.11.
8.3.12.
PTP_TAI_STA (PTP Application I/F Status Register, Address 0xe424) ......................................................... 70
PTP_TAI_TS_NS_LO (PTP TAI Timestamp Nano-Sec Low Register, Address 0xe426) ................................ 70
8.3.13.
PTP_TAI_TS_NS_HI (PTP TAI Timestamp Nano-Sec High Register, Address 0xe428) ................................ 71
8.3.14.
PTP_TAI_TS_S_LO (PTP TAI Timestamp Sec Low Register, Address 0xe42a) ............................................. 71
8.3.15.
8.3.16.
PTP_TAI_TS_S_HI (PTP TAI Timestamp Sec High Register, Address 0xe42c) ............................................. 71
PTP_TRX_TS_STA (PTP TxRx Timestamp Status Register, Address 0xe430) ................................................ 71
8.3.17.
PTP_TRX_TS_INFO (PTP TxRx Timestamp Info Register, Address 0xe440) ................................................ 72
8.3.18.
PTP_TRX_TS_SH (PTP TxRx Timestamp Source Hash Register, Address 0xe442) ....................................... 72
8.3.19.
PTP_TRX_TS_SID (PTP TxRx Timestamp Seq ID Register, Address 0xe444) ............................................... 73
8.3.20.
8.3.21.
PTP_ TRX_TS NS_LO (PTP TxRx Timestamp Nano-Sec Low Register, Address 0xe446) ............................. 73
PTP_ TRX_TS NS_HI (PTP TxRx Timestamp Nano-Sec High Register, Address 0xe448) ............................. 73
8.3.22.
PTP_ TRX_TS S_LO (PTP TxRx Timestamp Sec Low Register, Address 0xe44a) .......................................... 73
8.3.23.
PTP_ TRX_TS S_MI (PTP TxRx Timestamp Sec Mid Register, Address 0xe44c) ........................................... 74
8.3.24.
8.3.25.
PTP_ TRX_TS S_HI (PTP TxRx Timestamp Sec High Register, Address 0xe44e) ....................................... 74
OP REGISTER TABLES ................................................................................................................................................ 75
8.4.1. OPCR1 (OP Control Register 1, Address 0xDC0C) ............................................................................................ 75
8.4.2. OPCR2 (OP Control Register 2, Address 0xDD00) ............................................................................................. 75
8.4.3. OPCR3 (OP Control Register 3, Address 0xDD02) ............................................................................................. 76
8.4.4. OPINSR1 (OP Interrupt Status Register 1, Address 0xDD08) ............................................................................. 76
8.4.5. OPINER1 (OP Interrupt Enable Register 1, Address 0xDD0C) .......................................................................... 77
8.4.6. OPINMR1 (OP Interrupt Mask Register 1, Address 0xDD0E) ............................................................................ 78
8.4.7. OPINSR2 (OP Interrupt Status Register 2, Address 0xDD10) ............................................................................. 78
8.4.8. OPINER2 (OP Interrupt Enable Register 2, Address 0xDD14) ........................................................................... 79
8.4.9. OPINMR2 (OP Interrupt Mask Register 2, Address 0xDD16) ............................................................................. 79
OPINSR3 (OP Interrupt Status Register 3, Address 0xDD18) ........................................................................ 80
8.4.10.
OPINER3 (OP Interrupt Enable Register 3, Address 0xDD1C) ..................................................................... 80
8.4.11.
8.4.12.
OPINMR3 (OP Interrupt Mask Register 3, Address 0xDD1E) ....................................................................... 81
8.4.13.
OPCR4 (OP Control Register 4, Address 0xDD20) ........................................................................................ 81
POWER SEQUENCE AND REGULATORS ................................................................................................................ 82
POWER SEQUENCE ..................................................................................................................................................... 83
RESET ........................................................................................................................................................................ 83
CHARACTERISTICS ................................................................................................................................................. 85
10.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 85
10.2. RECOMMENDED OPERATING CONDITIONS ................................................................................................................. 85
THERMAL CHARACTERISTICS .................................................................................................................................... 86
10.3.
10.4.
POWER DISSIPATION .................................................................................................................................................. 86
10.5. DC CHARACTERISTICS ............................................................................................................................................... 87
10.6. OVER TEMPERATURE PROTECTION ............................................................................................................................ 90
10.7.
ESD ........................................................................................................................................................................... 91
10.8. CRYSTAL REQUIREMENTS .......................................................................................................................................... 92
10.9. OSCILLATOR/EXTERNAL CLOCK REQUIREMENTS ...................................................................................................... 92
10.10.
AC CHARACTERISTICS .......................................................................................................................................... 93
10.10.1. MDC/MDIO Timing......................................................................................................................................... 93
10.10.2. MII Transmission Cycle Timing ...................................................................................................................... 94
10.10.3. MII Reception Cycle Timing ............................................................................................................................ 95
RMII Transmission and Reception Cycle Timing ............................................................................................ 95
10.10.4.
10.10.5.
RGMII Timing Modes ...................................................................................................................................... 97
MECHANICAL DIMENSIONS ............................................................................................................................... 100
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Foton
9.
10.
9.1.
9.2.
11.
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
vi
Draft Rev 1.4
RTL9000AA-VC/RTL9000AN-VC
Datasheet
11.1. MECHANICAL DIMENSIONS NOTES .......................................................................................................................... 100
ORDERING INFORMATION ................................................................................................................................. 101
12.
List of Tables
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The document authorized to
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TABLE 1. TRANSCEIVER INTERFACE ........................................................................................................................................... 8
TABLE 2. CLOCK ......................................................................................................................................................................... 8
TABLE 3. MII .............................................................................................................................................................................. 8
TABLE 4. RMII ............................................................................................................................................................................ 9
TABLE 5. RGMII ....................................................................................................................................................................... 10
TABLE 6. PTP APPLICATION INTERFACE ................................................................................................................................... 10
TABLE 7. MANAGEMENT INTERFACE ........................................................................................................................................ 10
TABLE 8. POWER AND GROUND ................................................................................................................................................ 11
TABLE 9. HARDWARE STRAPPING CONFIGURATION ................................................................................................................. 12
TABLE 10. OVERVIEW OF THE OPERATING STATES ....................................................................................................................... 16
TABLE 11. SUMMARY OF PTP PACKET TYPES ............................................................................................................................ 31
TABLE 12. GENERAL INTERRUPTS AND SUB-FLAGS ...................................................................................................................... 43
TABLE 13. CONFIG PINS VS. CONFIGURATION REGISTER ............................................................................................................ 45
TABLE 14. CONFIGURATION REGISTER DEFINITIONS .................................................................................................................... 45
TABLE 15. MANAGEMENT FRAME FORMAT .................................................................................................................................. 46
TABLE 16. MANAGEMENT FRAME DESCRIPTION ........................................................................................................................... 46
TABLE 17. METHOD OF ACCESSING REGISTERS ............................................................................................................................ 48
TABLE 18. RTCT CABLE STATUS INDICATION.............................................................................................................................. 50
TABLE 19. SQI CLASSIFICATION ................................................................................................................................................... 51
TABLE 20. LED ............................................................................................................................................................................. 51
TABLE 21. REGISTER ACCESS TYPES ............................................................................................................................................ 54
TABLE 22. IEEE STANDARD REGISTER MAPPING AND DEFINITIONS ............................................................................................ 54
TABLE 23. BMCR (BASIC MODE CONTROL REGISTER, PAGE 0X0, REG 0X00) ............................................................................. 55
TABLE 24. BMSR (BASIC MODE STATUS REGISTER, PAGE 0X0, REG 0X01) ................................................................................ 56
TABLE 25. PHYID1 (PHY IDENTIFIER REGISTER 1, PAGE 0X0, REG 0X02) .................................................................................. 56
TABLE 26. PHYID2 (PHY IDENTIFIER REGISTER 2, PAGE 0X0, REG 0X03) .................................................................................. 56
TABLE 27. PHYCR (PHY CONTROL REGISTER, PAGE 0X0, REG 0X09) ........................................................................................ 57
TABLE 28. PHYSR1 (PHY STATUS REGISTER 1, PAGE 0X0, REG 0X0A)...................................................................................... 57
TABLE 29. MACR (MMD ACCESS CONTROL REGISTER, PAGE 0X0, REG 0X0D) ......................................................................... 58
TABLE 30. MAADR (MMD ACCESS ADDRESS DATA REGISTER, PAGE 0X0, REG 0X0E) ............................................................. 58
TABLE 31. PHYSFR (PHY STATUS SUB-FLAG REGISTER, PAGE 0XA42, REG 0X10) .................................................................... 58
TABLE 32. RTCTCR (RTCT CONTROL REGISTER, PAGE 0XA42, REG 0X11) ............................................................................... 59
TABLE 33. GINER (GENERAL INTERRUPT ENABLE REGISTER, PAGE 0XA42, REG 0X12) ............................................................. 59
TABLE 34. GINMR (GENERAL INTERRUPT MASK REGISTER, PAGE 0XA42, REG 0X14) ............................................................... 60
TABLE 35. SLPCR (SLEEP CONTROL REGISTER, PAGE 0XA42, REG 0X15) ................................................................................... 60
TABLE 36. LKTCR (LINK TIMER CONTROL REGISTER, PAGE 0XA42, REG 0X16) ........................................................................ 60
TABLE 37. PHYCR (PHY SPECIFIC CONTROL REGISTER, PAGE 0XA43, REG 0X18) ..................................................................... 60
TABLE 38. PHYSR2 (PHY STATUS REGISTER 2, PAGE 0XA43, REG 0X1A) ................................................................................. 61
TABLE 39. PHYSRAD (PHY SRAM ADDRESS REGISTER, PAGE 0XA43, REG 0X1B) .................................................................. 61
TABLE 40. PHYSRD (PHY SRAM DATA REGISTER, PAGE 0XA43, REG 0X1C) .......................................................................... 61
TABLE 41. GINSR (GENERAL INTERRUPT STATUS REGISTER, PAGE 0XA43, REG 0X1D) ............................................................. 62
TABLE 42. PAGSR (PAGE SELECT REGISTER, PAGE 0XA43, REG 0X1F) ...................................................................................... 62
TABLE 43. GPSFR (GENERAL PURPOSE SUB-FLAG REGISTER, PAGE 0XA47, REG 0X15) ............................................................. 62
Foton
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
vii
Draft Rev 1.4
RTL9000AA-VC/RTL9000AN-VC
Datasheet
TABLE 44. SLPCAP (SLEEP CAPABILITY REGISTER, PAGE 0XA5A, REG 0X14) ............................................................................ 62
PLCR (SCRAMBLER LOCK REGISTER, PAGE 0XA60, REG 0X11) ........................................................................... 63
TABLE 45.
TABLE 46.
PLCR (POLARITY CORRECTION REGISTER, PAGE 0XA60, REG 0X14) ................................................................... 63
TABLE 47. LKTR (LINK TIMER REGISTER, PAGE 0XA61, REG 0X10) ........................................................................................... 63
TABLE 48. SNRR (SIGNAL TO NOISE RATIO REGISTER, ADDRESS 0XA8C0) ................................................................................. 63
TABLE 49. MERR (MAXIMUM ERROR REGISTER, ADDRESS 0XA8E0) .......................................................................................... 64
TABLE 50. CLENR (CABLE LENGTH REGISTER, ADDRESS 0XA890) ............................................................................................ 64
TABLE 51. SSCCR (SSC CONTROL REGISTER, ADDRESS 0XD012) ............................................................................................... 64
TABLE 52. RXDVCR (RXDV CONTROL REGISTER, ADDRESS 0XD050) ...................................................................................... 64
TABLE 53. LEDCR (LED CONTROL REGISTER, ADDRESS 0XD040) ............................................................................................. 64
TABLE 54. LED_PTP (LED/PTP_GPIO SELECT REGISTER, ADDRESS 0XD42A) .......................................................................... 65
TABLE 55. PTP_CTL (PTP CONTROL REGISTER, ADDRESS 0XE400) ........................................................................................... 66
TABLE 56. PTP_INER (PTP INTERRUPT ENABLE REGISTER, ADDRESS 0XE402) ......................................................................... 66
TABLE 57. PTP_INSR (PTP INTERRUPT STATUS REGISTER, ADDRESS 0XE404) .......................................................................... 67
TABLE 58. PTP_CLK_CFG (PTP CLOCK CONFIG REGISTER, ADDRESS 0XE410) ........................................................................ 67
TABLE 59. PTP_CFG_NS_LO (PTP TIME CONFIG NANO-SEC LOW REGISTER, ADDRESS 0XE412) ............................................ 68
TABLE 60. PTP_CFG_NS_HI (PTP TIME CONFIG NANO-SEC HIGH REGISTER, ADDRESS 0XE414) ............................................ 68
TABLE 61. PTP_CFG_S_LO (PTP TIME CONFIG SEC LOW REGISTER, ADDRESS 0XE416) .......................................................... 68
TABLE 62. PTP_CFG_S_MI (PTP TIME CONFIG SEC MID REGISTER, ADDRESS 0XE418) ........................................................... 68
TABLE 63. PTP_S_HI (PTP TIME CONFIG SEC HIGH REGISTER, ADDRESS 0XE41A) ................................................................... 68
TABLE 64. PTP_TAI_CFG (PTP APPLICATION I/F CONFIG REGISTER, ADDRESS 0XE420) .......................................................... 69
TABLE 65. PTP_TRIG_CFG (PTP TRIGGER CONFIG REGISTER, ADDRESS 0XE422) .................................................................... 70
TABLE 66. PTP_TAI_STA (PTP APPLICATION I/F STATUS REGISTER, ADDRESS 0XE424) .......................................................... 70
TABLE 67. PTP_TAI_TS_NS_LO (PTP TAI TIMESTAMP NANO-SEC LOW REGISTER, ADDRESS 0XE426) .................................. 70
TABLE 68. PTP_TAI_TS_NS_HI (PTP TAI TIMESTAMP NANO-SEC HIGH REGISTER, ADDRESS 0XE428) .................................. 71
TABLE 69. PTP_S_LO (PTP TIME CONFIG SEC LOW REGISTER, ADDRESS 0XE42A) ................................................................... 71
TABLE 70. PTP_S_MI (PTP TIME CONFIG SEC MID REGISTER, ADDRESS 0XE42C) ..................................................................... 71
TABLE 71. PTP_TRX_TS_STA (PTP TXRX TIMESTAMP STATUS REGISTER, ADDRESS 0XE430) ................................................ 71
TABLE 72. PTP_TRX_TS_INFO (PTP TXRX TIMESTAMP INFO REGISTER, ADDRESS 0XE440) ................................................... 72
TABLE 73. PTP_TRX_TS_SH (PTP TXRX TIMESTAMP SOURCE HASH REGISTER, ADDRESS 0XE442)........................................ 72
TABLE 74. PTP_TRX_TS_SID (PTP TXRX TIMESTAMP SEQ ID REGISTER, ADDRESS 0XE444) .................................................. 73
TABLE 75. PTP_ TRX_TS NS_LO (PTP TXRX TIMESTAMP NANO-SEC LOW REGISTER, ADDRESS 0XE446) .............................. 73
TABLE 76. PTP_ TRX_TS NS_HI (PTP TXRX TIMESTAMP NANO-SEC HIGH REGISTER, ADDRESS 0XE448) .............................. 73
TABLE 77. PTP_ TRX_TS S_LO (PTP TXRX TIMESTAMP SEC LOW REGISTER, ADDRESS 0XE44A) ........................................... 73
TABLE 78. PTP_ TRX_TS S_MID (PTP TXRX TIMESTAMP SEC MID REGISTER, ADDRESS 0XE44C) .......................................... 74
TABLE 79. PTP_ TRX_TS S_LO (PTP TXRX TIMESTAMP SEC HIGH REGISTER, ADDRESS 0XE44E) ........................................... 74
TABLE 80. OPCR1 (OP CONTROL REGISTER 1, ADDRESS 0XDC0C) ............................................................................................ 75
TABLE 81. OPCR2 (OP CONTROL REGISTER 2, ADDRESS 0XDD00) ............................................................................................ 75
TABLE 82. OPCR3 (OP CONTROL REGISTER 3, ADDRESS 0XDD02) ............................................................................................ 76
TABLE 83. OPINSR1 (OP INTERRUPT STATUS REGISTER 1, ADDRESS 0XDD08) ......................................................................... 76
TABLE 84. OPINER1 (OP INTERRUPT ENABLE REGISTER 1, ADDRESS 0XDD0C) ........................................................................ 77
TABLE 85. OPINMR1 (OP INTERRUPT MASK REGISTER 1, ADDRESS 0XDD0E) .......................................................................... 78
TABLE 86. OPINSR2 (OP INTERRUPT STATUS REGISTER 2, ADDRESS 0XDD10) ......................................................................... 78
TABLE 87. OPINER2 (OP INTERRUPT ENABLE REGISTER 2, ADDRESS 0XDD14) ........................................................................ 79
TABLE 88. OPINMR2 (OP INTERRUPT MASK REGISTER 2, ADDRESS 0XDD16) .......................................................................... 79
TABLE 89. OPINSR3 (OP INTERRUPT STATUS REGISTER 3, ADDRESS 0XDD18) ......................................................................... 80
TABLE 90. OPINER3 (OP INTERRUPT ENABLE REGISTER 3, ADDRESS 0XDD1C) ........................................................................ 80
TABLE 91. OPINMR3 (OP INTERRUPT MASK REGISTER 3, ADDRESS 0XDD1E) .......................................................................... 81
TABLE 92. OPCR4 (OP CONTROL REGISTER 4, ADDRESS 0XDD20) ............................................................................................ 81
TABLE 93. PARAMETER SETTING FOR I/O POWER SELECTION ....................................................................................................... 82
TABLE 94. POWER SEQUENCE PARAMETERS ................................................................................................................................. 83
TABLE 95. PHY RESET SIGNAL TIMING PARAMETER ................................................................................................................... 84
TABLE 96. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 85
TABLE 97. RECOMMENDED OPERATING CONDITIONS ................................................................................................................... 85
TABLE 98. THERMAL CHARACTERISTICS ...................................................................................................................................... 86
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The document authorized to
2018-01-18 13:42:02
Foton
Integrated Precision Automotive PHY with 100BASE-T1 Transceiver
viii
Draft Rev 1.4
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