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MIPI CSI-2 specification v3-0.pdf 2019最新版
Contents
Figures
Tables
Release History
1 Introduction
1.1 Scope
1.2 Purpose
2 Terminology
2.1 Use of Special Terms
2.2 Definitions
2.3 Abbreviations
2.4 Acronyms
3 References
4 Overview of CSI-2
5 CSI-2 Layer Definitions
6 Camera Control Interface (CCI)
6.1 CCI (I2C) Data Transfer Protocol
6.1.1 CCI (I2C) Message Type
6.1.2 CCI (I2C) Read/Write Operations
6.2 CCI (I3C) Data Transfer Protocol
6.2.1 CCI (I3C SDR) Data Transfer Protocol
6.2.1.1 CCI (I3C SDR) Message Type
6.2.1.2 CCI (I3C SDR) Read/Write Operations
6.2.2 CCI (I3C DDR) Data Transfer Protocol
6.2.2.1 CCI (I3C DDR) Message Type
6.2.2.2 CCI (I3C DDR) Read/Write Operations
6.3 CCI (I3C) Error Detection and Recovery
6.3.1 CCI (I3C SDR) Error Detection and Recovery Method
6.3.2 CCI (I3C DDR) Error Detection and Recovery Method
6.3.3 Error Detection and Recovery for CCI (I3C) Master Devices
6.4 CCI (I2C) Slave Addresses
6.5 CCI (I3C) Slave Addresses
6.6 CCI Multi-Byte Registers
6.6.1 Overview
6.6.2 Transmission Byte Order for Multi-Byte Register Values
6.6.3 Multi-Byte Register Protocol (Informative)
6.7 CCI I/O Electrical and Timing Specifications
7 Physical Layer
7.1 D-PHY Physical Layer Option
7.2 C-PHY Physical Layer Option
7.3 PHY Support for the CSI-2 Unified Serial Link (USL) Feature
7.3.1 D-PHY Support Requirements for USL Feature
7.3.2 C-PHY Support Requirements for USL Feature
8 Multi-Lane Distribution and Merging
8.1 Lane Distribution for the D-PHY Physical Layer Option
8.2 Lane Distribution for the C-PHY Physical Layer Option
8.3 Multi-Lane Interoperability
8.3.1 C-PHY Lane De-Skew
9 Low Level Protocol
9.1 Low Level Protocol Packet Format
9.1.1 Low Level Protocol Long Packet Format
9.1.2 Low Level Protocol Short Packet Format
9.2 Data Identifier (DI)
9.3 Virtual Channel Identifier
9.4 Data Type (DT)
9.5 Packet Header Error Correction Code for D-PHY Physical LayerOption
9.5.1 General Hamming Code Applied to Packet Header
9.5.2 Hamming-Modified Code
9.5.3 ECC Generation on TX Side
9.5.4 Applying ECC on RX Side (Informative)
9.6 Checksum Generation
9.7 Packet Spacing
9.8 Synchronization Short Packet Data Type Codes
9.8.1 Frame Synchronization Packets
9.8.2 Line Synchronization Packets
9.9 Generic Short Packet Data Type Codes
9.10 Packet Spacing Examples Using the Low Power State
9.11 Latency Reduction and Transport Efficiency (LRTE)
9.11.1 Interpacket Latency Reduction (ILR)
9.11.2 Using ILR and Enhanced Transport Efficiency Together
9.11.3 LRTE Register Tables
9.12 Unified Serial Link (USL)
9.12.1 USL Technical Overview
9.12.2 USL Command Payload Constructs
9.12.3 USL Operation Procedures
9.12.4 Monitoring USL Command Transport Integrity
9.12.5 USL Powerup / Reset, SNS Configuration, and Mode Switching
9.13 Data Scrambling
9.13.1 CSI-2 Scrambling for D-PHY
9.13.2 CSI-2 Scrambling for C-PHY
9.13.3 Scrambling Details
9.14 Smart Region of Interest (SROI)
9.14.1 Overview of SROI Frame Format
9.14.2 Transmission of SROI Embedded Data Packet
9.14.3 SROI Packet Detection Options
9.14.4 SROI Use Cases (Informative)
9.14.5 Format of SROI Embedded Data Packet (SEDP)
9.15 Packet Data Payload Size Rules
9.16 Frame Format Examples
9.17 Data Interleaving
9.17.1 Data Type Interleaving
9.17.2 Virtual Channel Identifier Interleaving
10 Color Spaces
10.1 RGB Color Space Definition
10.2 YUV Color Space Definition
11 Data Formats
11.1 Generic 8-bit Long Packet Data Types
11.1.1 Null and Blanking Data
11.1.2 Embedded Information
11.1.3 Generic Long Packet Data Types 1 Through 4
11.2 YUV Image Data
11.2.1 Legacy YUV420 8-bit
11.2.2 YUV420 8-bit
11.2.3 YUV420 10-bit
11.2.4 YUV422 8-bit
11.2.5 YUV422 10-bit
11.3 RGB Image Data
11.3.1 RGB888
11.3.2 RGB666
11.3.3 RGB565
11.3.4 RGB555
11.3.5 RGB444
11.4 RAW Image Data
11.4.1 RAW6
11.4.2 RAW7
11.4.3 RAW8
11.4.4 RAW10
11.4.5 RAW12
11.4.6 RAW14
11.4.7 RAW16
11.4.8 RAW20
11.4.9 RAW24
11.5 User Defined Data Formats
12 Recommended Memory Storage
12.1 General/Arbitrary Data Reception
12.2 RGB888 Data Reception
12.3 RGB666 Data Reception
12.4 RGB565 Data Reception
12.5 RGB555 Data Reception
12.6 RGB444 Data Reception
12.7 YUV422 8-bit Data Reception
12.8 YUV422 10-bit Data Reception
12.9 YUV420 8-bit (Legacy) Data Reception
12.10 YUV420 8-bit Data Reception
12.11 YUV420 10-bit Data Reception
12.12 RAW6 Data Reception
12.13 RAW7 Data Reception
12.14 RAW8 Data Reception
12.15 RAW10 Data Reception
12.16 RAW12 Data Reception
12.17 RAW14 Data Reception
12.18 RAW16 Data Reception
12.19 RAW20 Data Reception
12.20 RAW24 Data Reception
Annex A JPEG8 Data Format (informative)
A.1 Introduction
A.2 JPEG Data Definition
A.3 Image Status Information
A.4 Embedded Images
A.5 JPEG8 Non-standard Markers
A.6 JPEG8 Data Reception
Annex B CSI-2 Implementation Example (informative)
B.1 Overview
B.2 CSI-2 Transmitter Detailed Block Diagram
B.3 CSI-2 Receiver Detailed Block Diagram
B.4 Details on the DPHY Implementation
B.4.1 CSI-2 Clock Lane Transmitter
B.4.2 CSI-2 Clock Lane Receiver
B.4.3 CSI-2 Data Lane Transmitter
B.4.4 CSI-2 Data Lane Receiver
Annex C CSI-2 Recommended Receiver Error Behavior (informative)
C.1 Overview
C.2 D-PHY Level Error
C.3 Packet Level Error
C.4 Protocol Decoding Level Error
Annex D CSI-2 Sleep Mode (informative)
D.1 Overview
D.2 SLM Command Phase
D.3 SLM Entry Phase
D.4 SLM Exit Phase
Annex E Data Compression for RAW Data Types (normative)
E.1 Predictors
E.1.1 Predictor1
E.1.2 Predictor2
E.2 Encoders
E.2.1 Coder for 10–8–10 Data Compression
E.2.2 Coder for 10–7–10 Data Compression
E.2.3 Coder for 10–6–10 Data Compression
E.2.4 Coder for 12-10-12 Data Compression
E.2.5 Coder for 12–8–12 Data Compression
E.2.6 Coder for 12–7–12 Data Compression
E.2.7 Coder for 12–6–12 Data Compression
E.3 Decoders
E.3.1 Decoder for 10–8–10 Data Compression
E.3.2 Decoder for 10–7–10 Data Compression
E.3.3 Decoder for 10–6–10 Data Compression
E.3.4 Decoder for 12–10–12 Data Compression
E.3.5 Decoder for 12–8–12 Data Compression
E.3.6 Decoder for 12–7–12 Data Compression
E.3.7 Decoder for 12–6–12 Data Compression
Annex F JPEG Interleaving (informative)
Annex G Scrambler Seeds for Lanes 9 and Above
Annex H Guidance on CSI-2 Over C-PHY ALP and PPI
H.1 CSI-2 with C-PHY ALP Mode
H.1.1 Concepts of ALP Mode and Legacy LP Mode
H.1.2 Burst Examples Using ALP Mode
H.1.3 Transmission and Reception of ALP Commands Through the PPI
H.1.4 Multi-Lane Operation Using ALP Mode
H.1.5 LP and ALP Operation
H.1.6 Bi-Directional Lane Turnaround
Specification for
Camera Serial Interface 2
(CSI-2SM)
Version 3.0
31 May 2019
MIPI Board Adopted 10 September 2019
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to this MIPI
Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
Further technical changes to this document are expected as work continues in the PHY Working Group.
Copyright © 2005-2019 MIPI Alliance, Inc.
All rights reserved.
Confidential
Specification for CSI-2
Version 3.0
31-May-2019
NOTICE OF DISCLAIMER
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Attn: Managing Director
ii
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Version 3.0
31-May-2019
Specification for CSI-2
1.1
1.2
2.1
2.2
2.3
2.4
Contents
........................................................................................................................ viii
Figures
Tables
..........................................................................................................................xv
Release History .............................................................................................................. xvii
1
Introduction .................................................................................................................1
Scope ............................................................................................................................... 1
Purpose ............................................................................................................................ 1
2 Terminology .................................................................................................................2
Use of Special Terms ....................................................................................................... 2
Definitions ....................................................................................................................... 2
Abbreviations ................................................................................................................... 3
Acronyms ......................................................................................................................... 3
3 References ....................................................................................................................6
4 Overview of CSI-2 .......................................................................................................7
5 CSI-2 Layer Definitions ..............................................................................................9
6 Camera Control Interface (CCI) ............................................................................. 11
CCI (I2C) Data Transfer Protocol .................................................................................. 12
6.1.1 CCI (I2C) Message Type ............................................................................................. 12
6.1.2 CCI (I2C) Read/Write Operations ............................................................................... 13
CCI (I3C) Data Transfer Protocol .................................................................................. 19
6.2.1 CCI (I3C SDR) Data Transfer Protocol ...................................................................... 19
6.2.2 CCI (I3C DDR) Data Transfer Protocol ..................................................................... 27
CCI (I3C) Error Detection and Recovery ...................................................................... 37
6.3.1 CCI (I3C SDR) Error Detection and Recovery Method ............................................. 37
6.3.2 CCI (I3C DDR) Error Detection and Recovery Method ............................................ 39
6.3.3 Error Detection and Recovery for CCI (I3C) Master Devices .................................... 45
CCI (I2C) Slave Addresses ............................................................................................. 45
CCI (I3C) Slave Addresses ............................................................................................ 45
CCI Multi-Byte Registers .............................................................................................. 46
6.6.1 Overview ..................................................................................................................... 46
6.6.2 Transmission Byte Order for Multi-Byte Register Values .......................................... 48
6.6.3 Multi-Byte Register Protocol (Informative) ............................................................... 49
CCI I/O Electrical and Timing Specifications ............................................................... 53
7 Physical Layer ...........................................................................................................57
D-PHY Physical Layer Option ...................................................................................... 57
C-PHY Physical Layer Option ....................................................................................... 58
PHY Support for the CSI-2 Unified Serial Link (USL) Feature .................................... 59
7.3.1 D-PHY Support Requirements for USL Feature ......................................................... 59
7.3.2 C-PHY Support Requirements for USL Feature ......................................................... 60
6.4
6.5
6.6
6.7
7.1
7.2
7.3
6.1
6.2
6.3
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Specification for CSI-2
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9.6
9.7
9.8
9.2
9.3
9.4
9.5
8 Multi-Lane Distribution and Merging ....................................................................61
Lane Distribution for the D-PHY Physical Layer Option .............................................. 66
8.1
Lane Distribution for the C-PHY Physical Layer Option .............................................. 69
8.2
8.3 Multi-Lane Interoperability ........................................................................................... 71
8.3.1 C-PHY Lane De-Skew ................................................................................................ 73
9 Low Level Protocol ....................................................................................................75
Low Level Protocol Packet Format ............................................................................... 76
9.1.1 Low Level Protocol Long Packet Format ................................................................... 76
9.1.2 Low Level Protocol Short Packet Format ................................................................... 81
Data Identifier (DI) ........................................................................................................ 82
Virtual Channel Identifier .............................................................................................. 82
Data Type (DT) .............................................................................................................. 84
Packet Header Error Correction Code for D-PHY Physical Layer Option .................... 85
9.5.1 General Hamming Code Applied to Packet Header .................................................... 85
9.5.2 Hamming-Modified Code ........................................................................................... 86
9.5.3 ECC Generation on TX Side ....................................................................................... 90
9.5.4 Applying ECC on RX Side (Informative) .................................................................. 91
Checksum Generation .................................................................................................... 93
Packet Spacing ............................................................................................................... 95
Synchronization Short Packet Data Type Codes............................................................ 96
9.8.1 Frame Synchronization Packets .................................................................................. 96
9.8.2 Line Synchronization Packets ..................................................................................... 97
Generic Short Packet Data Type Codes ......................................................................... 99
Packet Spacing Examples Using the Low Power State ............................................... 100
Latency Reduction and Transport Efficiency (LRTE) ................................................. 103
9.11.1 Interpacket Latency Reduction (ILR) ....................................................................... 103
9.11.2 Using ILR and Enhanced Transport Efficiency Together ......................................... 113
9.11.3 LRTE Register Tables ............................................................................................... 114
9.12 Unified Serial Link (USL) ........................................................................................... 117
9.12.1 USL Technical Overview .......................................................................................... 118
9.12.2 USL Command Payload Constructs ......................................................................... 119
9.12.3 USL Operation Procedures ....................................................................................... 122
9.12.4 Monitoring USL Command Transport Integrity ....................................................... 124
9.12.5 USL Powerup / Reset, SNS Configuration, and Mode Switching ............................ 125
9.13 Data Scrambling .......................................................................................................... 137
9.13.1 CSI-2 Scrambling for D-PHY ................................................................................... 138
9.13.2 CSI-2 Scrambling for C-PHY ................................................................................... 139
9.13.3 Scrambling Details .................................................................................................... 142
Smart Region of Interest (SROI) ................................................................................. 147
9.14.1 Overview of SROI Frame Format............................................................................. 147
9.14.2 Transmission of SROI Embedded Data Packet ........................................................ 149
9.14.3 SROI Packet Detection Options................................................................................ 150
9.14.4 SROI Use Cases (Informative) ................................................................................. 152
9.14.5 Format of SROI Embedded Data Packet (SEDP) ..................................................... 154
Packet Data Payload Size Rules .................................................................................. 157
Frame Format Examples .............................................................................................. 158
9.9
9.10
9.11
9.1
9.14
9.15
9.16
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9.17 Data Interleaving ......................................................................................................... 161
9.17.1 Data Type Interleaving .............................................................................................. 161
9.17.2 Virtual Channel Identifier Interleaving ..................................................................... 164
10 Color Spaces.............................................................................................................165
10.1 RGB Color Space Definition ....................................................................................... 165
10.2 YUV Color Space Definition ....................................................................................... 165
11 Data Formats ...........................................................................................................167
11.1 Generic 8-bit Long Packet Data Types ........................................................................ 169
11.1.1 Null and Blanking Data ............................................................................................ 169
11.1.2 Embedded Information ............................................................................................. 170
11.1.3 Generic Long Packet Data Types 1 Through 4 ......................................................... 170
11.2 YUV Image Data ......................................................................................................... 171
11.2.1 Legacy YUV420 8-bit ............................................................................................... 171
11.2.2 YUV420 8-bit ........................................................................................................... 174
11.2.3 YUV420 10-bit ......................................................................................................... 178
11.2.4 YUV422 8-bit ........................................................................................................... 180
11.2.5 YUV422 10-bit ......................................................................................................... 182
11.3 RGB Image Data .......................................................................................................... 184
11.3.1 RGB888 .................................................................................................................... 185
11.3.2 RGB666 .................................................................................................................... 187
11.3.3 RGB565 .................................................................................................................... 189
11.3.4 RGB555 .................................................................................................................... 191
11.3.5 RGB444 .................................................................................................................... 192
11.4 RAW Image Data ......................................................................................................... 193
11.4.1 RAW6 ....................................................................................................................... 194
11.4.2 RAW7 ....................................................................................................................... 195
11.4.3 RAW8 ....................................................................................................................... 196
11.4.4 RAW10 ..................................................................................................................... 197
11.4.5 RAW12 ..................................................................................................................... 199
11.4.6 RAW14 ..................................................................................................................... 200
11.4.7 RAW16 ..................................................................................................................... 202
11.4.8 RAW20 ..................................................................................................................... 203
11.4.9 RAW24 ..................................................................................................................... 205
11.5 User Defined Data Formats ......................................................................................... 206
12 Recommended Memory Storage ............................................................................209
12.1 General/Arbitrary Data Reception ............................................................................... 209
12.2 RGB888 Data Reception ............................................................................................. 210
12.3 RGB666 Data Reception ............................................................................................. 210
12.4 RGB565 Data Reception ............................................................................................. 211
12.5 RGB555 Data Reception ............................................................................................. 211
12.6 RGB444 Data Reception ............................................................................................. 212
12.7 YUV422 8-bit Data Reception .................................................................................... 212
12.8 YUV422 10-bit Data Reception .................................................................................. 213
12.9 YUV420 8-bit (Legacy) Data Reception ..................................................................... 214
12.10 YUV420 8-bit Data Reception .................................................................................... 215
12.11 YUV420 10-bit Data Reception .................................................................................. 216
12.12 RAW6 Data Reception ................................................................................................. 217
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Specification for CSI-2
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B.1
B.2
B.3
B.4
A.1
A.2
A.3
A.4
A.5
A.6
12.13 RAW7 Data Reception ................................................................................................. 217
12.14 RAW8 Data Reception ................................................................................................. 218
12.15 RAW10 Data Reception ............................................................................................... 218
12.16 RAW12 Data Reception ............................................................................................... 219
12.17 RAW14 Data Reception ............................................................................................... 219
12.18 RAW16 Data Reception ............................................................................................... 220
12.19 RAW20 Data Reception ............................................................................................... 220
12.20 RAW24 Data Reception ............................................................................................... 221
Annex A JPEG8 Data Format (informative) .............................................................223
Introduction.................................................................................................................. 223
JPEG Data Definition .................................................................................................. 224
Image Status Information ............................................................................................ 225
Embedded Images ........................................................................................................ 227
JPEG8 Non-standard Markers ..................................................................................... 228
JPEG8 Data Reception ................................................................................................ 228
Annex B CSI-2 Implementation Example (informative) .........................................229
Overview...................................................................................................................... 229
CSI-2 Transmitter Detailed Block Diagram ................................................................ 230
CSI-2 Receiver Detailed Block Diagram ..................................................................... 231
Details on the D-PHY Implementation ........................................................................ 232
B.4.1 CSI-2 Clock Lane Transmitter .................................................................................. 233
B.4.2 CSI-2 Clock Lane Receiver ...................................................................................... 234
B.4.3 CSI-2 Data Lane Transmitter .................................................................................... 235
B.4.4 CSI-2 Data Lane Receiver ........................................................................................ 237
Annex C CSI-2 Recommended Receiver Error Behavior (informative) ................239
Overview...................................................................................................................... 239
D-PHY Level Error ...................................................................................................... 240
Packet Level Error ....................................................................................................... 241
Protocol Decoding Level Error .................................................................................... 242
Annex D CSI-2 Sleep Mode (informative) .................................................................243
Overview...................................................................................................................... 243
SLM Command Phase ................................................................................................. 243
SLM Entry Phase ......................................................................................................... 244
SLM Exit Phase ........................................................................................................... 244
Annex E Data Compression for RAW Data Types (normative) ..............................245
Predictors ..................................................................................................................... 247
E.1.1 Predictor1 .................................................................................................................. 247
E.1.2 Predictor2 .................................................................................................................. 248
Encoders ...................................................................................................................... 249
E.2.1 Coder for 10–8–10 Data Compression ..................................................................... 249
E.2.2 Coder for 10–7–10 Data Compression ..................................................................... 251
E.2.3 Coder for 10–6–10 Data Compression ..................................................................... 254
E.2.4 Coder for 12-10-12 Data Compression ..................................................................... 257
E.2.5 Coder for 12–8–12 Data Compression ..................................................................... 259
E.2.6 Coder for 12–7–12 Data Compression ..................................................................... 262
E.2.7 Coder for 12–6–12 Data Compression ..................................................................... 265
D.1
D.2
D.3
D.4
C.1
C.2
C.3
C.4
E.1
E.2
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E.3
Decoders ...................................................................................................................... 268
E.3.1 Decoder for 10–8–10 Data Compression .................................................................. 268
E.3.2 Decoder for 10–7–10 Data Compression .................................................................. 271
E.3.3 Decoder for 10–6–10 Data Compression .................................................................. 274
E.3.4 Decoder for 12–10–12 Data Compression ................................................................ 277
E.3.5 Decoder for 12–8–12 Data Compression .................................................................. 280
E.3.6 Decoder for 12–7–12 Data Compression .................................................................. 283
E.3.7 Decoder for 12–6–12 Data Compression .................................................................. 287
Annex F JPEG Interleaving (informative) ................................................................291
Annex G Scrambler Seeds for Lanes 9 and Above ....................................................293
Annex H Guidance on CSI-2 Over C-PHY ALP and PPI ........................................295
CSI-2 with C-PHY ALP Mode .................................................................................... 295
H.1.1 Concepts of ALP Mode and Legacy LP Mode ......................................................... 295
H.1.2 Burst Examples Using ALP Mode ............................................................................ 298
H.1.3 Transmission and Reception of ALP Commands Through the PPI .......................... 303
H.1.4 Multi-Lane Operation Using ALP Mode .................................................................. 308
H.1.5 LP and ALP Operation .............................................................................................. 310
H.1.6 Bi-Directional Lane Turnaround ............................................................................... 310
H.1
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Specification for CSI-2
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Figures
Figure 1 Typical CSI-2 and CCI Transmitter and Receiver Interface for D-PHY ............................ 7
Figure 2 Typical CSI-2 and CCI Transmitter and Receiver Interface for C-PHY ............................ 8
Figure 3 CSI-2 Layer Definitions ..................................................................................................... 9
Figure 4 CCI (I2C) Single Read from Random Location ............................................................... 13
Figure 5 CCI (I2C) Single Read from Current Location................................................................. 14
Figure 6 CCI (I2C) Sequential Read Starting from Random Location ........................................... 15
Figure 7 CCI (I2C) Sequential Read Starting from Current Location ............................................ 16
Figure 8 CCI (I2C) Single Write to Random Location ................................................................... 17
Figure 9 CCI (I2C) Sequential Write Starting from Random Location .......................................... 18
Figure 10 CCI (I3C SDR) Single Read from Random Location .................................................... 21
Figure 11 CCI (I3C SDR) Single Read from Current Location ..................................................... 22
Figure 12 CCI (I3C SDR) Sequential Read Starting from Random Location................................ 23
Figure 13 CCI (I3C SDR) Sequential Read Starting from Current Location ................................. 24
Figure 14 CCI (I3C SDR) Single Write to Random Location ........................................................ 25
Figure 15 CCI (I3C SDR) Sequential Write Starting from Random Location ............................... 26
Figure 16 CCI (I3C DDR) Sequential Read from Random Location: 8-bit LENGTH
& INDEX ....................................................................................................................... 30
Figure 17 CCI (I3C DDR) Sequential Read from Random Location: 16-bit LENGTH
& INDEX ....................................................................................................................... 31
Figure 18 CCI (I3C DDR) Concatenated Sequential Read, Random Location: 8-bit LENGTH
& INDEX ....................................................................................................................... 33
Figure 19 CCI (I3C DDR) Concatenated Sequential Read, Random Location: 16-bit LENGTH
& INDEX ....................................................................................................................... 34
Figure 20 CCI (I3C DDR) Sequential Write Starting from Random Location .............................. 36
Figure 21 Example of SS0 Error Detection .................................................................................... 38
Figure 22 Example of SD0 Error Detection ................................................................................... 40
Figure 23 Example of SD1 Error Detection ................................................................................... 42
Figure 24 Example of MD0 Error Detection .................................................................................. 44
Figure 25 Corruption of 32-bit Register During Read Message .................................................... 47
Figure 26 Corruption of 32-bit Register During Write Message .................................................... 47
Figure 27 Example 16-bit Register Write ....................................................................................... 48
Figure 28 Example 32-bit Register Write (Address Not Shown) ................................................... 48
Figure 29 Example 64-bit Register Write (Address Not Shown) ................................................... 48
Figure 30 Example 16-bit Register Read ....................................................................................... 49
Figure 31 Example 32-bit Register Read ....................................................................................... 50
Figure 32 Example 16-bit Register Write ....................................................................................... 51
viii
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