第1页 / 共3593页
第2页 / 共3593页
第3页 / 共3593页
第4页 / 共3593页
第5页 / 共3593页
第6页 / 共3593页
第7页 / 共3593页
第8页 / 共3593页
IMXRT1064RM.pdf
Chapter 1: Introduction
About This Document
Audience
Organization
Suggested Reading
General Information
Related Documentation
Conventions
Register Access
Register Diagram Field Access Type Legend
Register Macro Usage
Signal Conventions
Acronyms and Abbreviations
Introduction
Block Diagram
Features
Target Applications
Endianness Support
Chapter 2: Memory Maps
Memory system overview
ARM Platform Memory Map
Chapter 3-5: Interrupts and DMA
Chapter 3: Interrupts, DMA Events, and XBAR Assignments
Chip-specific Interrupt information
Overview
CM7 interrupts
DMA Mux
XBAR Resource Assignments
Chapter 4: Direct Memory Access Multiplexer (DMAMUX)
Chip-specific DMAMUX information
Introduction
Overview
Features
Modes of operation
External signal description
Functional description
DMA channels with periodic triggering capability
Always-enabled DMA sources
Initialization/application information
Reset
Enabling and configuring sources
Memory map/register definition
DMA_CH_MUX Register Descriptions
DMA_CH_MUX Memory Map
Channel a Configuration (CHCFGa)
Chapter 5: Enhanced Direct Memory Access (eDMA)
Chip-specific eDMA information
Introduction
eDMA system block diagram
Block parts
Features
Modes of operation
Functional description
eDMA basic data flow
Fault reporting and handling
Channel preemption
Initialization/application information
eDMA initialization
Programming errors
Arbitration mode considerations
Fixed group arbitration, Fixed channel arbitration
Fixed group arbitration, Round-robin channel arbitration
Performing DMA transfers
Single request
Multiple requests
Using the modulo feature
Monitoring transfer descriptor status
Testing for minor loop completion
Reading the transfer descriptors of active channels
Checking channel preemption status
Channel Linking
Dynamic programming
Dynamically changing the channel priority
Dynamic channel linking
Dynamic scatter/gather
Method 1 (channel not using major loop channel linking)
Method 2 (channel using major loop channel linking)
Suspend/resume a DMA channel with active hardware service requests
Suspend an active DMA channel
Resume a DMA channel
Memory map/register definition
TCD memory
TCD initialization
TCD structure
Reserved memory and bit fields
DMA register descriptions
DMA Memory map
Control Register (CR)
Error Status Register (ES)
Enable Request Register (ERQ)
Enable Error Interrupt Register (EEI)
Clear Enable Error Interrupt Register (CEEI)
Set Enable Error Interrupt Register (SEEI)
Clear Enable Request Register (CERQ)
Set Enable Request Register (SERQ)
Clear DONE Status Bit Register (CDNE)
Set START Bit Register (SSRT)
Clear Error Register (CERR)
Clear Interrupt Request Register (CINT)
Interrupt Request Register (INT)
Error Register (ERR)
Hardware Request Status Register (HRS)
Enable Asynchronous Request in Stop Register (EARS)
Channel Priority Register (DCHPRI0 - DCHPRI31)
TCD Source Address (TCD0_SADDR - TCD31_SADDR)
TCD Signed Source Address Offset (TCD0_SOFF - TCD31_SOFF)
TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR)
TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO - TCD31_NBYTES_MLNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD31_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBYTES_MLOFFYES - TCD31_NBYTES_MLOFFYES)
TCD Last Source Address Adjustment (TCD0_SLAST - TCD31_SLAST)
TCD Destination Address (TCD0_DADDR - TCD31_DADDR)
TCD Signed Destination Address Offset (TCD0_DOFF - TCD31_DOFF)
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_CITER_ELINKNO - TCD31_CITER_ELINKNO)
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD31_CITER_ELINKYES)
TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA - TCD31_DLASTSGA)
TCD Control and Status (TCD0_CSR - TCD31_CSR)
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_BITER_ELINKNO - TCD31_BITER_ELINKNO)
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_BITER_ELINKYES - TCD31_BITER_ELINKYES)
Chapter 6: System Security
Chapter overview
Feature summary
High-Assurance Boot (HAB)
HAB process flow
HAB feature summary
Secure Non-Volatile Storage (SNVS) module
SNVS architecture
Data Co-Processor (DCP)
Standalone True Random Number Generator (TRNG)
OCOTP_CTRL
Central Security Unit (CSU)
System JTAG Controller (SJC)
Scan protection
Bus Encryption Engine (BEE)
Chapter 7: System Debug
Overview
Chip and ARM Platform Debug Architecture
Debug Features
Debug system components
AMBA Trace Bus (ATB)
CoreSight trace port interface (TPIU)
Embedded Trace Macrocell (ETM)
Instrumentation Trace Macrocell
Chip-Specific SJC Features
JTAG Disable Mode
JTAG ID
System JTAG controller main features
SJC TAP Port
SJC main blocks
Miscellaneous
Clock/Reset/Power
Supported tools
Chapter 8: System Boot
Chip-specific Boot Information
Overview
Boot modes
Boot mode pin settings
High-level boot sequence
Boot From Fuses mode (BOOT_MODE[1:0] = 00b)
Serial Downloader (BOOT_MODE[1:0] = 01b)
Internal Boot mode (BOOT_MODE[1:0] = 0b10)
Boot security settings
Device configuration
Boot eFUSE descriptions
GPIO boot overrides
Device Configuration Data (DCD)
Device initialization
Internal ROM/RAM memory map
Boot block activation
Clocks at boot time
Enabling Caches
Exception handling
Interrupt handling during boot
Persistent bits
Boot devices (internal boot)
Serial NOR Flash Boot via FlexSPI
Serial NOR eFUSE Configuration
FlexSPI Serial NOR Flash Boot Operation
FlexSPI NOR boot flow chart
Serial NOR and NAND configuration based on FlexSPI interface
FlexSPI Configuration Block
Serial NOR configuration block (512 bytes)
Parallel NOR and NAND configuration based on SEMC interface
SEMC Configuration Block
Parallel NOR Configuration Block (80 bytes)
Parallel NAND Configuration Block (256 bytes)
Expansion device
Expansion device eFUSE configuration
MMC and eMMC boot
SD, eSD, and SDXC
IOMUX configuration for SD/MMC
Redundant boot support for expansion device
Serial NOR/EEPROM through LPSPI
Serial NOR/EEPROM eFUSE configuration
Program image
Image Vector Table and Boot Data
Image vector table structure
Boot data structure
Device Configuration Data (DCD)
Write data command
Check data command
NOP command
Unlock command
Plugin image
Serial Downloader
USB
USB configuration details
IOMUX configuration for USB
Serial Download Protocol (SDP)
SDP commands
READ_REGISTER
WRITE_REGISTER
WRITE_FILE
ERROR_STATUS
DCD_WRITE
JUMP_ADDRESS
SET_BAUDRATE
Recovery devices
SD/MMC manufacture mode
High-Assurance Boot (HAB)
HAB API vector table addresses
ROM APIs
Chapter 9-11: Chip IO
Chapter 9: External Signals and Pin Multiplexing
Overview
Muxing Options
Chapter 10: IOMUX Controller (IOMUXC)
Overview
Features
Clocks
Functional description
ALT6 and ALT7 extended muxing modes
SW Loopback through SION bit
Daisy chain - multi pads driving same module input pin
IOMUXC GPR Memory Map/Register Definition
IOMUXC_GPR
IOMUXC_GPR_GPR0
IOMUXC_GPR_GPR1
IOMUXC_GPR_GPR2
IOMUXC_GPR_GPR3
IOMUXC_GPR_GPR4
IOMUXC_GPR_GPR5
IOMUXC_GPR_GPR6
IOMUXC_GPR_GPR7
IOMUXC_GPR_GPR8
IOMUXC_GPR_GPR9
IOMUXC_GPR_GPR10
IOMUXC_GPR_GPR11
IOMUXC_GPR_GPR12
IOMUXC_GPR_GPR13
IOMUXC_GPR_GPR14
IOMUXC_GPR_GPR15
IOMUXC_GPR_GPR16
IOMUXC_GPR_GPR17
IOMUXC_GPR_GPR18
IOMUXC_GPR_GPR19
IOMUXC_GPR_GPR20
IOMUXC_GPR_GPR21
IOMUXC_GPR_GPR22
IOMUXC_GPR_GPR23
IOMUXC_GPR_GPR24
IOMUXC_GPR_GPR25
IOMUXC_GPR_GPR26
IOMUXC_GPR_GPR27
IOMUXC_GPR_GPR28
IOMUXC_GPR_GPR29
IOMUXC_GPR_GPR30
IOMUXC_GPR_GPR31
IOMUXC_GPR_GPR32
IOMUXC_GPR_GPR33
IOMUXC_GPR_GPR34
IOMUXC SNVS Memory Map/Register Definition
IOMUXC_SNVS
IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP
IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ
IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ
IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE
IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B
IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF
IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP
IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ
IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ
IOMUXC SNVS GPR Memory Map/Register Definition
IOMUXC_SNVS_GPR
IOMUXC_SNVS_GPR_GPR0
IOMUXC_SNVS_GPR_GPR1
IOMUXC_SNVS_GPR_GPR2
IOMUXC_SNVS_GPR_GPR3
IOMUXC Memory Map/Register Definition
IOMUXC
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
IOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
IOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
IOMUXC_CCM_PMIC_READY_SELECT_INPUT
IOMUXC_CSI_DATA02_SELECT_INPUT
IOMUXC_CSI_DATA03_SELECT_INPUT
IOMUXC_CSI_DATA04_SELECT_INPUT
IOMUXC_CSI_DATA05_SELECT_INPUT
IOMUXC_CSI_DATA06_SELECT_INPUT
IOMUXC_CSI_DATA07_SELECT_INPUT
IOMUXC_CSI_DATA08_SELECT_INPUT
IOMUXC_CSI_DATA09_SELECT_INPUT
IOMUXC_CSI_HSYNC_SELECT_INPUT
IOMUXC_CSI_PIXCLK_SELECT_INPUT
IOMUXC_CSI_VSYNC_SELECT_INPUT
IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
IOMUXC_ENET_MDIO_SELECT_INPUT
IOMUXC_ENET0_RXDATA_SELECT_INPUT
IOMUXC_ENET1_RXDATA_SELECT_INPUT
IOMUXC_ENET_RXEN_SELECT_INPUT
IOMUXC_ENET_RXERR_SELECT_INPUT
IOMUXC_ENET0_TIMER_SELECT_INPUT
IOMUXC_ENET_TXCLK_SELECT_INPUT
IOMUXC_FLEXCAN1_RX_SELECT_INPUT
IOMUXC_FLEXCAN2_RX_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
IOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
IOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
IOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
IOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
IOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
IOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
IOMUXC_FLEXSPIA_DQS_SELECT_INPUT
IOMUXC_FLEXSPIA_DATA0_SELECT_INPUT
IOMUXC_FLEXSPIA_DATA1_SELECT_INPUT
IOMUXC_FLEXSPIA_DATA2_SELECT_INPUT
IOMUXC_FLEXSPIA_DATA3_SELECT_INPUT
IOMUXC_FLEXSPIB_DATA0_SELECT_INPUT
IOMUXC_FLEXSPIB_DATA1_SELECT_INPUT
IOMUXC_FLEXSPIB_DATA2_SELECT_INPUT
IOMUXC_FLEXSPIB_DATA3_SELECT_INPUT
IOMUXC_FLEXSPIA_SCK_SELECT_INPUT
IOMUXC_LPI2C1_SCL_SELECT_INPUT
IOMUXC_LPI2C1_SDA_SELECT_INPUT
IOMUXC_LPI2C2_SCL_SELECT_INPUT
IOMUXC_LPI2C2_SDA_SELECT_INPUT
IOMUXC_LPI2C3_SCL_SELECT_INPUT
IOMUXC_LPI2C3_SDA_SELECT_INPUT
IOMUXC_LPI2C4_SCL_SELECT_INPUT
IOMUXC_LPI2C4_SDA_SELECT_INPUT
IOMUXC_LPSPI1_PCS0_SELECT_INPUT
IOMUXC_LPSPI1_SCK_SELECT_INPUT
IOMUXC_LPSPI1_SDI_SELECT_INPUT
IOMUXC_LPSPI1_SDO_SELECT_INPUT
IOMUXC_LPSPI2_PCS0_SELECT_INPUT
IOMUXC_LPSPI2_SCK_SELECT_INPUT
IOMUXC_LPSPI2_SDI_SELECT_INPUT
IOMUXC_LPSPI2_SDO_SELECT_INPUT
IOMUXC_LPSPI3_PCS0_SELECT_INPUT
IOMUXC_LPSPI3_SCK_SELECT_INPUT
IOMUXC_LPSPI3_SDI_SELECT_INPUT
IOMUXC_LPSPI3_SDO_SELECT_INPUT
IOMUXC_LPSPI4_PCS0_SELECT_INPUT
IOMUXC_LPSPI4_SCK_SELECT_INPUT
IOMUXC_LPSPI4_SDI_SELECT_INPUT
IOMUXC_LPSPI4_SDO_SELECT_INPUT
IOMUXC_LPUART2_RX_SELECT_INPUT
IOMUXC_LPUART2_TX_SELECT_INPUT
IOMUXC_LPUART3_CTS_B_SELECT_INPUT
IOMUXC_LPUART3_RX_SELECT_INPUT
IOMUXC_LPUART3_TX_SELECT_INPUT
IOMUXC_LPUART4_RX_SELECT_INPUT
IOMUXC_LPUART4_TX_SELECT_INPUT
IOMUXC_LPUART5_RX_SELECT_INPUT
IOMUXC_LPUART5_TX_SELECT_INPUT
IOMUXC_LPUART6_RX_SELECT_INPUT
IOMUXC_LPUART6_TX_SELECT_INPUT
IOMUXC_LPUART7_RX_SELECT_INPUT
IOMUXC_LPUART7_TX_SELECT_INPUT
IOMUXC_LPUART8_RX_SELECT_INPUT
IOMUXC_LPUART8_TX_SELECT_INPUT
IOMUXC_NMI_SELECT_INPUT
IOMUXC_QTIMER2_TIMER0_SELECT_INPUT
IOMUXC_QTIMER2_TIMER1_SELECT_INPUT
IOMUXC_QTIMER2_TIMER2_SELECT_INPUT
IOMUXC_QTIMER2_TIMER3_SELECT_INPUT
IOMUXC_QTIMER3_TIMER0_SELECT_INPUT
IOMUXC_QTIMER3_TIMER1_SELECT_INPUT
IOMUXC_QTIMER3_TIMER2_SELECT_INPUT
IOMUXC_QTIMER3_TIMER3_SELECT_INPUT
IOMUXC_SAI1_MCLK2_SELECT_INPUT
IOMUXC_SAI1_RX_BCLK_SELECT_INPUT
IOMUXC_SAI1_RX_DATA0_SELECT_INPUT
IOMUXC_SAI1_RX_DATA1_SELECT_INPUT
IOMUXC_SAI1_RX_DATA2_SELECT_INPUT
IOMUXC_SAI1_RX_DATA3_SELECT_INPUT
IOMUXC_SAI1_RX_SYNC_SELECT_INPUT
IOMUXC_SAI1_TX_BCLK_SELECT_INPUT
IOMUXC_SAI1_TX_SYNC_SELECT_INPUT
IOMUXC_SAI2_MCLK2_SELECT_INPUT
IOMUXC_SAI2_RX_BCLK_SELECT_INPUT
IOMUXC_SAI2_RX_DATA0_SELECT_INPUT
IOMUXC_SAI2_RX_SYNC_SELECT_INPUT
IOMUXC_SAI2_TX_BCLK_SELECT_INPUT
IOMUXC_SAI2_TX_SYNC_SELECT_INPUT
IOMUXC_SPDIF_IN_SELECT_INPUT
IOMUXC_USB_OTG2_OC_SELECT_INPUT
IOMUXC_USB_OTG1_OC_SELECT_INPUT
IOMUXC_USDHC1_CD_B_SELECT_INPUT
IOMUXC_USDHC1_WP_SELECT_INPUT
IOMUXC_USDHC2_CLK_SELECT_INPUT
IOMUXC_USDHC2_CD_B_SELECT_INPUT
IOMUXC_USDHC2_CMD_SELECT_INPUT
IOMUXC_USDHC2_DATA0_SELECT_INPUT
IOMUXC_USDHC2_DATA1_SELECT_INPUT
IOMUXC_USDHC2_DATA2_SELECT_INPUT
IOMUXC_USDHC2_DATA3_SELECT_INPUT
IOMUXC_USDHC2_DATA4_SELECT_INPUT
IOMUXC_USDHC2_DATA5_SELECT_INPUT
IOMUXC_USDHC2_DATA6_SELECT_INPUT
IOMUXC_USDHC2_DATA7_SELECT_INPUT
IOMUXC_USDHC2_WP_SELECT_INPUT
IOMUXC_XBAR1_IN02_SELECT_INPUT
IOMUXC_XBAR1_IN03_SELECT_INPUT
IOMUXC_XBAR1_IN04_SELECT_INPUT
IOMUXC_XBAR1_IN05_SELECT_INPUT
IOMUXC_XBAR1_IN06_SELECT_INPUT
IOMUXC_XBAR1_IN07_SELECT_INPUT
IOMUXC_XBAR1_IN08_SELECT_INPUT
IOMUXC_XBAR1_IN09_SELECT_INPUT
IOMUXC_XBAR1_IN17_SELECT_INPUT
IOMUXC_XBAR1_IN18_SELECT_INPUT
IOMUXC_XBAR1_IN20_SELECT_INPUT
IOMUXC_XBAR1_IN22_SELECT_INPUT
IOMUXC_XBAR1_IN23_SELECT_INPUT
IOMUXC_XBAR1_IN24_SELECT_INPUT
IOMUXC_XBAR1_IN14_SELECT_INPUT
IOMUXC_XBAR1_IN15_SELECT_INPUT
IOMUXC_XBAR1_IN16_SELECT_INPUT
IOMUXC_XBAR1_IN25_SELECT_INPUT
IOMUXC_XBAR1_IN19_SELECT_INPUT
IOMUXC_XBAR1_IN21_SELECT_INPUT
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06
IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07
IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT
IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT
IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0
IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1
IOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT
IOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT
IOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0
IOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT
IOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT
IOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT
IOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT
IOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT
IOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT
IOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT
IOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2
IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT
IOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0
IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT
IOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT
IOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT
IOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT
IOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT
Chapter 11: General Purpose Input/Output (GPIO)
Chip-specific GPIO information
Overview
Block Diagram
Features
Clocks
GPIO Functional Description
GPIO Function
GPIO pad structure
Input Driver
Schmitt trigger
Input keeper
Output Driver
Drive strength
Output keeper
PU / PD / Keeper Logic
Open drain
GPIO Programming
GPIO Read Mode
GPIO Write Mode
Interrupt Control Unit
GPIO Register Descriptions
GPIO Memory map
GPIO data register (DR)
GPIO direction register (GDIR)
GPIO pad status register (PSR)
GPIO interrupt configuration register1 (ICR1)
GPIO interrupt configuration register2 (ICR2)
GPIO interrupt mask register (IMR)
GPIO interrupt status register (ISR)
GPIO edge select register (EDGE_SEL)
GPIO data register SET (DR_SET)
GPIO data register CLEAR (DR_CLEAR)
GPIO data register TOGGLE (DR_TOGGLE)
Chapter 12-18: Clocking and Power
Chapter 12: Clock and Power Management
Introduction
Device Power Management Architecture Components
Centralized components of clock generation and management
Centralized components of power generation, distribution and management
Reset generation and distribution system
Power and clock management framework
Clock Management
Centralized components of clock management system
Clock generation
Crystal Oscillator (XTALOSC)
PLLs
General PLL Control and Status Functions
CCM
Low Power Clock Gating unit (LPCG)
Peripheral components of clock management system
Interface and functional clock
Block level clock management
Master clock protocol
Slave clock protocol
Clock Domain(s)
Domain level clock management
Domain dependencies
Power management
Centralized Components of Power Management System
Integrated PMU
DCDC Regulator
Analog LDO regulators
USB LDO
SNVS regulator
GPC - General Power Controller
SRC - System reset Controller
Power domain(s)
Power distribution
Domain memory and domain logic state retention in case of power gating
Power Gating Domain Management
ARM Core Platform
SoC
Power Gating domain dependencies
Voltage domains
Voltage domain management
Dynamic
Voltage Scaling
Static
Standby Leakage reduction (SLR)
System domains layout
Power management techniques
Power saving techniques
Thermal-aware power management
Peripheral Power management
IO power reduction
Examples of External Power Supply Interface
ONOFF (Button)
WAKEUP Pin
Chapter 13: Clock Controller Module (CCM)
Chip-specific CCM information
Overview
Features
CCM Block Diagram
External Signals
CCM Clock Tree
System Clocks
Functional Description
Clock Generation
External Low Frequency Clock - CKIL
CKIL synchronizing to IPG_CLK
External High Frequency Clock - CKIH and internal oscillator
PLL reference clock
ARM PLL (PLL1)
System PLL (PLL2)
USB1 PLL (PLL3)
Audio PLL (PLL4)
Video PLL (PLL5)
Ethernet PLL (PLL6)
USB2 PLL (PLL7)
Phase Fractional Dividers (PFD)
CCM internal clock generation
Clock Switcher
PLL bypass procedure
PLL clock change
Clock Root Generator
Divider change handshake
Disabling / Enabling PLLs
Clock Switching Multiplexers
Low Power Clock Gating module (LPCG)
DVFS support
Power modes
RUN mode
WAIT mode
Entering WAIT mode
Exiting WAIT mode
STOP mode
Entering STOP mode
Exiting STOP mode
CCM Memory Map/Register Definition
CCM
CCM_CCR
CCM_CSR
CCM_CCSR
CCM_CACRR
CCM_CBCDR
CCM_CBCMR
CCM_CSCMR1
CCM_CSCMR2
CCM_CSCDR1
CCM_CS1CDR
CCM_CS2CDR
CCM_CDCDR
CCM_CSCDR2
CCM_CSCDR3
CCM_CDHIPR
CCM_CLPCR
CCM_CISR
CCM_CIMR
CCM_CCOSR
CCM_CGPR
CCM_CCGR0
CCM_CCGR1
CCM_CCGR2
CCM_CCGR3
CCM_CCGR4
CCM_CCGR5
CCM_CCGR6
CCM_CCGR7
CCM_CMEOR
CCM Analog Memory Map/Register Definition
CCM_ANALOG
CCM_ANALOG_PLL_ARMn
CCM_ANALOG_PLL_USB1n
CCM_ANALOG_PLL_USB2n
CCM_ANALOG_PLL_SYSn
CCM_ANALOG_PLL_SYS_SS
CCM_ANALOG_PLL_SYS_NUM
CCM_ANALOG_PLL_SYS_DENOM
CCM_ANALOG_PLL_AUDIOn
CCM_ANALOG_PLL_AUDIO_NUM
CCM_ANALOG_PLL_AUDIO_DENOM
CCM_ANALOG_PLL_VIDEOn
CCM_ANALOG_PLL_VIDEO_NUM
CCM_ANALOG_PLL_VIDEO_DENOM
CCM_ANALOG_PLL_ENETn
CCM_ANALOG_PFD_480n
CCM_ANALOG_PFD_528n
CCM_ANALOG_MISC0n
CCM_ANALOG_MISC1n
CCM_ANALOG_MISC2n
Chapter 14: Crystal Oscillator (XTALOSC)
Chip-specific XTALOSC information
Overview
External Signals
Crystal Oscillator 24 MHz
Oscillator Configuration (24 MHz)
Bypass Configuration (24 MHz)
RC Oscillator (24 MHz)
Crystal Frequency Detection(24 MHz)
Crystal Oscillator 32 kHz
Oscillator Configuration (32 kHz)
Bypass Configuration (32 kHz)
XTALOSC 24MHz Memory Map/Register Definition
XTALOSC24M
XTALOSC24M_MISC0n
XTALOSC24M_LOWPWR_CTRLn
XTALOSC24M_OSC_CONFIG0n
XTALOSC24M_OSC_CONFIG1n
XTALOSC24M_OSC_CONFIG2n
Chapter 15: Power Management Unit (PMU)
Chip-specific PMU information
Overview
Digital LDO Regulators
Analog LDO Regulators
LDO 1P1
LDO 2P5
Low Power Operation
USB LDO Regulator
SNVS Regulator
PMU Memory Map/Register Definition
PMU
PMU_REG_1P1n
PMU_REG_3P0n
PMU_REG_2P5n
PMU_REG_COREn
PMU_MISC0n
PMU_MISC1n
PMU_MISC2n
Chapter 16: General Power Controller (GPC)
Chip-specific GPC information
Overview
Clocks
Power Gating Control (PGC)
Overview
Features
GPC Interrupt Controller (INTC)
Interrupt Controller features
GPC Memory Map/Register Definition
GPC
GPC_CNTR
GPC_IMR1
GPC_IMR2
GPC_IMR3
GPC_IMR4
GPC_ISR1
GPC_ISR2
GPC_ISR3
GPC_ISR4
GPC_IMR5
GPC_ISR5
PGC Memory Map/Register Definition
PGC
PGC_MEGA_CTRL
PGC_MEGA_PUPSCR
PGC_MEGA_PDNSCR
PGC_MEGA_SR
PGC_CPU_CTRL
PGC_CPU_PUPSCR
PGC_CPU_PDNSCR
PGC_CPU_SR
Chapter 17: DCDC Converter (DCDC)
Chip-specific DCDC information
Introduction
Features
Block diagram
Functional description
Application information
Memory Map and register definition
DCDC register descriptions
DCDC Memory map
DCDC Register 0 (REG0)
DCDC Register 1 (REG1)
DCDC Register 2 (REG2)
DCDC Register 3 (REG3)
Chapter 18: Temperature Monitor (TEMPMON)
Chip-specific TEMPMON information
Overview
Software Usage Guidelines
TEMPMON Memory Map/Register Definition
TEMPMON
TEMPMON_TEMPSENSE0n
TEMPMON_TEMPSENSE1n
TEMPMON_TEMPSENSE2n
Chapter 19-22: SNVS, Reset and Fuse
Chapter 19: Secure Non-Volatile Storage (SNVS)
Chip-specific SNVS information
SNVS introduction
SNVS feature list
SNVS functional description
SNVS Structure
SNVS power domains
SNVS clock sources
Runtime Procedures
Using SNVS Timer Facilities
SNVS_HP Real Time Counter
RTC/SRTC control bits setting
Reading RTC and SRTC values
Using Other SNVS Registers
Using the General-Purpose Register
Reset and Initialization of SNVS
Initialization Checklists
SNVS register descriptions
SNVS Memory map
SNVS_HP Lock Register (HPLR)
SNVS_HP Command Register (HPCOMR)
SNVS_HP Control Register (HPCR)
SNVS_HP Status Register (HPSR)
SNVS_HP Real Time Counter MSB Register (HPRTCMR)
SNVS_HP Real Time Counter LSB Register (HPRTCLR)
SNVS_HP Time Alarm MSB Register (HPTAMR)
SNVS_HP Time Alarm LSB Register (HPTALR)
SNVS_LP Lock Register (LPLR)
SNVS_LP Control Register (LPCR)
SNVS_LP Status Register (LPSR)
SNVS_LP Secure Monotonic Counter MSB Register (LPSMCMR)
SNVS_LP Secure Monotonic Counter LSB Register (LPSMCLR)
SNVS_LP General Purpose Register 0 (legacy alias) (LPGPR0_legacy_alias)
SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0_alias - LPGPR3_alias)
SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3)
SNVS_HP Version ID Register 1 (HPVIDR1)
SNVS_HP Version ID Register 2 (HPVIDR2)
Chapter 20: System Reset Controller (SRC)
Chip-specific SRC information
SRC Overview
Features
External Signals
Clocks
Top-level resets, power-up sequence and external supply integration
Reset and Power-up Flow
Finite-State Machine (FSM)
Power mode transitions
Power-On Reset and power sequencing
External POR using SRC_POR_B
Internal POR
Functional Description
Reset Control
Reset inputs and outputs
Reset Handling
POR (SRC_POR_B)
COLD RESET
Parallel Reset Requests
Boot Mode Control
BOOT_MODE Pin Latching
SRC Memory Map/Register Definition
SRC
SRC_SCR
SRC_SBMR1
SRC_SRSR
SRC_SBMR2
SRC_GPR1
SRC_GPR2
SRC_GPR3
SRC_GPR4
SRC_GPR5
SRC_GPR6
SRC_GPR7
SRC_GPR8
SRC_GPR9
SRC_GPR10
Chapter 21: Fusemap
Boot Fusemap
Lock Fusemap
Fusemap Descriptions Table
Chapter 22: On-Chip OTP Controller (OCOTP_CTRL)
Chip-specific OCOTP_CTRL information
Overview
Features
Clocks
Top-Level Symbol and Functional Overview
Operation
Shadow Register Reload
Fuse and Shadow register read
Fuse and Shadow Register Writes
Write Postamble
Fuse Shadow Memory Footprint
OTP Read/Write Timing Parameters
Hardware Visible Fuses
Behavior During Reset
Secure JTAG control
Fuse Map
OCOTP Memory Map/Register Definition
OCOTP register descriptions
OCOTP Memory map
OTP Controller Control Register (CTRL)
OTP Controller Control Register (CTRL_SET)
OTP Controller Control Register (CTRL_CLR)
OTP Controller Control Register (CTRL_TOG)
OTP Controller Timing Register (TIMING)
OTP Controller Write Data Register (DATA)
OTP Controller Write Data Register (READ_CTRL)
OTP Controller Read Data Register (READ_FUSE_DATA)
Sticky bit Register (SW_STICKY)
Software Controllable Signals Register (SCS)
Software Controllable Signals Register (SCS_SET)
Software Controllable Signals Register (SCS_CLR)
Software Controllable Signals Register (SCS_TOG)
OTP Controller CRC test address (CRC_ADDR)
OTP Controller CRC Value Register (CRC_VALUE)
OTP Controller Version Register (VERSION)
OTP Controller Timing Register (TIMING2)
Value of OTP Bank0 Word0 (Lock controls) (LOCK)
Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) (CFG0)
Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) (CFG1)
Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) (CFG2)
Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) (CFG3)
Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) (CFG4)
Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) (CFG5)
Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) (CFG6)
Value of OTP Bank1 Word0 (Memory Related Info.) (MEM0)
Value of OTP Bank1 Word1 (Memory Related Info.) (MEM1)
Value of OTP Bank1 Word2 (Memory Related Info.) (MEM2)
Value of OTP Bank1 Word3 (Memory Related Info.) (MEM3)
Value of OTP Bank1 Word4 (Memory Related Info.) (MEM4)
Value of OTP Bank1 Word5 (Analog Info.) (ANA0)
Value of OTP Bank1 Word6 (Analog Info.) (ANA1)
Value of OTP Bank1 Word7 (Analog Info.) (ANA2)
Value of OTP Bank2 Word0 (OTPMK Key) (OTPMK0)
Value of OTP Bank2 Word1 (OTPMK Key) (OTPMK1)
Value of OTP Bank2 Word2 (OTPMK Key) (OTPMK2)
Value of OTP Bank2 Word3 (OTPMK Key) (OTPMK3)
Value of OTP Bank2 Word4 (OTPMK Key) (OTPMK4)
Value of OTP Bank2 Word5 (OTPMK Key) (OTPMK5)
Value of OTP Bank2 Word6 (OTPMK Key) (OTPMK6)
Value of OTP Bank2 Word7 (OTPMK Key) (OTPMK7)
Shadow Register for OTP Bank3 Word0 (SRK Hash) (SRK0)
Shadow Register for OTP Bank3 Word1 (SRK Hash) (SRK1)
Shadow Register for OTP Bank3 Word2 (SRK Hash) (SRK2)
Shadow Register for OTP Bank3 Word3 (SRK Hash) (SRK3)
Shadow Register for OTP Bank3 Word4 (SRK Hash) (SRK4)
Shadow Register for OTP Bank3 Word5 (SRK Hash) (SRK5)
Shadow Register for OTP Bank3 Word6 (SRK Hash) (SRK6)
Shadow Register for OTP Bank3 Word7 (SRK Hash) (SRK7)
Value of OTP Bank4 Word0 (Secure JTAG Response Field) (SJC_RESP0)
Value of OTP Bank4 Word1 (Secure JTAG Response Field) (SJC_RESP1)
Value of OTP Bank4 Word2 (MAC Address) (MAC0)
Value of OTP Bank4 Word3 (MAC Address) (MAC1)
Value of OTP Bank4 Word4 (MAC Address) (MAC2)
Value of OTP Bank4 Word5 (CRC Key) (OTPMK_CRC32)
Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) (GP1)
Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) (GP2)
Value of OTP Bank5 Word0 (SW GP1) (SW_GP1)
Value of OTP Bank5 Word1 (SW GP2) (SW_GP20)
Value of OTP Bank5 Word2 (SW GP2) (SW_GP21)
Value of OTP Bank5 Word3 (SW GP2) (SW_GP22)
Value of OTP Bank5 Word4 (SW GP2) (SW_GP23)
Value of OTP Bank5 Word5 (Misc Conf) (MISC_CONF0)
Value of OTP Bank5 Word6 (Misc Conf) (MISC_CONF1)
Value of OTP Bank5 Word7 (SRK Revoke) (SRK_REVOKE)
Value of OTP Bank6 Word0 (ROM Patch) (ROM_PATCH0)
Value of OTP Bank6 Word1 (ROM Patch) (ROM_PATCH1)
Value of OTP Bank6 Word2 (ROM Patch) (ROM_PATCH2)
Value of OTP Bank6 Word3 (ROM Patch) (ROM_PATCH3)
Value of OTP Bank6 Word4 (ROM Patch) (ROM_PATCH4)
Value of OTP Bank6 Word5 (ROM Patch) (ROM_PATCH5)
Value of OTP Bank6 Word6 (ROM Patch) (ROM_PATCH6)
Value of OTP Bank6 Word7 (ROM Patch) (ROM_PATCH7)
Value of OTP Bank7 Word0 (GP3) (GP30)
Value of OTP Bank7 Word1 (GP3) (GP31)
Value of OTP Bank7 Word2 (GP3) (GP32)
Value of OTP Bank7 Word3 (GP3) (GP33)
Value of OTP Bank7 Word4 (GP4) (GP40)
Value of OTP Bank7 Word5 (GP4) (GP41)
Value of OTP Bank7 Word6 (GP4) (GP42)
Value of OTP Bank7 Word7 (GP4) (GP43)
Chapter 23-26: External Memory Interfaces and Controllers
Chapter 23: External Memory Controllers
Overview
Smart External Memory Controller (SEMC) Overview
eMMC/eSD/SDIO
Quad Serial Peripheral Interface
SIP 4M Flash Memory
Chapter 24: Smart External Memory Controller (SEMC)
Chip-specific SEMC information
About this module
Introduction
Features
Operation Modes
Block diagram
Signals
Memory Map and register definition
SEMC register descriptions
SEMC Memory map
Module Control Register (MCR)
IO Mux Control Register (IOCR)
Master Bus (AXI) Control Register 0 (BMCR0)
Master Bus (AXI) Control Register 1 (BMCR1)
Base Register 0 (For SDRAM CS0 device) (BR0)
Base Register 1 (For SDRAM CS1 device) (BR1)
Base Register 2 (For SDRAM CS2 device) (BR2)
Base Register 3 (For SDRAM CS3 device) (BR3)
Base Register 4 (For NAND device) (BR4)
Base Register 5 (For NOR device) (BR5)
Base Register 6 (For PSRAM device) (BR6)
Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device) (BR7)
Base Register 8 (For NAND device) (BR8)
DLL Control Register (DLLCR)
Interrupt Enable Register (INTEN)
Interrupt Enable Register (INTR)
SDRAM control register 0 (SDRAMCR0)
SDRAM control register 1 (SDRAMCR1)
SDRAM control register 2 (SDRAMCR2)
SDRAM control register 3 (SDRAMCR3)
NAND control register 0 (NANDCR0)
NAND control register 1 (NANDCR1)
NAND control register 2 (NANDCR2)
NAND control register 3 (NANDCR3)
NOR control register 0 (NORCR0)
NOR control register 1 (NORCR1)
NOR control register 2 (NORCR2)
NOR control register 3 (NORCR3)
SRAM control register 0 (SRAMCR0)
SRAM control register 1 (SRAMCR1)
SRAM control register 2 (SRAMCR2)
SRAM control register 3 (SRAMCR3)
DBI-B control register 0 (DBICR0)
DBI-B control register 1 (DBICR1)
IP Command control register 0 (IPCR0)
IP Command control register 1 (IPCR1)
IP Command control register 2 (IPCR2)
IP Command register (IPCMD)
TX DATA register (for IP Command) (IPTXDAT)
RX DATA register (for IP Command) (IPRXDAT)
Status register 0 (STS0)
Status register 1 (STS1)
Status register 2 (STS2)
Status register 3 (STS3)
Status register 4 (STS4)
Status register 5 (STS5)
Status register 6 (STS6)
Status register 7 (STS7)
Status register 8 (STS8)
Status register 9 (STS9)
Status register 10 (STS10)
Status register 11 (STS11)
Status register 12 (STS12)
Status register 13 (STS13)
Status register 14 (STS14)
Status register 15 (STS15)
Functional description
Clocks
Reset
Pin Mux in SEMC
Device access by AXI Command
Device access by IP Command
SDRAM Controller Operations
SDRAM address map
SDRAM device access by IP Command
IP command - SDRAM Self Refresh
IP command - SDRAM Auto Refresh
IP command - SDRAM Mode Register Set
IP command - SDRAM Precharge
IP command - SDRAM Precharge ALL
IP command - SDRAM Active
IP command - SDRAM READ
IP command - SDRAM WRITE
SDRAM device access by AXI Command
SDRAM device read access by AXI Command
SDRAM device write access by AXI Command
SDRAM device pipelined access by AXI Command
SDRAM back-to-back access
SDRAM read-to-read access
SDRAM read-to-write access
SDRAM write-to-write access
SDRAM write-to-read access
Refresh command - SDRAM AUTO Refresh
SDRAM low power feature
Stop mode - SDRAM
BUS Idle - SDRAM
SDRAM Page Management
SDRAM Timers
Prescaler
Refresh interval timer
Urgent Refresh timer
Beat timer
ACTIVE to READ/WRITE timer
PRECHARGE to ACTIVE timer
CKE OFF timer
SELF REFRESH recover timer
AUTO REFRESH recover timer
Refresh to Refresh timer
ACTIVE to ACTIVE timer
ACTIVE to PRECHARGE timer
Write recovery timer
NAND Flash Controller Operations
NAND Flash address map
NAND Flash access address type
One Byte Column Address
Two Byte Column Address
One Byte Row Address
Two Byte Row Address
Three Byte Row Address
Five Byte Row/Column Address
NAND Flash access command type
Command Phase Only
Command + Wait Phase
Command + Address Phase
Command + Address + Wait Phase
Command + Address + Read Phase
Command + Address + Write Phase (For IP command)
Command + Read Phase
Command + Write Phase
Read Phase Only
Write Phase Only
Command + Address + Command + Read Phase
Command + Address + Write Phase (For AXI command)
NAND Flash read access EDO and non-EDO mode
NOR Flash Controller Operations
NOR Flash Read Operation in ASYNC Mode
NOR Flash Write Operation in ASYNC mode
NOR Flash Read Operation in SYNC mode
SRAM Controller Operations
SRAM Read Operation in ASYNC Mode
SRAM Write Operation in ASYNC mode
SRAM Read Operation in SYNC mode
SRAM Write Operation in SYNC mode
Display Bus Interface Controller Operations
Chapter 25: Ultra Secured Digital Host Controller (uSDHC)
Chip-specific uSDHC information
Overview
Features
Modes and Operations
Data transfer Modes
External Signals
Signals Overview
Clocks
Functional Description
Data Buffer
Write Operation Sequence
Read Operation Sequence
Data Buffer and Block Size
Dividing Large Data Transfer
DMA AHB Interface
Internal DMA Request
DMA Burst Length
AHB Master Interface
ADMA Engine
ADMA Concept and Descriptor Format
ADMA Interrupt
ADMA Error
Register Bank with IP Bus Interface
SD Protocol Unit
SD control misc
SD Clock control
Command control
Data control
Clock & Reset Manager
Clock Generator
SDIO Card Interrupt
Interrupts in 1-bit Mode
Interrupt in 4-bit Mode
Card Interrupt Handling
Card Insertion and Removal Detection
Power Management and Wake Up Events
Setting Wake Up Events
MMC fast boot
Boot operation
Alternative boot operation
Initialization/Application of uSDHC
Command Send & Response Receive Basic Operation
Card Identification Mode
Card Detect
Reset
Voltage Validation
Card Registry
Card Access
Block Write
Normal Write
DDR Write
Write with Pause
Block Read
Normal Read
DDR Read
Read with Pause
DLL (Delay Line) in Read Path
Suspend Resume
Suspend
Resume
ADMA Usage
Transfer Error
CRC Error
Internal DMA Error
Transfer ADMA Error
Auto CMD12 Error
Card Interrupt
Switch Function
Query, Enable and Disable SDIO High Speed Mode
Query, Enable and Disable SD High Speed Mode/SDR50/SDR104/DDR50
Query, Enable and Disable MMC High Speed Mode
Set MMC Bus Width
ADMA Operation
ADMA1 Operation
ADMA2 Operation
Fast Boot Operation
Normal fast boot flow
Alternative fast boot flow
Fast boot application case (in DMA mode)
Commands for MMC/SD/SDIO
Software Restrictions
Initialization Active
Software Polling Procedure
Suspend Operation
Data Length Setting
(A)DMA Address Setting
Data Port Access
Change Clock Frequency
Multi-block Read
uSDHC Memory Map/Register Definition
uSDHC register descriptions
uSDHC Memory map
DMA System Address (DS_ADDR)
Block Attributes (BLK_ATT)
Command Argument (CMD_ARG)
Command Transfer Type (CMD_XFR_TYP)
Command Response0 (CMD_RSP0)
Command Response1 (CMD_RSP1)
Command Response2 (CMD_RSP2)
Command Response3 (CMD_RSP3)
Data Buffer Access Port (DATA_BUFF_ACC_PORT)
Present State (PRES_STATE)
Protocol Control (PROT_CTRL)
System Control (SYS_CTRL)
Interrupt Status (INT_STATUS)
Interrupt Status Enable (INT_STATUS_EN)
Interrupt Signal Enable (INT_SIGNAL_EN)
Auto CMD12 Error Status (AUTOCMD12_ERR_STATUS)
Host Controller Capabilities (HOST_CTRL_CAP)
Watermark Level (WTMK_LVL)
Mixer Control (MIX_CTRL)
Force Event (FORCE_EVENT)
ADMA Error Status Register (ADMA_ERR_STATUS)
ADMA System Address (ADMA_SYS_ADDR)
DLL (Delay Line) Control (DLL_CTRL)
DLL Status (DLL_STATUS)
CLK Tuning Control and Status (CLK_TUNE_CTRL_STATUS)
Vendor Specific Register (VEND_SPEC)
MMC Boot Register (MMC_BOOT)
Vendor Specific 2 Register (VEND_SPEC2)
Tuning Control Register (TUNING_CTRL)
Chapter 26: FlexSPI Controller
Chip-specific FlexSPI information
Master ID allocation
Introduction
Features
Block diagram
Operation Modes
Glossary for FlexSPI module
External Signal Description
Memory Map and register definition
Register Access
FlexSPI register descriptions
FlexSPI Memory map
Module Control Register 0 (MCR0)
Module Control Register 1 (MCR1)
Module Control Register 2 (MCR2)
AHB Bus Control Register (AHBCR)
Interrupt Enable Register (INTEN)
Interrupt Register (INTR)
LUT Key Register (LUTKEY)
LUT Control Register (LUTCR)
AHB RX Buffer 0 Control Register 0 (AHBRXBUF0CR0)
AHB RX Buffer 1 Control Register 0 (AHBRXBUF1CR0)
AHB RX Buffer 2 Control Register 0 (AHBRXBUF2CR0)
AHB RX Buffer 3 Control Register 0 (AHBRXBUF3CR0)
Flash a Control Register 0 (FLSHA1CR0 - FLSHB2CR0)
Flash a Control Register 1 (FLSHA1CR1 - FLSHB2CR1)
Flash a Control Register 2 (FLSHA1CR2 - FLSHB2CR2)
Flash Control Register 4 (FLSHCR4)
IP Control Register 0 (IPCR0)
IP Control Register 1 (IPCR1)
IP Command Register (IPCMD)
IP RX FIFO Control Register (IPRXFCR)
IP TX FIFO Control Register (IPTXFCR)
DLL Control Register 0 (DLLACR - DLLBCR)
Status Register 0 (STS0)
Status Register 1 (STS1)
Status Register 2 (STS2)
AHB Suspend Status Register (AHBSPNDSTS)
IP RX FIFO Status Register (IPRXFSTS)
IP TX FIFO Status Register (IPTXFSTS)
IP RX FIFO Data Register a (RFDR0 - RFDR31)
IP TX FIFO Data Register a (TFDR0 - TFDR31)
LUT a (LUT0 - LUT63)
AHB Memory Map definition
AHB Memory Map for Serial Flash memory access
AHB Memory Map for IP RX FIFO read access
AHB Memory Map for IP TX FIFO write access
Functional description
Clocks
Interrupts
Flash Connection
Flash Access mode
SPI clock mode
Flash Individual mode and Parallel mode
SDR mode and DDR mode
Single, Dual, Quad, Octal mode
Flash memory map
Flash address sent to Device
Look Up Table
Programmable Sequence Engine
Instruction execution on SPI interface
Flash access sequence example
Flash access by IP Command
Reading Data from IP RX FIFO
Filling Data to IP TX FIFO
Flash access by AHB Command
AHB write access to Flash
AHB read access to Flash
AHB RX Buffer Management
Command Arbitration
Command Abort and Suspend
SCK stop feature
FlexSPI Output Timing
Output timing between Data and SCK
Output timing between Chip selection and SCK
FlexSPI Input Timing
RX Clock Source Features
Input timing for sampling with dummy read strobe
Input timing for sampling with flash provided read strobe
DLL configuration for sampling
Execute-In-Place Enhance mode
Application information
FlexSPI Initialization
Overview of Error Flags
Application on Serial NOR Flash device
Write Enable command
Write Registers command
Page Program command
Read Status 1 command
Read command
Fast Read command
Dual IO Fast Read command
Quad IO Fast Read command
DDR Quad IO Fast Read command
Application on HyperBus device
HyperFlash
HyperRAM
Application on Serial NAND Flash device
Application on FPGA device
Chapter 27-31: ARM Core Platform
Chapter 27: ARM Cortex M7 Platform
Chip-specific Arm Cortex M7 information
ARM Cortex M7 Platform
Overview
Block Diagram
External Signals
Clocks
Chapter 28: Network Interconnect Bus System (NIC-301)
Chip-specific NIC-301 information
Overview
NIC-301 Main Features
Modes and Operations
External Signals
Memory Map and Register Definition
Chapter 29: On-Chip RAM Memory Controller (OCRAM)
Chip-specific OCRAM information
Overview
Basic Functions
Read/Write Arbitration
Advanced Features
Read Data Wait State
Read Address Pipeline
Write Data Pipeline
Write Address Pipeline
Programmable Registers
Chapter 30: FlexRAM
Chip-specific FlexRAM information
Overview
Introduction
Features
Block diagram
Functional description
Interface Conversion
RAM Bank Allocation
Low power modes
Clocks
Reset
Interrupts
Memory Map and register definition
FLEXRAM register descriptions
FLEXRAM Memory map
TCM CRTL Register (TCM_CTRL)
Interrupt Status Register (INT_STATUS)
Interrupt Status Enable Register (INT_STAT_EN)
Interrupt Enable Register (INT_SIG_EN)
Chapter 31: AHB to IP Bridge (AIPSTZ)
Chip-specific AIPSTZ information
Overview
Features
Clocks
Functional Description
Access Protections
Access Support
Initialization Information
Security Block
AIPSTZ Memory Map/Register Definition
AIPSTZx
AIPSTZx_MPR
AIPSTZx_OPACR
AIPSTZx_OPACR1
AIPSTZx_OPACR2
AIPSTZx_OPACR3
AIPSTZx_OPACR4
Chapter 32-35: Display and Camera
Chapter 32: Display and Camera Overview
Display and Camera Overview
PiXel Processing Pipeline
LCD Interface
CMOS Sensor Interface
Chapter 33: CMOS Sensor Interface (CSI)
Chip-specific CSI information
Overview
External Signals
Clocks
Principles of Operation
Data Transfer with the Embedded DMA Controllers
Gated Clock Mode
Non-Gated Clock Mode
CCIR656 Interlace Mode
CCIR656 Progressive Mode
Error Correction for CCIR656 Coding
Interrupt Generation
Start Of Frame Interrupt (SOF_INT)
End Of Frame Interrupt (EOF_INT)
Change Of Field Interrupt (COF_INT)
CCIR Error Interrupt (ECC_INT)
RxFIFO Full Interrupt (RxFF_INT)
Statistic FIFO Full Interrupt (STATFF_INT)
RxFIFO Overrun Interrupt (RFF_OR_INT)
Statistic FIFO Overrun Interrupt (SFF_OR_INT)
Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1)
Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2)
Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)
AHB Bus Response Error Interrupt (HRESP_ERR_INT)
Data Packing Style
STAT FIFO Path
CSI Memory Map/Register Definition
CSI
CSI_CSICR1
CSI_CSICR2
CSI_CSICR3
CSI_CSISTATFIFO
CSI_CSIRFIFO
CSI_CSIRXCNT
CSI_CSISR
CSI_CSIDMASA_STATFIFO
CSI_CSIDMATS_STATFIFO
CSI_CSIDMASA_FB1
CSI_CSIDMASA_FB2
CSI_CSIFBUF_PARA
CSI_CSIIMAG_PARA
CSI_CSICR18
CSI_CSICR19
Chapter 34: Enhanced LCD Interface (eLCDIF)
Chip-specific eLCDIF information
Overview
External Signals
Clocks
Functional Description
Bus Interface Mechanisms
Bus Master Operation in Write/Display Modes
System Bus Master Performance
DMA Operation in MPU Read Mode
Write Data Path
LCDIF Interrupts
Initializing the LCDIF
Write Modes
DOTCLK Interface
Code Example
LUT
Panel Interface Generator (Pigeon Mode)
LCDIF Pin Usage by Interface Mode
Behavior During Reset
LCDIF Memory Map/Register Definition
LCDIF
LCDIF_CTRLn
LCDIF_CTRL1n
LCDIF_CTRL2n
LCDIF_TRANSFER_COUNT
LCDIF_CUR_BUF
LCDIF_NEXT_BUF
LCDIF_VDCTRL0n
LCDIF_VDCTRL1
LCDIF_VDCTRL2
LCDIF_VDCTRL3
LCDIF_VDCTRL4
LCDIF_BM_ERROR_STAT
LCDIF_CRC_STAT
LCDIF_STAT
LCDIF_PIGEONCTRL0n
LCDIF_PIGEONCTRL1n
LCDIF_PIGEONCTRL2n
LCDIF_PIGEONn
LCDIF_PIGEONn
LCDIF_PIGEONn
LCDIF_LUT_CTRL
LCDIF_LUT0_ADDR
LCDIF_LUT0_DATA
LCDIF_LUT1_ADDR
LCDIF_LUT1_DATA
Chapter 35: Pixel Pipeline (PXP)
Chip-specific PXP information
Overview
Clocks
Top-level architecture
Processing Details
Scaling Operation
Decimation Image Scaling
Bilinear Image Scaling Filter
YUV 4:2:2 Image Scaling
YUV 4:2:0 Image Scaling
RGB/YUV444 Image Scaling
Color Space Conversion (CSC)
CSC1 Operation
YUV versus YCbCr Support
Alpha Blending/Color Key
Alpha Blend
Porter-Duff Alpha Blend
Color Key
Rotation
Output Buffer
Address calculator
Block size selection
Interlaced Video Support
LCDIF Handshake
LCDIF Abort
Theory of Operation
Pixel Handling
Output Buffer Composition
PS Image Processing
Letterboxing
Clipping source images
Color Key Processing
In Place Processing (PS buffer is destination buffer)
Alpha Surface (AS) Processing
Alpha Handling
Color Key Processing (AS_CTRL)
Output Image Processing
Output Image Size
Output Format
Rotation/Flip operations
Queuing PXP transactions
Error Handling
Known PXP Limitations/Issues
PXP Memory Map/Register Definition
PXP
PXP_CTRLn
PXP_STATn
PXP_OUT_CTRLn
PXP_OUT_BUF
PXP_OUT_BUF2
PXP_OUT_PITCH
PXP_OUT_LRC
PXP_OUT_PS_ULC
PXP_OUT_PS_LRC
PXP_OUT_AS_ULC
PXP_OUT_AS_LRC
PXP_PS_CTRLn
PXP_PS_BUF
PXP_PS_UBUF
PXP_PS_VBUF
PXP_PS_PITCH
PXP_PS_BACKGROUND
PXP_PS_SCALE
PXP_PS_OFFSET
PXP_PS_CLRKEYLOW
PXP_PS_CLRKEYHIGH
PXP_AS_CTRL
PXP_AS_BUF
PXP_AS_PITCH
PXP_AS_CLRKEYLOW
PXP_AS_CLRKEYHIGH
PXP_CSC1_COEF0
PXP_CSC1_COEF1
PXP_CSC1_COEF2
PXP_POWER
PXP_NEXT
PXP_PORTER_DUFF_CTRL
Chapter 36-39: Audio
Chapter 36: Audio Overview
Audio Overview
Audio Module Overview
Medium Quality Sound (MQS)
Synchronous Audio Interface (SAI)
Sony/Philips Digital Interface (SPDIF)
Chapter 37: Synchronous Audio Interface (SAI)
Chip-specific SAI information
Introduction
Features
Block diagram
Modes of operation
External signals
Functional description
SAI clocking
SAI resets
Synchronous modes
Frame sync configuration
Data FIFO
Data alignment
FIFO pointers
FIFO packing
FIFO Combine
Word mask register
Interrupts and DMA requests
FIFO request flag
FIFO warning flag
FIFO error flag
Sync error flag
Word start flag
Memory map and register definition
I2S Register Descriptions
I2S Memory Map
Version ID (VERID)
Parameter (PARAM)
SAI Transmit Control (TCSR)
SAI Transmit Configuration 1 (TCR1)
SAI Transmit Configuration 2 (TCR2)
SAI Transmit Configuration 3 (TCR3)
SAI Transmit Configuration 4 (TCR4)
SAI Transmit Configuration 5 (TCR5)
SAI Transmit Data (TDRa)
SAI Transmit FIFO (TFRa)
SAI Transmit Mask (TMR)
SAI Receive Control (RCSR)
SAI Receive Configuration 1 (RCR1)
SAI Receive Configuration 2 (RCR2)
SAI Receive Configuration 3 (RCR3)
SAI Receive Configuration 4 (RCR4)
SAI Receive Configuration 5 (RCR5)
SAI Receive Data (RDRa)
SAI Receive FIFO (RFRa)
SAI Receive Mask (RMR)
Chapter 38: Medium Quality Sound (MQS)
Chip-specific MQS information
Overview
Block Diagram
External Signals
Interface Signals
Programming Considerations
Usage Model
Chapter 39: Sony/Philips Digital Interface (SPDIF)
Chip-specific SPDIF information
Overview
External Signals
Clocks
Functional Description
SPDIF Receiver
Audio Data Reception
Application Note
Channel Status Reception
Channel Status Interrupt
User Bit Reception
Validity Flag Reception
SPDIF Receiver Interrupt Exception Definition
Standards Compliance
SPDIF PLOCK Detection and Rxclk Output
Measuring Frequency of SPDIF_RxClk
SPDIF Transmitter
Audio Data Transmission
Channel Status Transmission
Validity Flag Transmission
SPDIF Memory Map/Register Definition
SPDIF
SPDIF_SCR
SPDIF_SRCD
SPDIF_SRPC
SPDIF_SIE
SPDIF_SIS
SPDIF_SIC
SPDIF_SRL
SPDIF_SRR
SPDIF_SRCSH
SPDIF_SRCSL
SPDIF_SRU
SPDIF_SRQ
SPDIF_STL
SPDIF_STR
SPDIF_STCSCH
SPDIF_STCSCL
SPDIF_SRFM
SPDIF_STC
Chapter 40-42: Connectivity
Chapter 40: 10/100-Mbps Ethernet MAC (ENET)
Chip-specific ENET information
Introduction
Overview
Features
Ethernet MAC features
IP protocol performance optimization features
IEEE 1588 features
Block diagram
External Signals
Clocks
Memory map/register definition
ENETx
ENETx_EIR
ENETx_EIMR
ENETx_RDAR
ENETx_TDAR
ENETx_ECR
ENETx_MMFR
ENETx_MSCR
ENETx_MIBC
ENETx_RCR
ENETx_TCR
ENETx_PALR
ENETx_PAUR
ENETx_OPD
ENETx_TXIC
ENETx_RXIC
ENETx_IAUR
ENETx_IALR
ENETx_GAUR
ENETx_GALR
ENETx_TFWR
ENETx_RDSR
ENETx_TDSR
ENETx_MRBR
ENETx_RSFL
ENETx_RSEM
ENETx_RAEM
ENETx_RAFL
ENETx_TSEM
ENETx_TAEM
ENETx_TAFL
ENETx_TIPG
ENETx_FTRL
ENETx_TACC
ENETx_RACC
ENETx_RMON_T_DROP
ENETx_RMON_T_PACKETS
ENETx_RMON_T_BC_PKT
ENETx_RMON_T_MC_PKT
ENETx_RMON_T_CRC_ALIGN
ENETx_RMON_T_UNDERSIZE
ENETx_RMON_T_OVERSIZE
ENETx_RMON_T_FRAG
ENETx_RMON_T_JAB
ENETx_RMON_T_COL
ENETx_RMON_T_P64
ENETx_RMON_T_P65TO127
ENETx_RMON_T_P128TO255
ENETx_RMON_T_P256TO511
ENETx_RMON_T_P512TO1023
ENETx_RMON_T_P1024TO2047
ENETx_RMON_T_P_GTE2048
ENETx_RMON_T_OCTETS
ENETx_IEEE_T_DROP
ENETx_IEEE_T_FRAME_OK
ENETx_IEEE_T_1COL
ENETx_IEEE_T_MCOL
ENETx_IEEE_T_DEF
ENETx_IEEE_T_LCOL
ENETx_IEEE_T_EXCOL
ENETx_IEEE_T_MACERR
ENETx_IEEE_T_CSERR
ENETx_IEEE_T_SQE
ENETx_IEEE_T_FDXFC
ENETx_IEEE_T_OCTETS_OK
ENETx_RMON_R_PACKETS
ENETx_RMON_R_BC_PKT
ENETx_RMON_R_MC_PKT
ENETx_RMON_R_CRC_ALIGN
ENETx_RMON_R_UNDERSIZE
ENETx_RMON_R_OVERSIZE
ENETx_RMON_R_FRAG
ENETx_RMON_R_JAB
ENETx_RMON_R_RESVD_0
ENETx_RMON_R_P64
ENETx_RMON_R_P65TO127
ENETx_RMON_R_P128TO255
ENETx_RMON_R_P256TO511
ENETx_RMON_R_P512TO1023
ENETx_RMON_R_P1024TO2047
ENETx_RMON_R_P_GTE2048
ENETx_RMON_R_OCTETS
ENETx_IEEE_R_DROP
ENETx_IEEE_R_FRAME_OK
ENETx_IEEE_R_CRC
ENETx_IEEE_R_ALIGN
ENETx_IEEE_R_MACERR
ENETx_IEEE_R_FDXFC
ENETx_IEEE_R_OCTETS_OK
ENETx_ATCR
ENETx_ATVR
ENETx_ATOFF
ENETx_ATPER
ENETx_ATCOR
ENETx_ATINC
ENETx_ATSTMP
ENETx_TGSR
ENETx_TCSRn
ENETx_TCCRn
Functional description
Ethernet MAC frame formats
Pause Frames
Magic packets
IP and higher layers frame format
Ethernet types
IPv4 datagram format
IPv6 datagram format
Internet Control Message Protocol (ICMP) datagram format
User Datagram Protocol (UDP) datagram format
TCP datagram format
IEEE 1588 message formats
Transport encapsulation
UDP/IP
Native Ethernet (PTPv2)
PTP header
PTPv1 header
PTPv2 header
MAC receive
Collision detection in half-duplex mode
Preamble processing
MAC address check
Unicast address check
Multicast and unicast address resolution
Broadcast address reject
Miss-bit implementation
Frame length/type verification: payload length check
Frame length/type verification: frame length check
VLAN frames processing
Pause frame termination
CRC check
Frame padding removal
MAC transmit
Frame payload padding
MAC address insertion
CRC-32 generation
Inter-packet gap (IPG)
Collision detection and handling — half-duplex operation only
Full-duplex flow control operation
Remote device congestion
Local device/FIFO congestion
Magic packet detection
Sleep mode
Magic packet detection
Wakeup
IP accelerator functions
Checksum calculation
Additional padding processing
32-bit Ethernet payload alignment
Receive processing
Transmit processing
Received frame discard
IPv4 fragments
IPv6 support
Receive processing
Transmit processing
Resets and stop controls
Hardware reset
Soft reset
Hardware freeze
Graceful stop
Graceful transmit stop (GTS)
Graceful receive stop (GRS)
Graceful stop interrupt (GRA)
IEEE 1588 functions
Adjustable timer module
Adjustable timer implementation
Timer Synchronization for Multi-Port Implementations
Transmit timestamping
Receive timestamping
Time synchronization
Input Capture and Output Compare
Input capture
Output compare
DMA requests
FIFO thresholds
Receive FIFO
Transmit FIFO
Loopback options
Legacy buffer descriptors
Legacy receive buffer descriptor
Legacy transmit buffer descriptor
Enhanced buffer descriptors
Enhanced receive buffer descriptor
Enhanced transmit buffer descriptor
Client FIFO application interface
Data structure description
Data structure examples
Frame status
FIFO protection
Transmit FIFO underflow
Transmit FIFO overflow
Receive FIFO overflow
PHY management interface
MDIO clause 22 frame format
MDIO clause 45 frame format
MDIO clock generation
MDIO operation
Ethernet interfaces
RMII interface
MII Interface — transmit
Transmit with collision — half-duplex
MII interface — receive
Interrupt coalescence
Interrupt coalescence setup
Updating the frame count threshold on-the-fly
Updating the timer threshold on-the-fly
Chapter 41: Universal Serial Bus Controller (USB)
Chip-specific USB information
Overview
Features
Modes of Operation
Normal Mode
Low-Power Mode
External Signals
Functional Description
USB 2.0 Controller Core 0/1
Host Mode
Peripheral (Device) Mode
USB Power Control
Entering Low Power Suspend Mode
Wake-Up Events
Host Mode Events
Interrupts
USB Core Interrupts
USB Wake-Up Interrupts
USB Operation Model
Register Interface
Configuration, Control and Status Register Set
Identification Registers
OTG Operations
Host Data Structures
Periodic Frame List
Asynchronous List Queue Head Pointer
Isochronous (High-Speed) Transfer Descriptor (iTD)
Next Link Pointer
iTD Transaction Status and Control List
iTD Buffer Page Pointer List (Plus)
Split Transaction Isochronous Transfer Descriptor (siTD)
Next Link Pointer
siTD Endpoint Capabilities/Characteristics
siTD Transfer State
siTD Buffer Pointer List (plus)
siTD Back Link Pointer
Queue element transfer descriptor (qTD)
Next qTD Pointer
Alternate Next qTD Pointer
qTD Token
qTD Buffer Page Pointer List
Queue Head
Queue Head Horizontal Link Pointer
Queue Head Endpoint Capabilities/Characteristics
Transfer Overlay-Queue Head
Periodic Frame Span Traversal Node (FSTN)
FSTN Normal Path Pointer
FSTN Back Path Link Pointer
Host Operational Model
Host Controller Initialization
Port Routing and Control
Port Routing Control through EHCI Configured (CF) Bit
Port Routing Control through PortOwner and Disconnect Event
Example Port Routing State Machine
EHCI HC Owner
Companion HC Owner
Port Power
Port Reporting Over-Current
Suspend/Resume-Host Operational Model
Port Suspend/Resume
Schedule Traversal Rules
Example - Preserving Micro-Frame Integrity
Transaction Fit - A Best-Fit Approximation Algorithm
Periodic Schedule Frame Boundaries vs Bus Frame Boundaries
Periodic Schedule
Managing Isochronous Transfers Using iTDs
Host Controller Operational Model for iTDs
Software Operational Model for iTDs
Periodic scheduling threshold
Asynchronous Schedule
Adding Queue Heads to Asynchronous Schedule
Removing Queue Heads from Asynchronous Schedule
Empty Asynchronous Schedule Detection
Restarting Asynchronous Schedule Before EOF
Example Method for Restarting Asynchronous Schedule Traversal
Async Sched Not Active
Async Sched Active
Async Sched Sleeping
Example Derivation for AsyncSchedSleepTime
Asynchronous schedule traversal: Start Event
Reclamation Status Bit (USBSTS Register)
Operational Model for Nak Counter
Nak Count Reload Control
Wait for List Head
Do Reload
Wait for Start Event
Managing Control/Bulk/Interrupt Transfers through Queue Heads
Fetch Queue Head
Advance Queue
Execute Transaction
Interrupt Transfer Pre-condition Criteria
Asynchronous Transfer Pre-operations and Pre-condition Criteria
Transfer Type Independent Pre-operations
Halting a Queue Head
Asynchronous Schedule Park Mode
Write Back qTD
Follow Queue Head Horizontal Pointer
Buffer Pointer List Use for Data Streaming with qTDs
Adding Interrupt Queue Heads to the Periodic Schedule
Managing Transfer Complete Interrupts from Queue Heads
Ping Control
Split Transactions
Split Transactions for Asynchronous Transfers
Asynchronous - Do Start Split
Asynchronous - Do Complete Split
Split Transaction Interrupt
Split Transaction Scheduling Mechanisms for Interrupt
Host Controller Operational Model for FSTNs
Software Operational Model for FSTNs
Tracking Split Transaction Progress for Interrupt Transfers
Split Transaction Execution State Machine for Interrupt
Rebalancing the periodic schedule
Split Transaction Isochronous
Split Transaction Scheduling Mechanisms for Isochronous
Tracking Split Transaction Progress for Isochronous Transfers
Split Transaction Execution State Machine for Isochronous
Periodic Isochronous - Do Start Split
Periodic Isochronous - Do Complete Split
Complete-Split for Scheduling Boundary Cases 2a, 2b
Split Transaction for Isochronous - Processing Examples
Host Controller Pause
Port Test Modes -Host Operational Model
Interrupts-Host Operational Model
Transfer/Transaction Based Interrupts
Transaction Error
Serial Bus Babble
Data Buffer Error
USB Interrupt (Interrupt on Completion (IOC))
Short Packet
Host Controller Event Interrupts
Port Change Events
Frame List Rollover
Interrupt on Async Advance
Host System Error
EHCI Deviation
Embedded Transaction Translator Function
Capability Registers
Operational Registers
Discovery-EHCI Deviation
Data Structures
Operational Model
Micro- frame Pipeline
Split State Machines
Asynchronous Transaction Scheduling and Buffer Management
USB 2.0 - 11.17.3
USB 2.0 - 11.17.4
Periodic Transaction Scheduling and Buffer Management
USB 2.0 - 11.18.6.[1-2]
USB 2.0 - 11.18.[7-8]
Multiple Transaction Translators
Device Operation
USB_USBMODE Register
Non-Zero Fields the Register File
SOF Interrupt
Embedded Design Interface
Frame Adjust Register
Miscellaneous variations from EHCI
Programmable Physical Interface Behaviour
Discovery
Port Reset
Port Speed Detection
Port Test Mode
Device Data Structures
Endpoint Queue Head (dQH)
Endpoint Capabilities/Characteristics
Transfer Overlay-Endpoint Queue Head
Current dTD Pointer
Set-up Buffer
Endpoint Transfer Descriptor (dTD)
Device Operational Model
Device Controller Initialization
Port State and Control
Bus Reset
Suspend/Resume
Suspend
Resume
Managing Endpoints
Endpoint Initialization
Stalling
Data Toggle
Data Toggle Reset
Data Toggle Inhibit
Priming Transmit Endpoints
Priming Receive Endpoints
Operational Model For Packet Transfers
Interrupt/Bulk Endpoint Operational Model
Interrupt/Bulk Endpoint Bus Response Matrix
Control Endpoint Operation Model
Setup Phase
Data Phase
Status Phase
Control Endpoint Bus Response Matrix
Isochronous Endpoint Operational Model
Isochronous Pipe Synchronization
Isochronous Endpoint Bus Response Matrix
Managing Queue Heads
Queue Head Initialization
Operational Model For Setup Transfers
Managing Transfers with Transfer Descriptors
Software Link Pointers
Building a Transfer Descriptor
Executing A Transfer Descriptor
Transfer Completion
Flushing/De-priming an Endpoint
Device Error Matrix
Servicing Interrupts
High-Frequency Interrupts
Low-Frequency Interrupts
Error Interrupts
USB Non-Core Memory Map/Register Definition
USBNC
USBNC_USB_OTG1_CTRL
USBNC_USB_OTG2_CTRL
USBNC_USB_OTG1_PHY_CTRL_0
USBNC_USB_OTG2_PHY_CTRL_0
USB Core Memory Map/Register Definition
USB
USB_nID
USB_nHWGENERAL
USB_nHWHOST
USB_nHWDEVICE
USB_nHWTXBUF
USB_nHWRXBUF
USB_nGPTIMER0LD
USB_nGPTIMER0CTRL
USB_nGPTIMER1LD
USB_nGPTIMER1CTRL
USB_nSBUSCFG
USB_nCAPLENGTH
USB_nHCIVERSION
USB_nHCSPARAMS
USB_nHCCPARAMS
USB_nDCIVERSION
USB_nDCCPARAMS
USB_nUSBCMD
USB_nUSBSTS
USB_nUSBINTR
USB_nFRINDEX
USB_nPERIODICLISTBASE
USB_nDEVICEADDR
USB_nASYNCLISTADDR
USB_nENDPTLISTADDR
USB_nBURSTSIZE
USB_nTXFILLTUNING
USB_nENDPTNAK
USB_nENDPTNAKEN
USB_nCONFIGFLAG
USB_nPORTSC1
USB_nOTGSC
USB_nUSBMODE
USB_nENDPTSETUPSTAT
USB_nENDPTPRIME
USB_nENDPTFLUSH
USB_nENDPTSTAT
USB_nENDPTCOMPLETE
USB_nENDPTCTRL0
USB_nENDPTCTRL1
USB_nENDPTCTRL2
USB_nENDPTCTRL3
USB_nENDPTCTRL4
USB_nENDPTCTRL5
USB_nENDPTCTRL6
USB_nENDPTCTRL7
Chapter 42: Universal Serial Bus 2.0 Integrated PHY (USB-PHY)
Chip-specific USB-PHY information
USB PHY Overview
Operation
UTMI
Digital Transmitter
Digital Receiver
Analog Receiver
HS Differential Receiver
Squelch Detector
LS/FS Differential Receiver
HS Disconnect Detector
USB Plugged-In Detector
Single-Ended USB_DP Receiver
Single-Ended USB_DN Receiver
9X Oversample Module
Analog Transmitter
Switchable High-Speed 45Ω Termination Resistors
Low-Speed/Full-Speed Differential Driver
High-Speed Differential Driver
Switchable 1.5KΩ USB_DP Pullup Resistor
Switchable 15KΩ USB_DP Pulldown Resistor
Recommended Register Configuration for USB Certification
Charger detection
Charger detect control table
Data pin contact detector
Charger detector
Charger detection software flow
Dead Battery Protect
USB PHY Memory Map/Register Definition
USBPHYx
USBPHYx_PWDn
USBPHYx_TXn
USBPHYx_RXn
USBPHYx_CTRLn
USBPHYx_STATUS
USBPHYx_DEBUGn
USBPHYx_DEBUG0_STATUS
USBPHYx_DEBUG1n
USBPHYx_VERSION
USB Analog Memory Map/Register Definition
USB_ANALOG
USB_ANALOG_USB1_VBUS_DETECTn
USB_ANALOG_USB1_CHRG_DETECTn
USB_ANALOG_USB1_VBUS_DETECT_STAT
USB_ANALOG_USB1_CHRG_DETECT_STAT
USB_ANALOG_USB1_MISCn
USB_ANALOG_USB2_VBUS_DETECTn
USB_ANALOG_USB2_CHRG_DETECTn
USB_ANALOG_USB2_VBUS_DETECT_STAT
USB_ANALOG_USB2_CHRG_DETECT_STAT
USB_ANALOG_USB2_MISCn
USB_ANALOG_DIGPROG
Chapter 43-49: Low Speed Peripherals Commuication
Chapter 43: Flexible Controller Area Network (FLEXCAN)
Chip-specific FLEXCAN information
Overview
Block Diagram
FLEXCAN Module Features
Modes of Operation
External Signals
Clocks
Message Buffer Structure
Rx FIFO Structure
Functional Description
Functional Overview
Transmit Process
Arbitration process
Lowest Mailbox number first
Highest Mailbox priority first
Local Priority disabled
Local Priority enabled
Receive Process
Matching Process
Move Process
Move-in
Move-out
Data Coherence
Transmission Abort Mechanism
Message Buffer Inactivation
Message Buffer Lock Mechanism
Rx FIFO
CAN Protocol Related Features
Remote Frames
Overload Frames
Time Stamp
Protocol Timing
Arbitration and Matching Timing
Modes of Operation Details
Freeze Mode
Module Disable Mode
Stop Mode
Interrupts
Initialization/Application Information
FLEXCAN Initialization Sequence
FLEXCAN Memory Map/Register Definition
FLEXCANx
FLEXCANx_MCR
FLEXCANx_CTRL1
FLEXCANx_TIMER
FLEXCANx_RXMGMASK
FLEXCANx_RX14MASK
FLEXCANx_RX15MASK
FLEXCANx_ECR
FLEXCANx_ESR1
FLEXCANx_IMASK2
FLEXCANx_IMASK1
FLEXCANx_IFLAG2
FLEXCANx_IFLAG1
FLEXCANx_CTRL2
FLEXCANx_ESR2
FLEXCANx_CRCR
FLEXCANx_RXFGMASK
FLEXCANx_RXFIR
FLEXCANx_DBG1
FLEXCANx_DBG2
FLEXCANx_RXIMRn
FLEXCANx_GFWR
Chapter 44: Flexible Data-rate Controller Area Network (CANFD/FlexCAN3)
Chip-specific FLEXCAN information
Introduction
Overview
FlexCAN module features
Modes of operation
FlexCAN signal descriptions
CAN Rx
CAN Tx
Functional description
Transmit process
Arbitration process
Lowest-number Mailbox first
Highest-priority Mailbox first
Local Priority disabled
Local Priority enabled
Arbitration process (continued)
Receive process
Matching process
Move process
Move-in
Move-out
Data coherence
Transmission abort mechanism
Mailbox inactivation
Mailbox lock mechanism
Enhanced Rx FIFO
Enhanced Rx FIFO matching process
Enhanced Rx FIFO under DMA operation
Enhanced Rx FIFO clear operation
Legacy Rx FIFO
Legacy Rx FIFO under DMA Operation
Clear Legacy FIFO Operation
CAN protocol related features
CAN FD ISO compliance
CAN FD frames
Transceiver Delay Compensation
Remote frames
Overload frames
Message buffer time stamp
High resolution time stamp
Protocol timing
Arbitration and matching timing
Tx Arbitration start delay
Clock domains and restrictions
Modes of operation details
Freeze mode
Module Disable mode
Doze mode
Stop mode
Interrupts
Bus interface
Initialization/application information
FlexCAN initialization sequence
Memory map/register definition
FlexCAN memory mapping
CAN register descriptions
CAN Memory map
Module Configuration Register (MCR)
Control 1 register (CTRL1)
Free Running Timer (TIMER)
Rx Mailboxes Global Mask Register (RXMGMASK)
Rx 14 Mask register (RX14MASK)
Rx 15 Mask register (RX15MASK)
Error Counter (ECR)
Error and Status 1 register (ESR1)
Interrupt Masks 2 register (IMASK2)
Interrupt Masks 1 register (IMASK1)
Interrupt Flags 2 register (IFLAG2)
Interrupt Flags 1 register (IFLAG1)
Control 2 register (CTRL2)
Error and Status 2 register (ESR2)
CRC Register (CRCR)
Legacy Rx FIFO Global Mask register (RXFGMASK)
Legacy Rx FIFO Information Register (RXFIR)
CAN Bit Timing Register (CBT)
Rx Individual Mask Registers (RXIMR0 - RXIMR63)
Enhanced CAN Bit Timing Prescalers (EPRS)
Enhanced Nominal CAN Bit Timing (ENCBT)
Enhanced Data Phase CAN bit Timing (EDCBT)
Enhanced Transceiver Delay Compensation (ETDC)
CAN FD Control Register (FDCTRL)
CAN FD Bit Timing Register (FDCBT)
CAN FD CRC Register (FDCRC)
Enhanced Rx FIFO Control Register (ERFCR)
Enhanced Rx FIFO Interrupt Enable register (ERFIER)
Enhanced Rx FIFO Status Register (ERFSR)
High Resolution Time Stamp (HR_TIME_STAMP0 - HR_TIME_STAMP63)
Enhanced Rx FIFO Filter Element (ERFFEL0 - ERFFEL127)
Message buffer structure
FlexCAN Memory Partition for CAN FD
FlexCAN message buffer memory map
Legacy Rx FIFO structure
Enhanced Rx FIFO structure
Chapter 45: Keypad Port (KPP)
Chip-specific KPP information
Overview
Features
Modes and Operations
Clocks
External Signals
Input Pins
Output Pins
Generation of Transfer Error Signal on Peripheral Bus
Functional Description
Keypad Matrix Construction
Keypad Port Configuration
Keypad Matrix Scanning
Keypad Standby
Glitch Suppression on Keypad Inputs
Multiple Key Closures
Ghost Key Problem and Correction
3-Point Contact Keys Support
Initialization/Application Information
Typical Keypad Configuration and Scanning Sequence
Key Press Interrupt Scanning Sequence
Additional Comments
KPP Memory Map/Register Definition
KPP
KPP_KPCR
KPP_KPSR
KPP_KDDR
KPP_KPDR
Chapter 46: Low Power Inter-Integrated Circuit (LPI2C)
Chip-specific LPI2C information
Introduction
Features
Block Diagram
Modes of operation
Signal Descriptions
Wiring options
Functional description
Clocking and Resets
Master Mode
Slave Mode
Interrupts and DMA Requests
Peripheral Triggers
Memory Map and Registers
LPI2C register descriptions
LPI2C Memory map
Version ID Register (VERID)
Parameter Register (PARAM)
Master Control Register (MCR)
Master Status Register (MSR)
Master Interrupt Enable Register (MIER)
Master DMA Enable Register (MDER)
Master Configuration Register 0 (MCFGR0)
Master Configuration Register 1 (MCFGR1)
Master Configuration Register 2 (MCFGR2)
Master Configuration Register 3 (MCFGR3)
Master Data Match Register (MDMR)
Master Clock Configuration Register 0 (MCCR0)
Master Clock Configuration Register 1 (MCCR1)
Master FIFO Control Register (MFCR)
Master FIFO Status Register (MFSR)
Master Transmit Data Register (MTDR)
Master Receive Data Register (MRDR)
Slave Control Register (SCR)
Slave Status Register (SSR)
Slave Interrupt Enable Register (SIER)
Slave DMA Enable Register (SDER)
Slave Configuration Register 1 (SCFGR1)
Slave Configuration Register 2 (SCFGR2)
Slave Address Match Register (SAMR)
Slave Address Status Register (SASR)
Slave Transmit ACK Register (STAR)
Slave Transmit Data Register (STDR)
Slave Receive Data Register (SRDR)
Chapter 47: Low Power Serial Peripheral Interface (LPSPI)
Chip-specific LPSPI information
Introduction
Features
Block Diagram
Modes of operation
Signal Descriptions
Functional description
Clocking and Resets
Master Mode
Slave Mode
Interrupts and DMA Requests
Peripheral Triggers
Memory Map and Registers
LPSPI register descriptions
LPSPI Memory map
Version ID Register (VERID)
Parameter Register (PARAM)
Control Register (CR)
Status Register (SR)
Interrupt Enable Register (IER)
DMA Enable Register (DER)
Configuration Register 0 (CFGR0)
Configuration Register 1 (CFGR1)
Data Match Register 0 (DMR0)
Data Match Register 1 (DMR1)
Clock Configuration Register (CCR)
FIFO Control Register (FCR)
FIFO Status Register (FSR)
Transmit Command Register (TCR)
Transmit Data Register (TDR)
Receive Status Register (RSR)
Receive Data Register (RDR)
Chapter 48: Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
Chip-specific LPUART information
Introduction
Features
Modes of operation
Signal Descriptions
Block diagram
Functional description
Clocking and Resets
Baud rate generation
Transmitter functional description
Send break and queued idle
Hardware flow control
Transceiver driver enable
Transceiver driver enable using RTS_B
Receiver functional description
Data sampling technique
Receiver wakeup operation
Idle-line wakeup
Address-mark wakeup
Data match wakeup
Address Match operation
Idle Match operation
Match On Match Off operation
Hardware flow control
Infrared decoder
Start bit detection
Noise filtering
Low-bit detection
High-bit detection
Additional LPUART functions
Data Modes
Idle length
Loop mode
Single-wire operation
Infrared interface
Infrared transmit encoder
Infrared receive decoder
Interrupts and status flags
Peripheral Triggers
Register definition
LPUART register descriptions
LPUART Memory map
Version ID Register (VERID)
Parameter Register (PARAM)
LPUART Global Register (GLOBAL)
LPUART Pin Configuration Register (PINCFG)
LPUART Baud Rate Register (BAUD)
LPUART Status Register (STAT)
LPUART Control Register (CTRL)
LPUART Data Register (DATA)
LPUART Match Address Register (MATCH)
LPUART Modem IrDA Register (MODIR)
LPUART FIFO Register (FIFO)
LPUART Watermark Register (WATER)
Chapter 49: Flexible I/O (FlexIO)
Chip-specific FlexIO information
Introduction
Features
Block Diagram
Modes of operation
FlexIO Signal Descriptions
Memory Map and Registers
FLEXIO register descriptions
FLEXIO Memory map
Version ID Register (VERID)
Parameter Register (PARAM)
FlexIO Control Register (CTRL)
Pin State Register (PIN)
Shifter Status Register (SHIFTSTAT)
Shifter Error Register (SHIFTERR)
Timer Status Register (TIMSTAT)
Shifter Status Interrupt Enable (SHIFTSIEN)
Shifter Error Interrupt Enable (SHIFTEIEN)
Timer Interrupt Enable Register (TIMIEN)
Shifter Status DMA Enable (SHIFTSDEN)
Shifter State Register (SHIFTSTATE)
Shifter Control N Register (SHIFTCTL0 - SHIFTCTL7)
Shifter Configuration N Register (SHIFTCFG0 - SHIFTCFG7)
Shifter Buffer N Register (SHIFTBUF0 - SHIFTBUF7)
Shifter Buffer N Bit Swapped Register (SHIFTBUFBIS0 - SHIFTBUFBIS7)
Shifter Buffer N Byte Swapped Register (SHIFTBUFBYS0 - SHIFTBUFBYS7)
Shifter Buffer N Bit Byte Swapped Register (SHIFTBUFBBS0 - SHIFTBUFBBS7)
Timer Control N Register (TIMCTL0 - TIMCTL7)
Timer Configuration N Register (TIMCFG0 - TIMCFG7)
Timer Compare N Register (TIMCMP0 - TIMCMP7)
Shifter Buffer N Nibble Byte Swapped Register (SHIFTBUFNBS0 - SHIFTBUFNBS7)
Shifter Buffer N Half Word Swapped Register (SHIFTBUFHWS0 - SHIFTBUFHWS7)
Shifter Buffer N Nibble Swapped Register (SHIFTBUFNIS0 - SHIFTBUFNIS7)
Functional description
Clocking and Resets
Shifter operation
Timer Operation
Pin operation
Interrupts and DMA Requests
Peripheral Triggers
Application Information
UART Transmit
UART Receive
SPI Master
SPI Slave
I2C Master
I2S Master
I2S Slave
Camera Interface
Motorola 68K/Intel 8080 Bus Interface
Low Power State Machine
Chapter 50-58: Timers
Chapter 50: Timers Overview
Overview
General Purpose Timer (GPT)
Periodic Interrupt Timer (PIT)
Quad Timer (TMR)
Enhanced Flex Pulse Width Modulator (eFlexPWM)
Quadrature Encoder/Decoder (ENC)
Watchdog Timer (WDOG1,2)
Watchdog Timer (RTWDOG /WDOG3)
External Watchdog Monitor (EWM)
Chapter 51: General Purpose Timer (GPT)
Chip-specific GPT information
Overview
Features
Modes and Operation
External Signals
External Clock Input
Input Capture Trigger Signals
Output Compare Signals
Clocks
Functional Description
Operating Modes
Restart Mode
Free-Run Mode
Operation
Input Capture
Output Compare
Interrupts
Low Power Mode Behavior
Debug Mode Behavior
Initialization/ Application Information
Selecting the Clock Source
GPT Memory Map/Register Definition
GPTx
GPTx_CR
GPTx_PR
GPTx_SR
GPTx_IR
GPTx_OCR1
GPTx_OCR2
GPTx_OCR3
GPTx_ICR1
GPTx_ICR2
GPTx_CNT
Chapter 52: Periodic Interrupt Timer (PIT)
Chip-specific PIT information
Introduction
Block diagram
Features
Modes of operation
PIT External Signals
Functional description
General operation
Timers
Debug mode
Interrupts
Chained timers
Initialization and application information
Example configuration for chained timers
Example configuration for the lifetime timer
PIT register descriptions
PIT Memory map
PIT Module Control Register (MCR)
PIT Upper Lifetime Timer Register (LTMR64H)
PIT Lower Lifetime Timer Register (LTMR64L)
Timer Load Value Register (LDVAL0 - LDVAL3)
Current Timer Value Register (CVAL0 - CVAL3)
Timer Control Register (TCTRL0 - TCTRL3)
Timer Flag Register (TFLG0 - TFLG3)
Chapter 53: Quad Timer (TMR)
Chip-specific TMR information
Overview
Features
Modes of Operation
Block Diagram
Memory Map and Registers
TMRx
TMRx_COMP1n
TMRx_COMP2n
TMRx_CAPTn
TMRx_LOADn
TMRx_HOLDn
TMRx_CNTRn
TMRx_CTRLn
TMRx_SCTRLn
TMRx_CMPLD1n
TMRx_CMPLD2n
TMRx_CSCTRLn
TMRx_FILTn
TMRx_DMAn
TMRx_ENBL
Functional Description
General
Usage of Compare Registers
Usage of Compare Load Registers
Usage of the Capture Register
Functional Modes
Stop Mode
Count Mode
Edge-Count Mode
Gated-Count Mode
Quadrature-Count Mode
Quadrature-Count Mode with Index Input
Signed-Count Mode
Triggered-Count Mode 1
Triggered-Count Mode 2
One-Shot Mode
Cascade-Count Mode
Pulse-Output Mode
Fixed-Frequency PWM Mode
Variable-Frequency PWM Mode
Resets
General
Clocks
General
Interrupts
General
Description of Interrupt Operation
Timer Compare Interrupts
Timer Compare 1 Interrupts (Available with Compare Load Feature)
Timer Compare 2 Interrupts (Available with Compare Load Feature)
Timer Overflow Interrupts
Timer Input Edge Interrupts
DMA
Chapter 54: Enhanced Flex Pulse Width Modulator (eFlexPWM)
Chip-specific FlexPWM information
Introduction
Features
Modes of Operation
Block Diagram
PWM Submodule
Signal Descriptions
PWM[n]_A and PWM[n]_B - External PWM Output Pair
PWM[n]_X - Auxiliary PWM Output signal
FAULT[n] - Fault Inputs
PWM[n]_EXT_SYNC - External Synchronization Signal
EXT_FORCE - External Output Force Signal
PWM[n]_EXTA and PWM[n]_EXTB - Alternate PWM Control Signals
PWM[n]_OUT_TRIG0 and PWM[n]_OUT_TRIG1 - Output Triggers
EXT_CLK - External Clock Signal
Functional Description
PWM Capabilities
Center Aligned PWMs
Edge Aligned PWMs
Phase Shifted PWMs
Double Switching PWMs
ADC Triggering
Enhanced Capture Capabilities (E-Capture)
Synchronous Switching of Multiple Outputs
Functional Details
PWM Clocking
Register Reload Logic
Counter Synchronization
PWM Generation
Output Compare Capabilities
Force Out Logic
Independent or Complementary Channel Operation
Deadtime Insertion Logic
Top/Bottom Correction
Manual Correction
Fractional Delay Logic
Fractional Delay Logic with NanoEdge Placement Block
Fractional Delay Logic without NanoEdge Placement Block
Output Logic
E-Capture
Fault Protection
Fault Pin Filter
Automatic Fault Clearing
Manual Fault Clearing
Fault Testing
PWM Generator Loading
Load Enable
Load Frequency
Reload Flag
Reload Errors
Initialization
Resets
Interrupts
DMA
PWM register descriptions
PWM Memory map
Counter Register (SM0CNT - SM3CNT)
Initial Count Register (SM0INIT - SM3INIT)
Control 2 Register (SM0CTRL2 - SM3CTRL2)
Control Register (SM0CTRL - SM3CTRL)
Value Register 0 (SM0VAL0 - SM3VAL0)
Fractional Value Register 1 (SM0FRACVAL1 - SM3FRACVAL1)
Value Register 1 (SM0VAL1 - SM3VAL1)
Fractional Value Register 2 (SM0FRACVAL2 - SM3FRACVAL2)
Value Register 2 (SM0VAL2 - SM3VAL2)
Fractional Value Register 3 (SM0FRACVAL3 - SM3FRACVAL3)
Value Register 3 (SM0VAL3 - SM3VAL3)
Fractional Value Register 4 (SM0FRACVAL4 - SM3FRACVAL4)
Value Register 4 (SM0VAL4 - SM3VAL4)
Fractional Value Register 5 (SM0FRACVAL5 - SM3FRACVAL5)
Value Register 5 (SM0VAL5 - SM3VAL5)
Fractional Control Register (SM0FRCTRL - SM3FRCTRL)
Output Control Register (SM0OCTRL - SM3OCTRL)
Status Register (SM0STS - SM3STS)
Interrupt Enable Register (SM0INTEN - SM3INTEN)
DMA Enable Register (SM0DMAEN - SM3DMAEN)
Output Trigger Control Register (SM0TCTRL - SM3TCTRL)
Fault Disable Mapping Register 0 (SM0DISMAP0 - SM3DISMAP0)
Fault Disable Mapping Register 1 (SM0DISMAP1 - SM3DISMAP1)
Deadtime Count Register 0 (SM0DTCNT0 - SM3DTCNT0)
Deadtime Count Register 1 (SM0DTCNT1 - SM3DTCNT1)
Capture Control A Register (SM0CAPTCTRLA - SM3CAPTCTRLA)
Capture Compare A Register (SM0CAPTCOMPA - SM3CAPTCOMPA)
Capture Control B Register (SM0CAPTCTRLB - SM3CAPTCTRLB)
Capture Compare B Register (SM0CAPTCOMPB - SM3CAPTCOMPB)
Capture Control X Register (SM0CAPTCTRLX - SM3CAPTCTRLX)
Capture Compare X Register (SM0CAPTCOMPX - SM3CAPTCOMPX)
Capture Value 0 Register (SM0CVAL0 - SM3CVAL0)
Capture Value 0 Cycle Register (SM0CVAL0CYC - SM3CVAL0CYC)
Capture Value 1 Register (SM0CVAL1 - SM3CVAL1)
Capture Value 1 Cycle Register (SM0CVAL1CYC - SM3CVAL1CYC)
Capture Value 2 Register (SM0CVAL2 - SM3CVAL2)
Capture Value 2 Cycle Register (SM0CVAL2CYC - SM3CVAL2CYC)
Capture Value 3 Register (SM0CVAL3 - SM3CVAL3)
Capture Value 3 Cycle Register (SM0CVAL3CYC - SM3CVAL3CYC)
Capture Value 4 Register (SM0CVAL4 - SM3CVAL4)
Capture Value 4 Cycle Register (SM0CVAL4CYC - SM3CVAL4CYC)
Capture Value 5 Register (SM0CVAL5 - SM3CVAL5)
Capture Value 5 Cycle Register (SM0CVAL5CYC - SM3CVAL5CYC)
Output Enable Register (OUTEN)
Mask Register (MASK)
Software Controlled Output Register (SWCOUT)
PWM Source Select Register (DTSRCSEL)
Master Control Register (MCTRL)
Master Control 2 Register (MCTRL2)
Fault Control Register (FCTRL0)
Fault Status Register (FSTS0)
Fault Filter Register (FFILT0)
Fault Test Register (FTST0)
Fault Control 2 Register (FCTRL20)
Chapter 55: Quadrature Encoder/Decoder (ENC)
Chip-specific ENC information
Introduction
Features
System Block Diagram
Decoder Block Diagram
Glitch Filter
Edge Detect State Machine
Position Counter
Position Difference Counter
Position Difference Counter Hold
Revolution Counter
Watchdog Timer
Pulse Accumulator Functionality
Signal Descriptions
Functional Description
Positive versus Negative Direction
Prescaler for Slow or Fast Speed Measurement
Holding Registers and Initializing Registers
Resets
Clocks
Interrupts
ENC register descriptions
ENC Memory map
Control Register (CTRL)
Input Filter Register (FILT)
Watchdog Timeout Register (WTR)
Position Difference Counter Register (POSD)
Position Difference Hold Register (POSDH)
Revolution Counter Register (REV)
Revolution Hold Register (REVH)
Upper Position Counter Register (UPOS)
Lower Position Counter Register (LPOS)
Upper Position Hold Register (UPOSH)
Lower Position Hold Register (LPOSH)
Upper Initialization Register (UINIT)
Lower Initialization Register (LINIT)
Input Monitor Register (IMR)
Test Register (TST)
Control 2 Register (CTRL2)
Upper Modulus Register (UMOD)
Lower Modulus Register (LMOD)
Upper Position Compare Register (UCOMP)
Lower Position Compare Register (LCOMP)
Chapter 56: Watchdog Timer (WDOG1-2)
Chip-specific WDOG information
Overview
Features
External signals
Clocks
Watchdog mechanism and system integration
Functional description
Timeout event
Servicing WDOG to reload the counter
Interrupt event
Power-down counter event
Low power modes
STOP and DOZE mode
WAIT mode
Debug mode
Operations
Watchdog reset generation
WDOG_B generation
Reset
Interrupt
Flow Diagrams
Initialization
WDOG Memory Map/Register Definition
WDOG Register Descriptions
WDOG Memory Map
Watchdog Control (WCR)
Watchdog Service (WSR)
Watchdog Reset Status (WRSR)
Watchdog Interrupt Control (WICR)
Watchdog Miscellaneous Control (WMCR)
Chapter 57: RTWDOG (WDOG3)
Chip-specific RTWDOG information
Introduction
Features
Block diagram
Functional description
Clock source
Watchdog refresh mechanism
Window mode
Refreshing the Watchdog
Using interrupts to delay resets
Backup reset
Functionality in debug and low-power modes
Fast testing of the watchdog
Testing each byte of the counter
Entering user mode
Application Information
Memory map and register definition
WDOG Register Descriptions
WDOG Memory Map
Watchdog Control and Status (CS)
Watchdog Counter (CNT)
Watchdog Timeout Value (TOVAL)
Watchdog Window (WIN)
Chapter 58: External Watchdog Monitor (EWM)
Chip-specific EWM information
Introduction
Features
Modes of Operation
Stop Mode
Wait Mode
Debug Mode
Block Diagram
EWM Signal Descriptions
Memory Map/Register Definition
EWM register descriptions
EWM Memory map
Control Register (CTRL)
Service Register (SERV)
Compare Low Register (CMPL)
Compare High Register (CMPH)
Clock Control Register (CLKCTRL)
Clock Prescaler Register (CLKPRESCALER)
Functional Description
The EWM_OUT_b Signal
EWM_OUT_b pin state in low power modes
The EWM_in Signal
EWM Counter
EWM Compare Registers
EWM Refresh Mechanism
EWM Interrupt
Selecting the EWM counter clock
Counter clock prescaler
Chapter 59-62: On Chip Cross Triggers
Chapter 59: On Chip Cross Triggers Overview
Overview
Cross BAR (XBAR)
And-Or-Inverter (AOI)
Chapter 60: Inter-Peripheral Crossbar Switch A (XBARA)
Chip-specific XBAR information
Introduction
Overview
Features
Modes of Operation
Block Diagram
Signal Descriptions
XBAR_OUT[0:NUM_OUT-1] - MUX Outputs
XBAR_IN[0:NUM_IN-1] - MUX Inputs
DMA_REQ[n] - DMA Request Output(s)
DMA_ACK[n] - DMA Acknowledge Input(s)
INT_REQ[n] - Interrupt Request Output(s)
Memory Map and Register Descriptions
XBARAx
XBARAx_SEL0
XBARAx_SEL1
XBARAx_SEL2
XBARAx_SEL3
XBARAx_SEL4
XBARAx_SEL5
XBARAx_SEL6
XBARAx_SEL7
XBARAx_SEL8
XBARAx_SEL9
XBARAx_SEL10
XBARAx_SEL11
XBARAx_SEL12
XBARAx_SEL13
XBARAx_SEL14
XBARAx_SEL15
XBARAx_SEL16
XBARAx_SEL17
XBARAx_SEL18
XBARAx_SEL19
XBARAx_SEL20
XBARAx_SEL21
XBARAx_SEL22
XBARAx_SEL23
XBARAx_SEL24
XBARAx_SEL25
XBARAx_SEL26
XBARAx_SEL27
XBARAx_SEL28
XBARAx_SEL29
XBARAx_SEL30
XBARAx_SEL31
XBARAx_SEL32
XBARAx_SEL33
XBARAx_SEL34
XBARAx_SEL35
XBARAx_SEL36
XBARAx_SEL37
XBARAx_SEL38
XBARAx_SEL39
XBARAx_SEL40
XBARAx_SEL41
XBARAx_SEL42
XBARAx_SEL43
XBARAx_SEL44
XBARAx_SEL45
XBARAx_SEL46
XBARAx_SEL47
XBARAx_SEL48
XBARAx_SEL49
XBARAx_SEL50
XBARAx_SEL51
XBARAx_SEL52
XBARAx_SEL53
XBARAx_SEL54
XBARAx_SEL55
XBARAx_SEL56
XBARAx_SEL57
XBARAx_SEL58
XBARAx_SEL59
XBARAx_SEL60
XBARAx_SEL61
XBARAx_SEL62
XBARAx_SEL63
XBARAx_SEL64
XBARAx_SEL65
XBARAx_CTRL0
XBARAx_CTRL1
Functional Description
General
Functional Mode
Resets
Clocks
Interrupts and DMA Requests
Chapter 61: Inter-Peripheral Crossbar Switch B (XBARB)
Chip-specific XBAR information
Introduction
Memory Map and Register Descriptions
XBARBx
XBARBx_SEL0
XBARBx_SEL1
XBARBx_SEL2
XBARBx_SEL3
XBARBx_SEL4
XBARBx_SEL5
XBARBx_SEL6
XBARBx_SEL7
Chapter 62: And-Or-Inverter (AOI)
Chip-specific AOI information
Introduction
Overview
Features
Modes of Operation
External Signal Description
Memory Map and Register Descriptions
AOIx
AOIx_BFCRT01n
AOIx_BFCRT23n
Functional Description
Configuration Examples for the Boolean Function Evaluation
AOI Timing Between Inputs and Outputs
Chapter 63-67: Analog
Chapter 63: Analog Overview
Overview
Analog-to-Digital Converter (ADC)
Touch Screen Control (TSC)
ADC External Trigger Control (ADC_ETC)
Analog Comparator (ACMP)
Chapter 64: Analog Comparator (ACMP)
Chip-specific CMP information
Introduction
CMP features
6-bit DAC key features
ANMUX key features
CMP, DAC and ANMUX diagram
CMP block diagram
Memory map/register definitions
CMPx
CMPx_CR0
CMPx_CR1
CMPx_FPR
CMPx_SCR
CMPx_DACCR
CMPx_MUXCR
Functional description
CMP functional modes
Disabled mode (# 1)
Continuous mode (#s 2A & 2B)
Sampled, Non-Filtered mode (#s 3A & 3B)
Sampled, Filtered mode (#s 4A & 4B)
Windowed mode (#s 5A & 5B)
Windowed/Resampled mode (# 6)
Windowed/Filtered mode (#7)
Power modes
Wait mode operation
Stop mode operation
Startup and operation
Low-pass filter
Enabling filter modes
Latency issues
CMP interrupts
DMA support
Digital-to-analog converter
DAC functional description
Voltage reference source select
DAC resets
DAC clocks
DAC interrupts
Chapter 65: Analog-to-Digital Converter (ADC)
Chip-specific ADC information
Overview
Features
ADC I/F block diagram
ADC block diagram
ADC module interface
Modes of Operation
External Signals
Clocks
Functional Description
Clock Select and Divide Control
Voltage Reference Selection
Hardware Triggering and Channel Selection
Conversion Control
Initiating Conversions
Completing Conversions
Aborting Conversions
Power Control
Sample Time and Total Conversion Time
Conversion Time Examples
Typical conversion time configuration
Long conversion time configuration
Short conversion time configuration
Hardware Average Function
Automatic Compare Function
Calibration Function
User Defined Offset Function
MCU Wait Mode Operation
MCU Stop Mode Operation
Stop Mode With ADACK Disabled
Stop Mode With ADACK Enabled
Initialization Information
ADC Module Initialization Example
Initialization Sequence
Pseudo-Code Example
Application Information
Sources of Error
Sampling Error
Pin Leakage Error
Noise-Induced Errors
Code Width and Quantization Error
Linearity Errors
Code Jitter, Non-Monotonicity, and Missing Codes
Memory map and register definition
ADCx
ADCx_HC0
ADCx_HCn
ADCx_HS
ADCx_R0
ADCx_Rn
ADCx_CFG
ADCx_GC
ADCx_GS
ADCx_CV
ADCx_OFS
ADCx_CAL
Chapter 66: ADC External Trigger Control (ADC_ETC)
Chip-specific ADC_ETC information
About this module
Introduction
Features
Block diagram
Functional description
Clocks
Reset
Operations
Memory Map and register definition
ADC_ETC register descriptions
ADC_ETC Memory map
ADC_ETC Global Control Register (CTRL)
ETC DONE0 and DONE1 IRQ State Register (DONE0_1_IRQ)
ETC DONE_2 and DONE_ERR IRQ State Register (DONE2_ERR_IRQ)
ETC DMA control Register (DMA_CTRL)
ETC_TRIG0 Control Register (TRIG0_CTRL)
ETC_TRIG0 Counter Register (TRIG0_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG0_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG0_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG0_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG0_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG0_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG0_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG0_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG0_RESULT_7_6)
ETC_TRIG1 Control Register (TRIG1_CTRL)
ETC_TRIG1 Counter Register (TRIG1_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG1_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG1_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG1_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG1_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG1_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG1_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG1_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG1_RESULT_7_6)
ETC_TRIG2 Control Register (TRIG2_CTRL)
ETC_TRIG2 Counter Register (TRIG2_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG2_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG2_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG2_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG2_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG2_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG2_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG2_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG2_RESULT_7_6)
ETC_TRIG3 Control Register (TRIG3_CTRL)
ETC_TRIG3 Counter Register (TRIG3_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG3_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG3_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG3_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG3_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG3_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG3_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG3_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG3_RESULT_7_6)
ETC_TRIG4 Control Register (TRIG4_CTRL)
ETC_TRIG4 Counter Register (TRIG4_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG4_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG4_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG4_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG4_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG4_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG4_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG4_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG4_RESULT_7_6)
ETC_TRIG5 Control Register (TRIG5_CTRL)
ETC_TRIG5 Counter Register (TRIG5_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG5_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG5_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG5_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG5_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG5_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG5_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG5_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG5_RESULT_7_6)
ETC_TRIG6 Control Register (TRIG6_CTRL)
ETC_TRIG6 Counter Register (TRIG6_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG6_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG6_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG6_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG6_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG6_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG6_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG6_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG6_RESULT_7_6)
ETC_TRIG7 Control Register (TRIG7_CTRL)
ETC_TRIG7 Counter Register (TRIG7_COUNTER)
ETC_TRIG Chain 0/1 Register (TRIG7_CHAIN_1_0)
ETC_TRIG Chain 2/3 Register (TRIG7_CHAIN_3_2)
ETC_TRIG Chain 4/5 Register (TRIG7_CHAIN_5_4)
ETC_TRIG Chain 6/7 Register (TRIG7_CHAIN_7_6)
ETC_TRIG Result Data 1/0 Register (TRIG7_RESULT_1_0)
ETC_TRIG Result Data 3/2 Register (TRIG7_RESULT_3_2)
ETC_TRIG Result Data 5/4 Register (TRIG7_RESULT_5_4)
ETC_TRIG Result Data 7/6 Register (TRIG7_RESULT_7_6)
Chapter 67: Touch Screen Controller (TSC)
Chip-specific TSC information
Overview
Features
Functional Description
Operating modes
Idle
Pre-charge
Detection
Measurement
Data valid check
Interrupt
Reset
Debug mode
Configuration
TSC configurations
TSC-ADC-TSC analogue configuration
TSC, TSC analogue and ADC connection
TSC and GPIO
ADC-TSC co-working
TSC Memory Map/Register Definition
TSC
TSC_BASIC_SETTING
TSC_PRE_CHARGE_TIME
TSC_FLOW_CONTROL
TSC_MEASEURE_VALUE
TSC_INT_EN
TSC_INT_SIG_EN
TSC_INT_STATUS
TSC_DEBUG_MODE
TSC_DEBUG_MODE2
Appendix A: Revision History
Appendix B: Change summary from rev0 to rev0.1
Change summary for this latest revision
i.MX RT1064 Processor Reference
Manual
Document Number: IMXRT1064RM
Rev. 0.1, 12/2018
2
NXP Semiconductors
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
Section number
Contents
Title
Chapter 1
Introduction
Page
1.1
1.2
1.3
1.4
1.5
About This Document...................................................................................................................................................21
Introduction...................................................................................................................................................................29
Features......................................................................................................................................................................... 31
Target Applications.......................................................................................................................................................33
Endianness Support.......................................................................................................................................................33
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................35
2.2
ARM Platform Memory Map....................................................................................................................................... 35
Interrupts, DMA Events, and XBAR Assignments
Chapter 3
Chip-specific Interrupt information.............................................................................................................................. 43
Overview.......................................................................................................................................................................43
CM7 interrupts..............................................................................................................................................................43
DMA Mux.....................................................................................................................................................................52
XBAR Resource Assignments......................................................................................................................................60
Direct Memory Access Multiplexer (DMAMUX)
Chapter 4
Chip-specific DMAMUX information......................................................................................................................... 73
Introduction...................................................................................................................................................................73
External signal description............................................................................................................................................75
Functional description...................................................................................................................................................75
Initialization/application information........................................................................................................................... 80
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
4.4
4.5
4.6 Memory map/register definition................................................................................................................................... 83
Enhanced Direct Memory Access (eDMA)
Chapter 5
NXP Semiconductors
3
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
Section number
Title
Page
5.1
5.2
Chip-specific eDMA information................................................................................................................................. 87
Introduction...................................................................................................................................................................87
5.3 Modes of operation....................................................................................................................................................... 91
5.4
5.5
Functional description...................................................................................................................................................91
Initialization/application information........................................................................................................................... 97
5.6 Memory map/register definition................................................................................................................................... 113
Chapter 6
System Security
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Chapter overview.......................................................................................................................................................... 173
Feature summary...........................................................................................................................................................173
High-Assurance Boot (HAB)........................................................................................................................................175
Secure Non-Volatile Storage (SNVS) module............................................................................................................. 178
Data Co-Processor (DCP)............................................................................................................................................. 179
Standalone True Random Number Generator (TRNG)................................................................................................ 180
OCOTP_CTRL............................................................................................................................................................. 180
Central Security Unit (CSU).........................................................................................................................................181
System JTAG Controller (SJC).................................................................................................................................... 181
6.10 Bus Encryption Engine (BEE)...................................................................................................................................... 182
Chapter 7
System Debug
7.1
7.2
Overview.......................................................................................................................................................................185
Chip and ARM Platform Debug Architecture.............................................................................................................. 185
7.3 Miscellaneous............................................................................................................................................................... 191
7.4
Supported tools............................................................................................................................................................. 191
Chapter 8
System Boot
8.1
8.2
8.3
8.4
4
Chip-specific Boot Information.................................................................................................................................... 193
Overview.......................................................................................................................................................................195
Boot modes................................................................................................................................................................... 196
Device configuration.....................................................................................................................................................201
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
NXP Semiconductors
Section number
Title
Page
8.5
8.6
8.7
8.8
8.9
Device initialization...................................................................................................................................................... 203
Boot devices (internal boot)..........................................................................................................................................209
Program image.............................................................................................................................................................. 239
Plugin image................................................................................................................................................................. 246
Serial Downloader........................................................................................................................................................ 247
8.10 Recovery devices.......................................................................................................................................................... 256
8.11
SD/MMC manufacture mode........................................................................................................................................257
8.12 High-Assurance Boot (HAB)........................................................................................................................................257
8.13 ROM APIs.................................................................................................................................................................... 259
Chapter 9
External Signals and Pin Multiplexing
9.1
Overview.......................................................................................................................................................................271
Chapter 10
IOMUX Controller (IOMUXC)
10.1 Overview.......................................................................................................................................................................299
10.2 Clocks........................................................................................................................................................................... 301
10.3
Functional description...................................................................................................................................................301
10.4
IOMUXC GPR Memory Map/Register Definition.......................................................................................................304
10.5
IOMUXC SNVS Memory Map/Register Definition.................................................................................................... 358
10.6
IOMUXC SNVS GPR Memory Map/Register Definition........................................................................................... 374
10.7
IOMUXC Memory Map/Register Definition............................................................................................................... 378
Chapter 11
General Purpose Input/Output (GPIO)
11.1 Chip-specific GPIO information...................................................................................................................................959
11.2 Overview.......................................................................................................................................................................959
11.3 Clocks........................................................................................................................................................................... 963
11.4 GPIO Functional Description....................................................................................................................................... 963
11.5 GPIO Register Descriptions..........................................................................................................................................969
Chapter 12
Clock and Power Management
NXP Semiconductors
5
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
Section number
Title
Page
12.1
Introduction...................................................................................................................................................................989
12.2 Device Power Management Architecture Components................................................................................................989
12.3 Clock Management....................................................................................................................................................... 992
12.4
Power management.......................................................................................................................................................1001
12.5 ONOFF (Button)...........................................................................................................................................................1014
12.6 WAKEUP Pin............................................................................................................................................................... 1016
Chapter 13
Clock Controller Module (CCM)
13.1 Chip-specific CCM information................................................................................................................................... 1017
13.2 Overview.......................................................................................................................................................................1017
13.3 External Signals............................................................................................................................................................ 1020
13.4 CCM Clock Tree...........................................................................................................................................................1020
13.5
System Clocks...............................................................................................................................................................1023
13.6
Functional Description..................................................................................................................................................1037
13.7 CCM Memory Map/Register Definition.......................................................................................................................1050
13.8 CCM Analog Memory Map/Register Definition..........................................................................................................1100
Chapter 14
Crystal Oscillator (XTALOSC)
14.1 Chip-specific XTALOSC information..........................................................................................................................1143
14.2 Overview.......................................................................................................................................................................1143
14.3 External Signals............................................................................................................................................................ 1144
14.4 Crystal Oscillator 24 MHz............................................................................................................................................ 1144
14.5 Crystal Oscillator 32 kHz..............................................................................................................................................1147
14.6 XTALOSC 24MHz Memory Map/Register Definition................................................................................................1148
Chapter 15
Power Management Unit (PMU)
15.1 Chip-specific PMU information................................................................................................................................... 1161
15.2 Overview.......................................................................................................................................................................1161
15.3 Digital LDO Regulators................................................................................................................................................1163
15.4 Analog LDO Regulators............................................................................................................................................... 1164
6
NXP Semiconductors
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
Section number
Title
Page
15.5 USB LDO Regulator.....................................................................................................................................................1165
15.6
SNVS Regulator............................................................................................................................................................1166
15.7
PMU Memory Map/Register Definition.......................................................................................................................1166
Chapter 16
General Power Controller (GPC)
16.1 Chip-specific GPC information.................................................................................................................................... 1191
16.2 Overview.......................................................................................................................................................................1191
16.3 Clocks........................................................................................................................................................................... 1192
16.4
Power Gating Control (PGC)........................................................................................................................................1192
16.5 GPC Interrupt Controller (INTC)................................................................................................................................. 1195
16.6 GPC Memory Map/Register Definition........................................................................................................................1196
16.7
PGC Memory Map/Register Definition........................................................................................................................1202
Chapter 17
DCDC Converter (DCDC)
17.1 Chip-specific DCDC information................................................................................................................................. 1209
17.2
Introduction...................................................................................................................................................................1209
17.3
Features......................................................................................................................................................................... 1209
17.4 Block diagram...............................................................................................................................................................1210
17.5
Functional description...................................................................................................................................................1210
17.6 Application information................................................................................................................................................1211
17.7 Memory Map and register definition............................................................................................................................ 1212
Chapter 18
Temperature Monitor (TEMPMON)
18.1 Chip-specific TEMPMON information........................................................................................................................ 1223
18.2 Overview.......................................................................................................................................................................1223
18.3
Software Usage Guidelines...........................................................................................................................................1225
18.4 TEMPMON Memory Map/Register Definition............................................................................................................1226
Chapter 19
Secure Non-Volatile Storage (SNVS)
19.1 Chip-specific SNVS information..................................................................................................................................1233
NXP Semiconductors
7
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
Section number
Title
Page
19.2
SNVS introduction........................................................................................................................................................1233
19.3
SNVS Structure.............................................................................................................................................................1235
19.4 Runtime Procedures...................................................................................................................................................... 1237
19.5 Reset and Initialization of SNVS..................................................................................................................................1240
19.6
SNVS register descriptions........................................................................................................................................... 1243
Chapter 20
System Reset Controller (SRC)
20.1 Chip-specific SRC information.....................................................................................................................................1273
20.2
SRC Overview.............................................................................................................................................................. 1273
20.3 External Signals............................................................................................................................................................ 1274
20.4 Clocks........................................................................................................................................................................... 1274
20.5 Top-level resets, power-up sequence and external supply integration......................................................................... 1275
20.6
Power-On Reset and power sequencing....................................................................................................................... 1280
20.7
Functional Description..................................................................................................................................................1281
20.8
SRC Memory Map/Register Definition........................................................................................................................1286
Chapter 21
Fusemap
21.1 Boot Fusemap............................................................................................................................................................... 1301
21.2 Lock Fusemap...............................................................................................................................................................1306
21.3
Fusemap Descriptions Table.........................................................................................................................................1307
Chapter 22
On-Chip OTP Controller (OCOTP_CTRL)
22.1 Chip-specific OCOTP_CTRL information...................................................................................................................1323
22.2 Overview.......................................................................................................................................................................1323
22.3 Clocks........................................................................................................................................................................... 1324
22.4 Top-Level Symbol and Functional Overview...............................................................................................................1325
22.5
Fuse Map.......................................................................................................................................................................1331
22.6 OCOTP Memory Map/Register Definition.................................................................................................................. 1331
Chapter 23
External Memory Controllers
8
NXP Semiconductors
i.MX RT1064 Processor Reference Manual, Rev. 0.1, 12/2018
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
