Cover
Overview
Table of Contents
List of Tables
List of Figures
1 Signal Description
1.1 Pin Description
1.1.1 88E1510/88E1518 48-Pin QFN Package Pinout
1.1.2 88E1512 56-Pin QFN Package Pinout
1.1.3 88E1514 56-Pin QFN Package Pinout
1.2 Pin Assignment List
1.2.1 88E1510 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.2 88E1518 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.3 88E1512 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.4 88E1514 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name
2 PHY Functional Specifications
2.1 Modes of Operation and Major Interfaces
2.2 Copper Media Interface
2.2.1 Transmit Side Network Interface
2.2.2 Encoder
2.2.3 Receive Side Network Interface
2.2.4 Decoder
2.3 1.25 GHz SERDES Interface
2.3.1 Electrical Interface
2.4 MAC Interfaces
2.4.1 SGMII Interface
2.4.2 RGMII Interface
2.4.3 10/100 Mbps Functionality
2.4.4 TX_ER and RX_ER Coding
2.5 Loopback
2.5.1 System Interface Loopback
2.5.2 Synchronous SERDES Loopback
2.5.3 Line Loopback
2.5.4 External Loopback
2.6 Fiber/Copper Auto-Selection
2.6.1 Preferred Media
2.6.2 Definition of link in SGMII Media Interface in the context of auto media selection
2.6.3 Notes on Determining which Media Linked Up
2.7 Synchronizing FIFO
2.8 Resets
2.9 Power Management
2.9.1 Low Power Modes
2.9.2 RGMII/SGMII MAC Interface Power Down
2.10 Auto-Negotiation
2.10.1 10/100/1000BASE-T Auto-Negotiation
2.10.2 1000BASE-X Auto-Negotiation
2.10.3 SGMII Auto-Negotiation
2.11 Downshift Feature
2.12 Fast 1000BASE-T Link Down Indication
2.13 Advanced Virtual Cable Tester®
2.13.1 Maximum Peak
2.13.2 First Peak
2.13.3 Offset
2.13.4 Sample Point
2.13.5 Pulse Amplitude and Pulse Width
2.13.6 Drop Link
2.13.7 VCT™ with Link Up
2.13.8 Alternate VCT Control
2.14 Data Terminal Equipment (DTE) Detect
2.15 Energy Efficient Ethernet (EEE)
2.15.1 Energy Efficient Ethernet Low Power Modes
2.15.2 Energy Efficient Ethernet (EEE) Buffering for Master mode
2.15.3 Energy Efficient Ethernet Auto-Negotiation
2.16 CRC Error Counter and Frame Counter
2.16.1 Enabling The CRC Error Counter and Packet Counter
2.17 Packet Generator
2.18 RX_ER Byte Capture
2.19 1.25G PRBS Generator and Checker
2.20 MDI/MDIX Crossover
2.21 Unidirectional Transmit
2.22 Polarity Correction
2.23 FLP Exchange Complete with No Link
2.24 Duplex Mismatch Indicator
2.25 Link Disconnect Counter
2.26 LED
2.26.1 LED Polarity
2.26.2 Pulse Stretching and Blinking
2.26.3 Bi-Color LED Mixing
2.26.4 Modes of Operation
2.27 CLK125
2.27.1 Synchronous Ethernet Recovered Clock
2.28 Precise Timing Protocol (PTP) Time Stamping Support
2.28.1 PTP Control
2.28.2 Packet Time Stamping
2.28.3 Time Application Interface (TAI)
2.28.4 ReadPlus Command
2.29 Interrupt
2.30 Automatic and Manual Impedance Calibration
2.30.1 MAC Interface Calibration Circuit
2.30.2 MAC Interface Calibration Register Definitions
2.30.3 Changing Auto Calibration Targets
2.30.4 Manual Settings to The Calibration Registers
2.31 Configuring the 88E1510/88E1518/88E1512/88E1514 Device
2.31.1 Hardware Configuration
2.31.2 Software Configuration - Management Interface
2.32 Jumbo Packet Support
2.33 Temperature Sensor
2.34 Regulators and Power Supplies
2.34.1 AVDD18
2.34.2 AVDDC18
2.34.3 AVDD33
2.34.4 DVDD
2.34.5 REG_IN
2.34.6 AVDD18_OUT
2.34.7 DVDD_OUT
2.34.8 VDDO
2.34.9 Power Supply Sequencing
2.35 Wake on Lan (WOL) Event Detection
2.35.1 Wake Up Frame Event
2.35.2 Magic Packet Event
2.35.3 Link Change Event
3 88E1510/88E1518/88E1512/88E1514 Register Description
3.1 PHY MDIO Register Description
3.2 PHY XMDIO Register Description
4 Electrical Specifications
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 Package Thermal Information
4.3.1 Thermal Conditions for 88E1510/88E1518 48-pin, QFN Package
4.3.2 Thermal Conditions for 88E1512/88E1514 56-pin, QFN Package
4.4 88E1510/88E1518 Current Consumption
4.4.1 Current Consumption AVDD18 + AVDDC18
4.4.2 Current Consumption AVDD33
4.4.3 Current Consumption DVDD
4.4.4 Current Consumption VDDO
4.5 88E1512 Current Consumption
4.5.1 Current Consumption AVDD18 + AVDDC18
4.5.2 Current Consumption AVDD33
4.5.3 Current Consumption DVDD
4.5.4 Current Consumption VDDO
4.6 DC Operating Conditions
4.6.1 Digital Pins
4.6.2 IEEE DC Transceiver Parameters
4.7 AC Electrical Specifications
4.7.1 Reset Timing
4.7.2 XTAL_IN/XTAL_OUT Timing
4.7.3 SyncE Recovered Clock Output Timing
4.7.4 LED to CONFIG Timing
4.8 SGMII Interface Timing
4.8.1 SGMII Output AC Characteristics
4.8.2 SGMII Input AC Characteristics
4.9 PTP Interface Timing
4.9.1 PTP Clock Input Timing
4.9.2 PTP Event Request Input AC Timing (LED[1])
4.9.3 PTP Trigger Generate Output AC Timing (LED[1])
4.10 RGMII Interface Timing
4.10.1 RGMII AC Characteristics
4.10.2 RGMII Delay Timing for different RGMII Modes
4.11 MDC/MDIO Timing
4.12 IEEE AC Transceiver Parameters
4.13 CLK125
4.14 Latency Timing
4.14.1 RGMII to 1000BASE-T Transmit Latency Timing
4.14.2 RGMII to 100BASE-TX Transmit Latency Timing
4.14.3 RGMII to 10BASE-T Transmit Latency Timing
4.14.4 1000BASE-T to RGMII Receive Latency Timing
4.14.5 100BASE-TX to RGMII Receive Latency Timing
4.14.6 10BASE-T to RGMII Receive Latency Timing
4.14.7 10/100/1000BASE-T to SGMII Latency Timing
4.14.8 SGMII to 10/100/1000BASE-T Latency Timing
5 Package Mechanical Dimensions
5.1 48-Pin QFN Package
5.2 56-Pin QFN Package
6 Order Information
6.1 Ordering Part Numbers and Package Markings
6.1.1 Package Marking Examples
6.1.2 Package Marking Samples
Back Cover