Table 1. Device summary
1 Introduction
2 Description
2.1 Device overview
Table 2. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B device features and peripheral counts
2.2 Ultra-low-power device continuum
2.2.1 Performance
2.2.2 Shared peripherals
2.2.3 Common system strategy
2.2.4 Features
3 Functional overview
Figure 1. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B block diagram
3.1 Low power modes
Table 3. Functionalities depending on the operating power supply range
Table 4. CPU frequency range depending on dynamic voltage scaling
Table 5. Working mode-dependent functionalities (from Run/active down to standby)
3.2 ARM® Cortex®-M3 core with MPU
3.3 Reset and supply management
3.3.1 Power supply schemes
3.3.2 Power supply supervisor
3.3.3 Voltage regulator
3.3.4 Boot modes
3.4 Clock management
Figure 2. Clock tree
3.5 Low power real-time clock and backup registers
3.6 GPIOs (general-purpose inputs/outputs)
3.7 Memories
3.8 DMA (direct memory access)
3.9 LCD (liquid crystal display)
3.10 ADC (analog-to-digital converter)
3.10.1 Temperature sensor
3.10.2 Internal voltage reference (VREFINT)
3.11 DAC (digital-to-analog converter)
3.12 Ultra-low-power comparators and reference voltage
3.13 Routing interface
3.14 Touch sensing
3.15 Timers and watchdogs
Table 6. Timer feature comparison
3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)
3.15.2 Basic timers (TIM6 and TIM7)
3.15.3 SysTick timer
3.15.4 Independent watchdog (IWDG)
3.15.5 Window watchdog (WWDG)
3.16 Communication interfaces
3.16.1 I²C bus
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART)
3.16.3 Serial peripheral interface (SPI)
3.16.4 Universal serial bus (USB)
3.17 CRC (cyclic redundancy check) calculation unit
3.18 Development support
4 Pin descriptions
Figure 3. STM32L15xVx UFBGA100 ballout
Figure 4. STM32L15xVx LQFP100 pinout
Figure 5. STM32L15xRx TFBGA64 ballout
Figure 6. STM32L15xRx LQFP64 pinout
Figure 7. STM32L15xCx LQFP48 pinout
Figure 8. STM32L15xCx UFQFPN48 pinout
Table 7. Legend/abbreviations used in the pinout table
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions
Table 9. Alternate function input/output
5 Memory mapping
Figure 9. Memory map
6 Electrical characteristics
6.1 Parameter conditions
6.1.1 Minimum and maximum values
6.1.2 Typical values
6.1.3 Typical curves
6.1.4 Loading capacitor
6.1.5 Pin input voltage
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
6.1.6 Power supply scheme
Figure 12. Power supply scheme
6.1.7 Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
6.1.8 Current consumption measurement
Figure 14. Current consumption measurement scheme
6.2 Absolute maximum ratings
Table 10. Voltage characteristics
Table 11. Current characteristics
Table 12. Thermal characteristics
6.3 Operating conditions
6.3.1 General operating conditions
Table 13. General operating conditions
6.3.2 Embedded reset and power control block characteristics
Table 14. Embedded reset and power control block characteristics
6.3.3 Embedded internal reference voltage
Table 15. Embedded internal reference voltage calibration values
Table 16. Embedded internal reference voltage
6.3.4 Supply current characteristics
Table 17. Current consumption in Run mode, code with data processing running from Flash
Table 18. Current consumption in Run mode, code with data processing running from RAM
Table 19. Current consumption in Sleep mode
Table 20. Current consumption in Low power run mode
Table 21. Current consumption in Low power sleep mode
Table 22. Typical and maximum current consumptions in Stop mode
Table 23. Typical and maximum current consumptions in Standby mode
Table 24. Peripheral current consumption
6.3.5 Wakeup time from Low power mode
Table 25. Low-power mode wakeup timings
6.3.6 External clock source characteristics
Table 26. High-speed external user clock characteristics
Figure 15. High-speed external clock source AC timing diagram
Table 27. Low-speed external user clock characteristics
Figure 16. Low-speed external clock source AC timing diagram
Table 28. HSE oscillator characteristics
Figure 17. HSE oscillator circuit diagram
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)
Figure 18. Typical application with a 32.768 kHz crystal
6.3.7 Internal clock source characteristics
Table 30. HSI oscillator characteristics
Table 31. LSI oscillator characteristics
Table 32. MSI oscillator characteristics
6.3.8 PLL characteristics
Table 33. PLL characteristics
6.3.9 Memory characteristics
Table 34. RAM and hardware registers
Table 35. Flash memory and data EEPROM characteristics
Table 36. Flash memory, data EEPROM endurance and data retention
6.3.10 EMC characteristics
Table 37. EMS characteristics
Table 38. EMI characteristics
6.3.11 Electrical sensitivity characteristics
Table 39. ESD absolute maximum ratings
Table 40. Electrical sensitivities
6.3.12 I/O current injection characteristics
Table 41. I/O current injection susceptibility
6.3.13 I/O port characteristics
Table 42. I/O static characteristics
Table 43. Output voltage characteristics
Table 44. I/O AC characteristics
Figure 19. I/O AC characteristics definition
6.3.14 NRST pin characteristics
Table 45. NRST pin characteristics
Figure 20. Recommended NRST pin protection
6.3.15 TIM timer characteristics
Table 46. TIMx characteristics
6.3.16 Communication interfaces
Table 47. I2C characteristics
Figure 21. I2C bus AC waveforms and measurement circuit
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)
Table 49. SPI characteristics
Figure 22. SPI timing diagram - slave mode and CPHA = 0
Figure 23. SPI timing diagram - slave mode and CPHA = 1(1)
Figure 24. SPI timing diagram - master mode(1)
Table 50. USB startup time
Table 51. USB DC electrical characteristics
Figure 25. USB timings: definition of data signal rise and fall time
Table 52. USB: full speed electrical characteristics
6.3.17 12-bit ADC characteristics
Table 53. ADC clock frequency
Table 54. ADC characteristics
Table 55. ADC accuracy
Figure 26. ADC accuracy characteristics
Figure 27. Typical connection diagram using the ADC
Figure 28. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion
Table 56. Maximum source impedance RAIN max
Figure 29. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 30. Power supply and reference decoupling (VREF+ connected to VDDA)
6.3.18 DAC electrical specifications
Table 57. DAC characteristics
Figure 31. 12-bit buffered /non-buffered DAC
6.3.19 Temperature sensor characteristics
Table 58. Temperature sensor calibration values
Table 59. Temperature sensor characteristics
6.3.20 Comparator
Table 60. Comparator 1 characteristics
Table 61. Comparator 2 characteristics
6.3.21 LCD controller (STM32L152xx only)
Table 62. LCD controller characteristics
7 Package characteristics
7.1 Package mechanical data
Figure 32. LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline
Table 63. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
Figure 33. LQFP100 recommended footprint
Figure 34. LQFP100 marking example (package top view)
Figure 35. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline
Table 64. LQFP64 10 x 10 mm 64-pin low-profile quad flat package mechanical data
Figure 36. LQFP64 recommended footprint
Figure 37. LQFP64 marking example (package top view)
Figure 38. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline
Table 65. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Figure 39. LQFP48 recommended footprint
Figure 40. LQFP48 marking example (package top view)
Figure 41. UFQFPN48 7 x 7 mm 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package outline
Table 66. UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data
Figure 42. UFQFPN48 recommended footprint
Figure 43. UFQFPN48 marking example (package top view)
Figure 44. UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package outline
Table 67. UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data
Figure 45. UFBGA100 marking example (package top view)
Figure 46. TFBGA64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline
Table 68. TFBGA64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data
Figure 47. TFBGA64 marking example (package top view)
Figure 48. Recommended PCB design rules for pads (0.5 mm pitch BGA)
7.2 Thermal characteristics
Table 69. Thermal characteristics
Figure 49. Thermal resistance
7.2.1 Reference document
8 Part numbering
Table 70. Ordering information scheme
9 Revision history
Table 71. Document revision history