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Arm®v8-M Architecture Reference Manual.pdf
ARMv8-M Architecture Reference Manual
Contents
Preface
About this book
Using this book
Part A, ARMv8-M Architecture Introduction and Overview
Part B, ARMv8-M Architecture Rules
Part C, ARMv8-M Instructions
Part D, ARMv8-M Registers
Part E, ARMv8-M Pseudocode
Part F, Packet Protocols
Conventions
Typographic conventions
Signals
Numbers
Pseudocode descriptions
Assembler syntax descriptions
Additional reading
ARM publications
Other publications
Feedback
Feedback on this book
Part A: ARMv8-M Architecture Introduction and Overview
A1: Introduction
A1.1 Document layout and terminology
A1.1.1 Structure of the document
A1.1.2 Scope of the document
A1.1.3 Intended audience
A1.1.4 Terminology, phrases
A1.1.5 Terminology, ARMv8-M specific terms
A1.2 About the ARMv8 architecture, and architecture profiles
A1.3 The ARMv8-M architecture profile
A1.3.1 Security Extension
A1.3.2 MPU model
A1.3.3 Nested Vector Interrupt Controller
A1.3.4 Stack pointers
A1.3.5 The ARMv8-M instruction set
A1.3.6 Debug
A1.4 ARMv8-M variants
Part B: ARMv8-M Architecture Rules
B1: Resets
B1.1 Resets, Cold reset, and Warm reset
B2: Power Management
B2.1 Power management
B2.1.1 The Wait for Event (WFE) instruction
B2.1.2 The Event register
B2.1.3 The Wait for Interrupt (WFI) instruction
B2.1.4 Sleep on exit
B3: Programmers’ Model
B3.1 PE modes, Thread mode and Handler mode
B3.2 Privileged and unprivileged execution
B3.3 Registers
B3.4 XPSR, APSR, IPSR, and EPSR
B3.4.1 Application Program Status Register (APSR)
B3.4.2 Interrupt Program Status Register (IPSR)
B3.4.3 Execution Program Status Register (EPSR)
B3.5 Security states, Secure state, and Non-secure state
B3.6 Security states, register banking between them
B3.7 Stack pointer
B3.8 Exception numbers and exception priority numbers
B3.9 Exception enable, pending, and active bits
B3.10 Security states, exception banking
B3.11 Faults
B3.12 Priority model
B3.13 Secure address protection
B3.14 Security state transitions
B3.15 Function calls from Secure state to Non-secure state
B3.16 Function returns from Non-secure state
B3.17 Exception handling
B3.18 Exception entry, context stacking
B3.19 Exception entry, register clearing after context stacking
B3.20 Stack limit checks
B3.21 Exception return
B3.22 Integrity signature
B3.23 Exceptions during exception entry
B3.24 Exceptions during exception return
B3.25 Tail-chaining
B3.26 Exceptions, instruction resume, or instruction restart
B3.27 Vector tables
B3.28 Hardware-controlled priority escalation to HardFault
B3.29 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK, for software-controlled priority boosting
B3.30 Lockup
B3.30.1 Instruction-related lockup behavior
B3.30.2 Exception-related lockup behavior
B3.31 Exception during a singleword load operation
B3.32 Special-purpose CONTROL register
B3.33 Saving context on process switch
B3.34 Context Synchronization Event
B3.35 Coprocessor support
B4: Floating-point Support
B4.1 The optional Floating-point Extension, FPv5
B4.2 About the Floating-point Status and Control Register (FPSCR)
B4.3 Registers for floating-point data processing, S0-S31, or D0-D15
B4.4 Floating-point standards and terminology
B4.5 Floating-point data representable
B4.6 Floating-point encoding formats, half-precision, single-precision, and double-precision
B4.7 The IEEE 754 floating-point exceptions
B4.8 The Flush-to-zero mode
B4.9 The Default NaN mode, and NaN handling
B4.10 The Default NaN
B4.11 Combinations of floating-point exceptions
B4.12 Priority of floating-point exceptions relative to other floating-point exceptions
B5: Memory Model
B5.1 Memory accesses
B5.2 Address space
B5.3 Endianness
B5.4 Alignment behavior
B5.5 Atomicity
B5.5.1 Single-copy atomicity
B5.5.2 Multi-copy atomicity
B5.6 Concurrent modification and execution of instructions
B5.7 Access rights
B5.8 Observability of memory accesses
B5.9 Completion of memory accesses
B5.10 Ordering requirements for memory accesses
B5.11 Ordering of implicit memory accesses
B5.12 Ordering of explicit memory accesses
B5.13 Memory barriers
B5.13.1 Instruction Synchronization Barrier
B5.13.2 Data Memory Barrier
B5.13.3 Data Synchronization Barrier
B5.13.4 Synchronization requirements for System Control Space
B5.14 Normal memory
B5.15 Cacheability attributes
B5.16 Device memory
B5.17 Device memory attributes
B5.17.1 Gathering and non-Gathering Device memory attributes
B5.17.2 Reordering and non-Reordering Device memory attributes
B5.17.3 Early Write Acknowledgement and no Early Write Acknowledgement Device memory attributes
B5.18 Shareability domains
B5.19 Shareability attributes
B5.20 Memory access restrictions
B5.21 Mismatched memory attributes
B5.22 Load-Exclusive and Store-Exclusive accesses to Normal memory
B5.23 Load-Acquire and Store-Release accesses to memory
B5.24 Caches
B5.25 Cache identification
B5.26 Cache visibility
B5.27 Cache coherency
B5.28 Cache enabling and disabling
B5.29 Cache behavior at reset
B5.30 Behavior of Preload Data (PLD) and Preload Instruction (PLI) instructions with caches
B5.31 Branch predictors
B5.32 Cache maintenance operations
B5.33 Ordering of cache maintenance operations
B5.34 Branch predictor maintenance operations
B6: The System Address Map
B6.1 System address map
B6.2 The System region of the system address map
B6.3 The System Control Space (SCS)
B7: Synchronization and Semaphores
B7.1 Exclusive access instructions
B7.2 The local monitors
B7.3 The global monitor
B7.3.1 Load-Exclusive and Store-Exclusive
B7.3.2 Load-Exclusive and Store-Exclusive in Shareable memory
B7.4 Exclusive access instructions and the monitors
B7.5 Load-Exclusive and Store-Exclusive instruction constraints
B8: The ARMv8-M Protected Memory System Architecture
B8.1 Memory Protection Unit
B8.2 Security attribution
B8.3 Security attribution unit (SAU)
B8.4 IMPLEMENTATION DEFINED Attribution Unit (IDAU)
B9: The System Timer, SysTick
B9.1 The system timer, SysTick
B10: Nested Vectored Interrupt Controller
B10.1 NVIC definition
B10.2 NVIC operation
B11: Debug
B11.1 About debug
B11.1.1 Debug feature overview
B11.1.2 Debug mechanisms
B11.1.3 Debug resources
B11.1.4 Trace
B11.1.5 Levels of debug
B11.2 Accessing debug features
B11.2.1 ROM table
B11.2.2 Debug System registers
B11.2.3 CoreSight and identification registers
B11.3 Debug authentication interface
B11.3.1 Halting debug authentication
B11.3.2 DebugMonitor authentication
B11.3.3 Non-invasive debug authentication
B11.3.4 DAP access permissions
B11.4 Debug event behavior
B11.4.1 About debug events
B11.4.2 Debug stepping
B11.4.3 Vector catch
B11.4.4 Breakpoint instructions
B11.4.5 External debug request
B11.5 Exiting Debug state
B11.6 Multiprocessor support
B11.6.1 Cross-halt event
B11.6.2 External restart request
B12: Debug and Trace Components
B12.1 Instrumentation Trace Macrocell
B12.1.1 About the ITM
B12.1.2 ITM operation
B12.1.3 Timestamp support
B12.1.4 Synchronization support
B12.1.5 Continuation bits
B12.2 Data Watchpoint and Trace unit
B12.2.1 About the DWT
B12.2.2 DWT unit operation
B12.2.3 Constraints on programming DWT comparators
B12.2.4 CMPMATCH trigger events
B12.2.5 Matching in detail
B12.2.6 DWT match restrictions and relaxations
B12.2.7 DWT trace restrictions and relaxations
B12.2.8 CYCCNT cycle counter and related timers
B12.2.9 Profiling counter support
B12.2.10 Program Counter sampling support
B12.3 Embedded Trace Macrocell
B12.4 Trace Port Interface Unit
B12.5 Flash Patch and Breakpoint unit
B12.5.1 About the FPB unit
B12.5.2 FPB unit operation
Part C: ARMv8-M Instruction Set
C1: Instruction Set Overview
C1.1 Instruction set
C1.2 Format of instruction descriptions
C1.2.1 The title
C1.2.2 A short description
C1.2.3 The instruction encoding or encodings
C1.2.4 Any alias conditions, if applicable
C1.2.5 A list of the assembler symbols for the instruction
C1.2.6 Pseudocode describing how the instruction operates
C1.2.7 Exceptions
C1.2.8 Notes
C1.3 Pseudocode for instruction descriptions
C1.3.1 Instruction encoding diagrams and instruction pseudocode
C1.3.2 Pseudocode descriptions of operations on general-purpose registers and PC
C1.3.3 Limitations of the instruction pseudocode
C1.4 Unified Assembler Language
C1.4.1 Conditional instructions
C1.4.2 Use of labels in UAL instruction syntax
C1.4.3 Using syntax information
C1.5 Standard assembler syntax fields
C1.6 Conditional execution
C1.6.1 Pseudocode details of conditional execution
C1.6.2 Conditional execution of undefined instructions
C1.6.3 Interaction of undefined instruction behavior with unpredictable or constrained unpredictable instruction behavior
C1.6.4 ITSTATE
C1.6.5 Branching into and out of an IT block
C1.7 Instruction set encoding information
C1.7.1 UNDEFINED and UNPREDICTABLE instruction set space
C1.7.2 Use of 0b1111 as a register specifier
C1.7.3 Use of 0b1101 as a register specifier
C1.7.4 Branching
C1.8 Modified immediate constants
C1.8.1 Operation of modified immediate constants
C1.9 NOP-compatible hint instructions
C1.10 Instruction set, interworking support
C1.11 Instruction set, interstating support
C1.12 SBZ or SBO fields in instructions
C2: Instruction Specification
C2.1 Top level T32 instruction set encoding
C2.2 16-bit T32 instruction encoding
C2.2.1 Shift (immediate), add, subtract, move, and compare
C2.2.2 Data-processing (two low registers)
C2.2.3 Special data instructions and branch and exchange
C2.2.4 Load/store (register offset)
C2.2.5 Load/store word/byte (immediate offset)
C2.2.6 Load/store halfword (immediate offset)
C2.2.7 Load/store (SP-relative)
C2.2.8 Add PC/SP (immediate)
C2.2.9 Miscellaneous 16-bit instructions
C2.2.10 Load/store multiple
C2.2.11 Conditional branch, and Supervisor Call
C2.3 32-bit T32 instruction encoding
C2.3.1 Load/store (multiple, dual, exclusive, acquire-release), table branch
C2.3.2 Data-processing (shifted register)
C2.3.3 Data-processing (modified immediate)
C2.3.4 Data-processing (plain binary immediate)
C2.3.5 Branches and miscellaneous control
C2.3.6 Load/store single
C2.3.7 Data-processing (register)
C2.3.8 Multiply, multiply accumulate, and absolute difference
C2.3.9 Long multiply and divide
C2.3.10 Coprocessor and floating-point instructions
C2.4 Alphabetical list of instructions
C2.4.1 ADC (immediate)
C2.4.2 ADC (register)
C2.4.3 ADD (SP plus immediate)
C2.4.4 ADD (SP plus register)
C2.4.5 ADD (immediate)
C2.4.6 ADD (immediate, to PC)
C2.4.7 ADD (register)
C2.4.8 ADR
C2.4.9 AND (immediate)
C2.4.10 AND (register)
C2.4.11 ASR (immediate)
C2.4.12 ASR (register)
C2.4.13 ASRS (immediate)
C2.4.14 ASRS (register)
C2.4.15 B
C2.4.16 BFC
C2.4.17 BFI
C2.4.18 BIC (immediate)
C2.4.19 BIC (register)
C2.4.20 BKPT
C2.4.21 BL
C2.4.22 BLX, BLXNS
C2.4.23 BX, BXNS
C2.4.24 CBNZ, CBZ
C2.4.25 CDP, CDP2
C2.4.26 CLREX
C2.4.27 CLZ
C2.4.28 CMN (immediate)
C2.4.29 CMN (register)
C2.4.30 CMP (immediate)
C2.4.31 CMP (register)
C2.4.32 CPS
C2.4.33 DBG
C2.4.34 DMB
C2.4.35 DSB
C2.4.36 EOR (immediate)
C2.4.37 EOR (register)
C2.4.38 FLDMDBX, FLDMIAX
C2.4.39 FSTMDBX, FSTMIAX
C2.4.40 ISB
C2.4.41 IT
C2.4.42 LDA
C2.4.43 LDAB
C2.4.44 LDAEX
C2.4.45 LDAEXB
C2.4.46 LDAEXH
C2.4.47 LDAH
C2.4.48 LDC, LDC2 (immediate)
C2.4.49 LDC, LDC2 (literal)
C2.4.50 LDM, LDMIA, LDMFD
C2.4.51 LDMDB, LDMEA
C2.4.52 LDR (immediate)
C2.4.53 LDR (literal)
C2.4.54 LDR (register)
C2.4.55 LDRB (immediate)
C2.4.56 LDRB (literal)
C2.4.57 LDRB (register)
C2.4.58 LDRBT
C2.4.59 LDRD (immediate)
C2.4.60 LDRD (literal)
C2.4.61 LDREX
C2.4.62 LDREXB
C2.4.63 LDREXH
C2.4.64 LDRH (immediate)
C2.4.65 LDRH (literal)
C2.4.66 LDRH (register)
C2.4.67 LDRHT
C2.4.68 LDRSB (immediate)
C2.4.69 LDRSB (literal)
C2.4.70 LDRSB (register)
C2.4.71 LDRSBT
C2.4.72 LDRSH (immediate)
C2.4.73 LDRSH (literal)
C2.4.74 LDRSH (register)
C2.4.75 LDRSHT
C2.4.76 LDRT
C2.4.77 LSL (immediate)
C2.4.78 LSL (register)
C2.4.79 LSLS (immediate)
C2.4.80 LSLS (register)
C2.4.81 LSR (immediate)
C2.4.82 LSR (register)
C2.4.83 LSRS (immediate)
C2.4.84 LSRS (register)
C2.4.85 MCR, MCR2
C2.4.86 MCRR, MCRR2
C2.4.87 MLA
C2.4.88 MLS
C2.4.89 MOV (immediate)
C2.4.90 MOV (register)
C2.4.91 MOV, MOVS (register-shifted register)
C2.4.92 MOVT
C2.4.93 MRC, MRC2
C2.4.94 MRRC, MRRC2
C2.4.95 MRS
C2.4.96 MSR (register)
C2.4.97 MUL
C2.4.98 MVN (immediate)
C2.4.99 MVN (register)
C2.4.100 NOP
C2.4.101 ORN (immediate)
C2.4.102 ORN (register)
C2.4.103 ORR (immediate)
C2.4.104 ORR (register)
C2.4.105 PKHBT, PKHTB
C2.4.106 PLD (literal)
C2.4.107 PLD (register)
C2.4.108 PLD, PLDW (immediate)
C2.4.109 PLI (immediate, literal)
C2.4.110 PLI (register)
C2.4.111 POP (multiple registers)
C2.4.112 POP (single register)
C2.4.113 PUSH (multiple registers)
C2.4.114 PUSH (single register)
C2.4.115 QADD
C2.4.116 QADD16
C2.4.117 QADD8
C2.4.118 QASX
C2.4.119 QDADD
C2.4.120 QDSUB
C2.4.121 QSAX
C2.4.122 QSUB
C2.4.123 QSUB16
C2.4.124 QSUB8
C2.4.125 RBIT
C2.4.126 REV
C2.4.127 REV16
C2.4.128 REVSH
C2.4.129 ROR (immediate)
C2.4.130 ROR (register)
C2.4.131 RORS (immediate)
C2.4.132 RORS (register)
C2.4.133 RRX
C2.4.134 RRXS
C2.4.135 RSB (immediate)
C2.4.136 RSB (register)
C2.4.137 SADD16
C2.4.138 SADD8
C2.4.139 SASX
C2.4.140 SBC (immediate)
C2.4.141 SBC (register)
C2.4.142 SBFX
C2.4.143 SDIV
C2.4.144 SEL
C2.4.145 SEV
C2.4.146 SG
C2.4.147 SHADD16
C2.4.148 SHADD8
C2.4.149 SHASX
C2.4.150 SHSAX
C2.4.151 SHSUB16
C2.4.152 SHSUB8
C2.4.153 SMLABB, SMLABT, SMLATB, SMLATT
C2.4.154 SMLAD, SMLADX
C2.4.155 SMLAL
C2.4.156 SMLALBB, SMLALBT, SMLALTB, SMLALTT
C2.4.157 SMLALD, SMLALDX
C2.4.158 SMLAWB, SMLAWT
C2.4.159 SMLSD, SMLSDX
C2.4.160 SMLSLD, SMLSLDX
C2.4.161 SMMLA, SMMLAR
C2.4.162 SMMLS, SMMLSR
C2.4.163 SMMUL, SMMULR
C2.4.164 SMUAD, SMUADX
C2.4.165 SMULBB, SMULBT, SMULTB, SMULTT
C2.4.166 SMULL
C2.4.167 SMULWB, SMULWT
C2.4.168 SMUSD, SMUSDX
C2.4.169 SSAT
C2.4.170 SSAT16
C2.4.171 SSAX
C2.4.172 SSUB16
C2.4.173 SSUB8
C2.4.174 STC, STC2
C2.4.175 STL
C2.4.176 STLB
C2.4.177 STLEX
C2.4.178 STLEXB
C2.4.179 STLEXH
C2.4.180 STLH
C2.4.181 STM, STMIA, STMEA
C2.4.182 STMDB, STMFD
C2.4.183 STR (immediate)
C2.4.184 STR (register)
C2.4.185 STRB (immediate)
C2.4.186 STRB (register)
C2.4.187 STRBT
C2.4.188 STRD (immediate)
C2.4.189 STREX
C2.4.190 STREXB
C2.4.191 STREXH
C2.4.192 STRH (immediate)
C2.4.193 STRH (register)
C2.4.194 STRHT
C2.4.195 STRT
C2.4.196 SUB (SP minus immediate)
C2.4.197 SUB (SP minus register)
C2.4.198 SUB (immediate)
C2.4.199 SUB (immediate, from PC)
C2.4.200 SUB (register)
C2.4.201 SVC
C2.4.202 SXTAB
C2.4.203 SXTAB16
C2.4.204 SXTAH
C2.4.205 SXTB
C2.4.206 SXTB16
C2.4.207 SXTH
C2.4.208 TBB, TBH
C2.4.209 TEQ (immediate)
C2.4.210 TEQ (register)
C2.4.211 TST (immediate)
C2.4.212 TST (register)
C2.4.213 TT, TTT, TTA, TTAT
C2.4.214 UADD16
C2.4.215 UADD8
C2.4.216 UASX
C2.4.217 UBFX
C2.4.218 UDF
C2.4.219 UDIV
C2.4.220 UHADD16
C2.4.221 UHADD8
C2.4.222 UHASX
C2.4.223 UHSAX
C2.4.224 UHSUB16
C2.4.225 UHSUB8
C2.4.226 UMAAL
C2.4.227 UMLAL
C2.4.228 UMULL
C2.4.229 UQADD16
C2.4.230 UQADD8
C2.4.231 UQASX
C2.4.232 UQSAX
C2.4.233 UQSUB16
C2.4.234 UQSUB8
C2.4.235 USAD8
C2.4.236 USADA8
C2.4.237 USAT
C2.4.238 USAT16
C2.4.239 USAX
C2.4.240 USUB16
C2.4.241 USUB8
C2.4.242 UXTAB
C2.4.243 UXTAB16
C2.4.244 UXTAH
C2.4.245 UXTB
C2.4.246 UXTB16
C2.4.247 UXTH
C2.4.248 VABS
C2.4.249 VADD
C2.4.250 VCMP
C2.4.251 VCMPE
C2.4.252 VCVT (between double-precision and single-precision)
C2.4.253 VCVT (between floating-point and fixed-point)
C2.4.254 VCVT (floating-point to integer)
C2.4.255 VCVT (integer to floating-point)
C2.4.256 VCVTA
C2.4.257 VCVTB
C2.4.258 VCVTM
C2.4.259 VCVTN
C2.4.260 VCVTP
C2.4.261 VCVTR
C2.4.262 VCVTT
C2.4.263 VDIV
C2.4.264 VFMA
C2.4.265 VFMS
C2.4.266 VFNMA
C2.4.267 VFNMS
C2.4.268 VLDM
C2.4.269 VLDR
C2.4.270 VLLDM
C2.4.271 VLSTM
C2.4.272 VMAXNM
C2.4.273 VMINNM
C2.4.274 VMLA
C2.4.275 VMLS
C2.4.276 VMOV (between general-purpose register and single-precision register)
C2.4.277 VMOV (between two general-purpose registers and a doubleword register)
C2.4.278 VMOV (between two general-purpose registers and two single-precision registers)
C2.4.279 VMOV (half of doubleword register to single general-purpose register)
C2.4.280 VMOV (immediate)
C2.4.281 VMOV (register)
C2.4.282 VMOV (single general-purpose register to half of doubleword register)
C2.4.283 VMRS
C2.4.284 VMSR
C2.4.285 VMUL
C2.4.286 VNEG
C2.4.287 VNMLA
C2.4.288 VNMLS
C2.4.289 VNMUL
C2.4.290 VPOP
C2.4.291 VPUSH
C2.4.292 VRINTA
C2.4.293 VRINTM
C2.4.294 VRINTN
C2.4.295 VRINTP
C2.4.296 VRINTR
C2.4.297 VRINTX
C2.4.298 VRINTZ
C2.4.299 VSEL
C2.4.300 VSQRT
C2.4.301 VSTM
C2.4.302 VSTR
C2.4.303 VSUB
C2.4.304 WFE
C2.4.305 WFI
C2.4.306 YIELD
Part D: ARMv8-M Registers
D1: Register Specification
D1.1 Register index
D1.1.1 Special and general-purpose registers
D1.1.2 Payloads
D1.1.3 Instrumentation Macrocell
D1.1.4 Data Watchpoint and Trace
D1.1.5 Flash Patch and Breakpoint
D1.1.6 Implementation Control Block
D1.1.7 SysTick Timer
D1.1.8 Nested Vectored Interrupt Controller
D1.1.9 System Control Block
D1.1.10 Memory Protection Unit
D1.1.11 Security Attribution Unit
D1.1.12 Debug Control Block
D1.1.13 Software Interrupt Generation
D1.1.14 Floating-point Extension
D1.1.15 Cache Maintenance Operations
D1.1.16 Debug Identification Block
D1.1.17 Implementation Control Block (NS alias)
D1.1.18 SysTick Timer (NS alias)
D1.1.19 Nested Vectored Interrupt Controller (NS alias)
D1.1.20 System Control Block (NS alias)
D1.1.21 Memory Protection Unit (NS alias)
D1.1.22 Debug Control Block (NS alias)
D1.1.23 Software Interrupt Generation (NS alias)
D1.1.24 Floating-point Extension (NS alias)
D1.1.25 Cache Maintenance Operations (NS alias)
D1.1.26 Debug Identification Block (NS alias)
D1.1.27 Trace Port Interface Unit
D1.2 Alphabetical list of registers
D1.2.1 ACTLR, Auxiliary Control Register
D1.2.2 AFSR, Auxiliary Fault Status Register
D1.2.3 AIRCR, Application Interrupt and Reset Control Register
D1.2.4 APSR, Application Program Status Register
D1.2.5 BASEPRI, Base Priority Mask Register
D1.2.6 BFAR, BusFault Address Register
D1.2.7 BFSR, BusFault Status Register
D1.2.8 BPIALL, Branch Predictor Invalidate All
D1.2.9 CCR, Configuration and Control Register
D1.2.10 CCSIDR, Current Cache Size ID register
D1.2.11 CFSR, Configurable Fault Status Register
D1.2.12 CLIDR, Cache Level ID Register
D1.2.13 CONTROL, Control Register
D1.2.14 CPACR, Coprocessor Access Control Register
D1.2.15 CPPWR, Coprocessor Power Control Register
D1.2.16 CPUID, CPUID base register
D1.2.17 CSSELR, Cache Size Selection Register
D1.2.18 CTR, Cache Type Register
D1.2.19 DAUTHCTRL, Debug Authentication Control Register
D1.2.20 DAUTHSTATUS, Debug Authentication Status Register
D1.2.21 DCCIMVAC, Data Cache line Clean and Invalidate by Address to PoC
D1.2.22 DCCISW, Data Cache line Clean and Invalidate by Set/Way
D1.2.23 DCCMVAC, Data Cache line Clean by Address to PoC
D1.2.24 DCCMVAU, Data Cache line Clean by address to PoU
D1.2.25 DCCSW, Data Cache Clean line by Set/Way
D1.2.26 DCIDR0, SCS Component Identification Register 0
D1.2.27 DCIDR1, SCS Component Identification Register 1
D1.2.28 DCIDR2, SCS Component Identification Register 2
D1.2.29 DCIDR3, SCS Component Identification Register 3
D1.2.30 DCIMVAC, Data Cache line Invalidate by Address to PoC
D1.2.31 DCISW, Data Cache line Invalidate by Set/Way
D1.2.32 DCRDR, Debug Core Register Data Register
D1.2.33 DCRSR, Debug Core Register Select Register
D1.2.34 DDEVARCH, SCS Device Architecture Register
D1.2.35 DDEVTYPE, SCS Device Type Register
D1.2.36 DEMCR, Debug Exception and Monitor Control Register
D1.2.37 DFSR, Debug Fault Status Register
D1.2.38 DHCSR, Debug Halting Control and Status Register
D1.2.39 DLAR, SCS Software Lock Access Register
D1.2.40 DLSR, SCS Software Lock Status Register
D1.2.41 DPIDR0, SCS Peripheral Identification Register 0
D1.2.42 DPIDR1, SCS Peripheral Identification Register 1
D1.2.43 DPIDR2, SCS Peripheral Identification Register 2
D1.2.44 DPIDR3, SCS Peripheral Identification Register 3
D1.2.45 DPIDR4, SCS Peripheral Identification Register 4
D1.2.46 DPIDR5, SCS Peripheral Identification Register 5
D1.2.47 DPIDR6, SCS Peripheral Identification Register 6
D1.2.48 DPIDR7, SCS Peripheral Identification Register 7
D1.2.49 DSCSR, Debug Security Control and Status Register
D1.2.50 DWT_CIDR0, DWT Component Identification Register 0
D1.2.51 DWT_CIDR1, DWT Component Identification Register 1
D1.2.52 DWT_CIDR2, DWT Component Identification Register 2
D1.2.53 DWT_CIDR3, DWT Component Identification Register 3
D1.2.54 DWT_COMP, DWT Comparator Register, n = 0 - 14
D1.2.55 DWT_CPICNT, DWT CPI Count Register
D1.2.56 DWT_CTRL, DWT Control Register
D1.2.57 DWT_CYCCNT, DWT Cycle Count Register
D1.2.58 DWT_DEVARCH, DWT Device Architecture Register
D1.2.59 DWT_DEVTYPE, DWT Device Type Register
D1.2.60 DWT_EXCCNT, DWT Exception Overhead Count Register
D1.2.61 DWT_FOLDCNT, DWT Folded Instruction Count Register
D1.2.62 DWT_FUNCTION, DWT Comparator Function Register, n = 0 - 14
D1.2.63 DWT_LAR, DWT Software Lock Access Register
D1.2.64 DWT_LSR, DWT Software Lock Status Register
D1.2.65 DWT_LSUCNT, DWT LSU Count Register
D1.2.66 DWT_PCSR, DWT Program Counter Sample Register
D1.2.67 DWT_PIDR0, DWT Peripheral Identification Register 0
D1.2.68 DWT_PIDR1, DWT Peripheral Identification Register 1
D1.2.69 DWT_PIDR2, DWT Peripheral Identification Register 2
D1.2.70 DWT_PIDR3, DWT Peripheral Identification Register 3
D1.2.71 DWT_PIDR4, DWT Peripheral Identification Register 4
D1.2.72 DWT_PIDR5, DWT Peripheral Identification Register 5
D1.2.73 DWT_PIDR6, DWT Peripheral Identification Register 6
D1.2.74 DWT_PIDR7, DWT Peripheral Identification Register 7
D1.2.75 DWT_SLEEPCNT, DWT Sleep Count Register
D1.2.76 EPSR, Execution Program Status Register
D1.2.77 EXC_RETURN, Exception Return Payload
D1.2.78 FAULTMASK, Fault Mask Register
D1.2.79 FNC_RETURN, Function Return Payload
D1.2.80 FPCAR, Floating-Point Context Address Register
D1.2.81 FPCCR, Floating-Point Context Control Register
D1.2.82 FPDSCR, Floating-Point Default Status Control Register
D1.2.83 FPSCR, Floating-point Status and Control Register
D1.2.84 FP_CIDR0, FP Component Identification Register 0
D1.2.85 FP_CIDR1, FP Component Identification Register 1
D1.2.86 FP_CIDR2, FP Component Identification Register 2
D1.2.87 FP_CIDR3, FP Component Identification Register 3
D1.2.88 FP_COMP, Flash Patch Comparator Register, n = 0 - 141
D1.2.89 FP_CTRL, Flash Patch Control Register
D1.2.90 FP_DEVARCH, FPB Device Architecture Register
D1.2.91 FP_DEVTYPE, FPB Device Type Register
D1.2.92 FP_LAR, FPB Software Lock Access Register
D1.2.93 FP_LSR, FPB Software Lock Status Register
D1.2.94 FP_PIDR0, FP Peripheral Identification Register 0
D1.2.95 FP_PIDR1, FP Peripheral Identification Register 1
D1.2.96 FP_PIDR2, FP Peripheral Identification Register 2
D1.2.97 FP_PIDR3, FP Peripheral Identification Register 3
D1.2.98 FP_PIDR4, FP Peripheral Identification Register 4
D1.2.99 FP_PIDR5, FP Peripheral Identification Register 5
D1.2.100 FP_PIDR6, FP Peripheral Identification Register 6
D1.2.101 FP_PIDR7, FP Peripheral Identification Register 7
D1.2.102 FP_REMAP, Flash Patch Remap Register
D1.2.103 HFSR, HardFault Status Register
D1.2.104 ICIALLU, Instruction Cache Invalidate All to PoU
D1.2.105 ICIMVAU, Instruction Cache line Invalidate by Address to PoU
D1.2.106 ICSR, Interrupt Control and State Register
D1.2.107 ICTR, Interrupt Controller Type Register
D1.2.108 ID_AFR0, Auxiliary Feature Register 0
D1.2.109 ID_DFR0, Debug Feature Register 0
D1.2.110 ID_ISAR0, Instruction Set Attribute Register 0
D1.2.111 ID_ISAR1, Instruction Set Attribute Register 1
D1.2.112 ID_ISAR2, Instruction Set Attribute Register 2
D1.2.113 ID_ISAR3, Instruction Set Attribute Register 3
D1.2.114 ID_ISAR4, Instruction Set Attribute Register 4
D1.2.115 ID_ISAR5, Instruction Set Attribute Register 5
D1.2.116 ID_MMFR0, Memory Model Feature Register 0
D1.2.117 ID_MMFR1, Memory Model Feature Register 1
D1.2.118 ID_MMFR2, Memory Model Feature Register 2
D1.2.119 ID_MMFR3, Memory Model Feature Register 3
D1.2.120 ID_PFR0, Processor Feature Register 0
D1.2.121 ID_PFR1, Processor Feature Register 1
D1.2.122 IPSR, Interrupt Program Status Register
D1.2.123 ITM_CIDR0, ITM Component Identification Register 0
D1.2.124 ITM_CIDR1, ITM Component Identification Register 1
D1.2.125 ITM_CIDR2, ITM Component Identification Register 2
D1.2.126 ITM_CIDR3, ITM Component Identification Register 3
D1.2.127 ITM_DEVARCH, ITM Device Architecture Register
D1.2.128 ITM_DEVTYPE, ITM Device Type Register
D1.2.129 ITM_LAR, ITM Software Lock Access Register
D1.2.130 ITM_LSR, ITM Software Lock Status Register
D1.2.131 ITM_PIDR0, ITM Peripheral Identification Register 0
D1.2.132 ITM_PIDR1, ITM Peripheral Identification Register 1
D1.2.133 ITM_PIDR2, ITM Peripheral Identification Register 2
D1.2.134 ITM_PIDR3, ITM Peripheral Identification Register 3
D1.2.135 ITM_PIDR4, ITM Peripheral Identification Register 4
D1.2.136 ITM_PIDR5, ITM Peripheral Identification Register 5
D1.2.137 ITM_PIDR6, ITM Peripheral Identification Register 6
D1.2.138 ITM_PIDR7, ITM Peripheral Identification Register 7
D1.2.139 ITM_STIM, ITM Stimulus Port Register, n = 0 - 255
D1.2.140 ITM_TCR, ITM Trace Control Register
D1.2.141 ITM_TER, ITM Trace Enable Register, n = 0 - 7
D1.2.142 ITM_TPR, ITM Trace Privilege Register
D1.2.143 LR, Link Register
D1.2.144 MAIR_ATTR, Memory Attribute Indirection Register Attributes
D1.2.145 MMFAR, MemManage Fault Address Register
D1.2.146 MMFSR, MemManage Fault Status Register
D1.2.147 MPU_CTRL, MPU Control Register
D1.2.148 MPU_MAIR0, MPU Memory Attribute Indirection Register 0
D1.2.149 MPU_MAIR1, MPU Memory Attribute Indirection Register 1
D1.2.150 MPU_RBAR, MPU Region Base Address Register
D1.2.151 MPU_RBAR_A, MPU Region Base Address Register Alias, n = 1 - 3
D1.2.152 MPU_RLAR, MPU Region Limit Address Register
D1.2.153 MPU_RLAR_A, MPU Region Limit Address Register Alias, n = 1 - 3
D1.2.154 MPU_RNR, MPU Region Number Register
D1.2.155 MPU_TYPE, MPU Type Register
D1.2.156 MSPLIM, Main Stack Pointer Limit Register
D1.2.157 MVFR0, Media and VFP Feature Register 0
D1.2.158 MVFR1, Media and VFP Feature Register 1
D1.2.159 MVFR2, Media and VFP Feature Register 2
D1.2.160 NSACR, Non-secure Access Control Register
D1.2.161 NVIC_IABR, Interrupt Active Bit Register, n = 0 - 15
D1.2.162 NVIC_ICER, Interrupt Clear Enable Register, n = 0 - 15
D1.2.163 NVIC_ICPR, Interrupt Clear Pending Register, n = 0 - 15
D1.2.164 NVIC_IPR, Interrupt Priority Register, n = 0 - 123
D1.2.165 NVIC_ISER, Interrupt Set Enable Register, n = 0 - 15
D1.2.166 NVIC_ISPR, Interrupt Set Pending Register, n = 0 - 15
D1.2.167 NVIC_ITNS, Interrupt Target Non-secure Register, n = 0 - 15
D1.2.168 PC, Program Counter
D1.2.169 PRIMASK, Exception Mask Register
D1.2.170 PSPLIM, Process Stack Pointer Limit Register
D1.2.171 R, general-purpose register, n = 0 - 12
D1.2.172 RETPSR, Combined Exception Return Program Status Registers
D1.2.173 SAU_CTRL, SAU Control Register
D1.2.174 SAU_RBAR, SAU Region Base Address Register
D1.2.175 SAU_RLAR, SAU Region Limit Address Register
D1.2.176 SAU_RNR, SAU Region Number Register
D1.2.177 SAU_TYPE, SAU Type Register
D1.2.178 SCR, System Control Register
D1.2.179 SFAR, Secure Fault Address Register
D1.2.180 SFSR, Secure Fault Status Register
D1.2.181 SHCSR, System Handler Control and State Register
D1.2.182 SHPR1, System Handler Priority Register 1
D1.2.183 SHPR2, System Handler Priority Register 2
D1.2.184 SHPR3, System Handler Priority Register 3
D1.2.185 SP, Current Stack Pointer Register
D1.2.186 SP_NS, Stack Pointer (Non-secure)
D1.2.187 STIR, Software Triggered Interrupt Register
D1.2.188 SYST_CALIB, SysTick Calibration Value Register
D1.2.189 SYST_CSR, SysTick Control and Status Register
D1.2.190 SYST_CVR, SysTick Current Value Register
D1.2.191 SYST_RVR, SysTick Reload Value Register
D1.2.192 TPIU_ACPR, TPIU Asynchronous Clock Prescaler Register
D1.2.193 TPIU_CIDR0, TPIU Component Identification Register 0
D1.2.194 TPIU_CIDR1, TPIU Component Identification Register 1
D1.2.195 TPIU_CIDR2, TPIU Component Identification Register 2
D1.2.196 TPIU_CIDR3, TPIU Component Identification Register 3
D1.2.197 TPIU_CSPSR, TPIU Current Parallel Port Sizes Register
D1.2.198 TPIU_DEVTYPE, TPIU Device Type Register
D1.2.199 TPIU_FFCR, TPIU Formatter and Flush Control Register
D1.2.200 TPIU_FFSR, TPIU Formatter and Flush Status Register
D1.2.201 TPIU_LAR, TPIU Software Lock Access Register
D1.2.202 TPIU_LSR, TPIU Software Lock Status Register
D1.2.203 TPIU_PIDR0, TPIU Peripheral Identification Register 0
D1.2.204 TPIU_PIDR1, TPIU Peripheral Identification Register 1
D1.2.205 TPIU_PIDR2, TPIU Peripheral Identification Register 2
D1.2.206 TPIU_PIDR3, TPIU Peripheral Identification Register 3
D1.2.207 TPIU_PIDR4, TPIU Peripheral Identification Register 4
D1.2.208 TPIU_PIDR5, TPIU Peripheral Identification Register 5
D1.2.209 TPIU_PIDR6, TPIU Peripheral Identification Register 6
D1.2.210 TPIU_PIDR7, TPIU Peripheral Identification Register 7
D1.2.211 TPIU_PSCR, TPIU Periodic Synchronization Control Register
D1.2.212 TPIU_SPPR, TPIU Selected Pin Protocol Register
D1.2.213 TPIU_SSPSR, TPIU Supported Parallel Port Sizes Register
D1.2.214 TPIU_TYPE, TPIU Device Identifier Register
D1.2.215 TT_RESP, Test Target Response Payload
D1.2.216 UFSR, UsageFault Status Register
D1.2.217 VTOR, Vector Table Offset Register
D1.2.218 XPSR, Combined Program Status Registers
Part E: ARMv8-M Pseudocode
E1: ARM Pseudocode Definition
E1.1 About the ARM pseudocode
E1.1.1 General limitations of ARM pseudocode
E1.2 Data types
E1.2.1 General data type rules
E1.2.2 Bitstrings
Syntax
Description
E1.2.3 Integers
Syntax
Description
E1.2.4 Reals
Syntax
Description
E1.2.5 Booleans
Syntax
Description
E1.2.6 Enumerations
Syntax and examples
Description
E1.2.7 Structures
Syntax and examples
Description
E1.2.8 Tuples
Examples
Description
E1.2.9 Arrays
Syntax
Description
E1.3 Operators
E1.3.1 Relational operators
Equality and non-equality
Comparisons
Set membership with IN
E1.3.2 Boolean operators
E1.3.3 Bitstring operators
Logical operations on bitstrings
Bitstring concatenation and slicing
E1.3.4 Arithmetic operators
Unary plus and minus
Addition and subtraction
Multiplication
Division and modulo
Scaling
Raising to a power
E1.3.5 The assignment operator
General expression syntax
E1.3.6 Precedence rules
E1.3.7 Conditional expressions
E1.3.8 Operator polymorphism
E1.4 Statements and control structures
E1.4.1 Statements and Indentation
E1.4.2 Function and procedure calls
Procedure and function definitions
Procedure calls
Return statements
E1.4.3 Conditional control structures
if … then … else …
case … of …
E1.4.4 Loop control structures
repeat … until …
while … do
for …
E1.4.5 Special statements
UNDEFINED
UNPREDICTABLE
SEE…
IMPLEMENTATION_DEFINED
E1.4.6 Comments
E1.5 Built-in functions
E1.5.1 Bitstring manipulation functions
Bitstring length
Bitstring concatenation and replication
Bitstring count
Testing a bitstring for being all zero or all ones
Lowest and highest set bits of a bitstring
Zero-extension and sign-extension of bitstrings
Converting bitstrings to integers
E1.5.2 Arithmetic functions
Absolute value
Rounding and aligning
Maximum and minimum
E1.6 ARM pseudocode definition index
E2: Pseudocode Specification
E2.1 Alphabetical Pseudocode List
E2.1.1 ALUWritePC
E2.1.2 ASR
E2.1.3 ASR_C
E2.1.4 AccType
E2.1.5 AccessAttributes
E2.1.6 ActivateException
E2.1.7 AddWithCarry
E2.1.8 AddressDescriptor
E2.1.9 BKPTInstrDebugEvent
E2.1.10 BLXWritePC
E2.1.11 BXWritePC
E2.1.12 BigEndian
E2.1.13 BigEndianReverse
E2.1.14 BranchTo
E2.1.15 BranchToAndCommit
E2.1.16 BranchToNS
E2.1.17 BranchWritePC
E2.1.18 CallSupervisor
E2.1.19 CanHaltOnEvent
E2.1.20 CanPendMonitorOnEvent
E2.1.21 CheckCPEnabled
E2.1.22 CheckDecodeFaults
E2.1.23 CheckPermission
E2.1.24 ClearEventRegister
E2.1.25 ClearExclusiveByAddress
E2.1.26 ClearExclusiveLocal
E2.1.27 ComparePriorities
E2.1.28 ConditionHolds
E2.1.29 ConditionPassed
E2.1.30 ConstrainUnpredictableBool
E2.1.31 ConsumeExcStackFrame
E2.1.32 Coproc_Accepted
E2.1.33 Coproc_DoneLoading
E2.1.34 Coproc_DoneStoring
E2.1.35 Coproc_GetOneWord
E2.1.36 Coproc_GetTwoWords
E2.1.37 Coproc_GetWordToStore
E2.1.38 Coproc_InternalOperation
E2.1.39 Coproc_SendLoadedWord
E2.1.40 Coproc_SendOneWord
E2.1.41 Coproc_SendTwoWords
E2.1.42 CreateException
E2.1.43 CurrentCond
E2.1.44 CurrentMode
E2.1.45 CurrentModeIsPrivileged
E2.1.46 D
E2.1.47 DWT_AddressCompare
E2.1.48 DWT_CycCountMatch
E2.1.49 DWT_DataAddressMatch
E2.1.50 DWT_DataMatch
E2.1.51 DWT_DataValueMatch
E2.1.52 DWT_InstructionAddressMatch
E2.1.53 DWT_InstructionMatch
E2.1.54 DWT_ValidMatch
E2.1.55 DataMemoryBarrier
E2.1.56 DataSynchronizationBarrier
E2.1.57 Deactivate
E2.1.58 Debug_authentication
E2.1.59 DecodeExecute
E2.1.60 DecodeImmShift
E2.1.61 DecodeRegShift
E2.1.62 DefaultExcInfo
E2.1.63 DefaultMemoryAttributes
E2.1.64 DefaultPermissions
E2.1.65 DerivedLateArrival
E2.1.66 DeviceType
E2.1.67 EndOfInstruction
E2.1.68 EventRegistered
E2.1.69 ExcInfo
E2.1.70 ExceptionActiveBitCount
E2.1.71 ExceptionDetails
E2.1.72 ExceptionEnabled
E2.1.73 ExceptionEntry
E2.1.74 ExceptionPriority
E2.1.75 ExceptionReturn
E2.1.76 ExceptionTaken
E2.1.77 ExceptionTargetsSecure
E2.1.78 ExclusiveMonitorsPass
E2.1.79 ExecuteCPCheck
E2.1.80 ExecuteFPCheck
E2.1.81 ExecutionPriority
E2.1.82 ExternalInvasiveDebugEnabled
E2.1.83 ExternalNoninvasiveDebugEnabled
E2.1.84 ExternalSecureInvasiveDebugEnabled
E2.1.85 ExternalSecureNoninvasiveDebugEnabled
E2.1.86 ExternalSecureSelfHostedDebugEnabled
E2.1.87 FPAbs
E2.1.88 FPAdd
E2.1.89 FPB_BreakpointMatch
E2.1.90 FPB_CheckBreakPoint
E2.1.91 FPB_CheckMatchAddress
E2.1.92 FPCompare
E2.1.93 FPDefaultNaN
E2.1.94 FPDiv
E2.1.95 FPDoubleToHalf
E2.1.96 FPDoubleToSingle
E2.1.97 FPExc
E2.1.98 FPHalfToDouble
E2.1.99 FPHalfToSingle
E2.1.100 FPInfinity
E2.1.101 FPMax
E2.1.102 FPMaxNormal
E2.1.103 FPMaxNum
E2.1.104 FPMin
E2.1.105 FPMinNum
E2.1.106 FPMul
E2.1.107 FPMulAdd
E2.1.108 FPNeg
E2.1.109 FPProcessException
E2.1.110 FPProcessNaN
E2.1.111 FPProcessNaNs
E2.1.112 FPProcessNaNs3
E2.1.113 FPRound
E2.1.114 FPRoundInt
E2.1.115 FPSingleToDouble
E2.1.116 FPSingleToHalf
E2.1.117 FPSqrt
E2.1.118 FPSub
E2.1.119 FPToFixed
E2.1.120 FPToFixedDirected
E2.1.121 FPType
E2.1.122 FPUnpack
E2.1.123 FPZero
E2.1.124 FaultNumbers
E2.1.125 FetchInstr
E2.1.126 FindPriv
E2.1.127 FixedToFP
E2.1.128 FunctionReturn
E2.1.129 GenerateCoprocessorException
E2.1.130 GenerateDebugEventResponse
E2.1.131 GenerateIntegerZeroDivide
E2.1.132 HaltingDebugAllowed
E2.1.133 HandleException
E2.1.134 HaveDSPExt
E2.1.135 HaveDWT
E2.1.136 HaveDebugMonitor
E2.1.137 HaveFPB
E2.1.138 HaveFPExt
E2.1.139 HaveHaltingDebug
E2.1.140 HaveITM
E2.1.141 HaveMainExt
E2.1.142 HaveSPFPOnly
E2.1.143 HaveSecurityExt
E2.1.144 HaveSysTick
E2.1.145 HighestPri
E2.1.146 Hint_Debug
E2.1.147 Hint_PreloadData
E2.1.148 Hint_PreloadDataForWrite
E2.1.149 Hint_PreloadInstr
E2.1.150 Hint_Yield
E2.1.151 IDAUCheck
E2.1.152 ITAdvance
E2.1.153 ITSTATE
E2.1.154 ITSTATEType
E2.1.155 InITBlock
E2.1.156 InstructionAdvance
E2.1.157 InstructionSynchronizationBarrier
E2.1.158 Int
E2.1.159 IntegerZeroDivideTrappingEnabled
E2.1.160 IsAccessible
E2.1.161 IsActiveForState
E2.1.162 IsAligned
E2.1.163 IsCPEnabled
E2.1.164 IsDWTConfigUnpredictable
E2.1.165 IsDWTEnabled
E2.1.166 IsExceptionTargetConfigurable
E2.1.167 IsExclusiveGlobal
E2.1.168 IsExclusiveLocal
E2.1.169 IsIrqValid
E2.1.170 IsReqExcPriNeg
E2.1.171 IsSecure
E2.1.172 LR
E2.1.173 LSL
E2.1.174 LSL_C
E2.1.175 LSR
E2.1.176 LSR_C
E2.1.177 LastInITBlock
E2.1.178 LoadWritePC
E2.1.179 Lockup
E2.1.180 LookUpRName
E2.1.181 LookUpSP
E2.1.182 LookUpSPLim
E2.1.183 LookUpSP_with_security_mode
E2.1.184 MAIRDecode
E2.1.185 MPUCheck
E2.1.186 MarkExclusiveGlobal
E2.1.187 MarkExclusiveLocal
E2.1.188 MaxExceptionNum
E2.1.189 MemA
E2.1.190 MemA_with_priv
E2.1.191 MemA_with_priv_security
E2.1.192 MemI
E2.1.193 MemO
E2.1.194 MemType
E2.1.195 MemU
E2.1.196 MemU_unpriv
E2.1.197 MemU_with_priv
E2.1.198 MemoryAttributes
E2.1.199 MergeExcInfo
E2.1.200 NextInstrAddr
E2.1.201 NextInstrITState
E2.1.202 NoninvasiveDebugAllowed
E2.1.203 PC
E2.1.204 PEMode
E2.1.205 PendReturnOperation
E2.1.206 PendingExceptionDetails
E2.1.207 Permissions
E2.1.208 PopStack
E2.1.209 PreserveFPState
E2.1.210 ProcessorID
E2.1.211 PushCalleeStack
E2.1.212 PushStack
E2.1.213 R
E2.1.214 RName
E2.1.215 ROR
E2.1.216 ROR_C
E2.1.217 RRX
E2.1.218 RRX_C
E2.1.219 RSPCheck
E2.1.220 RaiseAsyncBusFault
E2.1.221 RawExecutionPriority
E2.1.222 ResetSCSRegs
E2.1.223 RestrictedNSPri
E2.1.224 ReturnState
E2.1.225 S
E2.1.226 SAttributes
E2.1.227 SCS_UpdateStatusRegs
E2.1.228 SP
E2.1.229 SP_Main
E2.1.230 SP_Main_NonSecure
E2.1.231 SP_Main_Secure
E2.1.232 SP_Process
E2.1.233 SP_Process_NonSecure
E2.1.234 SP_Process_Secure
E2.1.235 SRType
E2.1.236 Sat
E2.1.237 SatQ
E2.1.238 SecureDebugMonitorAllowed
E2.1.239 SecureHaltingDebugAllowed
E2.1.240 SecureNoninvasiveDebugAllowed
E2.1.241 SecurityCheck
E2.1.242 SecurityState
E2.1.243 SendEvent
E2.1.244 SerializeVFP
E2.1.245 SetActive
E2.1.246 SetDWTDebugEvent
E2.1.247 SetEventRegister
E2.1.248 SetExclusiveMonitors
E2.1.249 SetITSTATEAndCommit
E2.1.250 SetMonStep
E2.1.251 SetPending
E2.1.252 SetThisInstrDetails
E2.1.253 Shift
E2.1.254 Shift_C
E2.1.255 SignedSat
E2.1.256 SignedSatQ
E2.1.257 SleepOnExit
E2.1.258 Stack
E2.1.259 StandardFPSCRValue
E2.1.260 SteppingDebug
E2.1.261 T32ExpandImm
E2.1.262 T32ExpandImm_C
E2.1.263 TTResp
E2.1.264 TailChain
E2.1.265 TakePreserveFPException
E2.1.266 TakeReset
E2.1.267 ThisInstr
E2.1.268 ThisInstrAddr
E2.1.269 ThisInstrITState
E2.1.270 ThisInstrLength
E2.1.271 TopLevel
E2.1.272 UnsignedSat
E2.1.273 UnsignedSatQ
E2.1.274 UpdateFPCCR
E2.1.275 UpdateSecureDebugEnable
E2.1.276 VFPExcBarrier
E2.1.277 VFPExpandImm
E2.1.278 VFPNegMul
E2.1.279 VFPSmallRegisterBank
E2.1.280 ValidateAddress
E2.1.281 ValidateExceptionReturn
E2.1.282 Vector
E2.1.283 WaitForEvent
E2.1.284 WaitForInterrupt
E2.1.285 _D
E2.1.286 _ITStateChanged
E2.1.287 _Mem
E2.1.288 _NextInstrAddr
E2.1.289 _NextInstrITState
E2.1.290 _PCChanged
E2.1.291 _PendingReturnOperation
E2.1.292 _R
E2.1.293 _SP
E2.1.294 common
Part F: Debug Packet Protocols
F1: ITM and DWT Packet Protocol Specification
F1.1 About the ITM and DWT packets
F1.1.1 Uses of ITM and DWT packets
F1.1.2 ITM and DWT protocol packet headers
F1.1.3 Packet transmission by the trace sink
F1.2 Alphabetical list of DWT and ITM packets
F1.2.1 Data Trace Data Address packet
F1.2.2 Data Trace Data Value packet
F1.2.3 Data Trace Match packet
F1.2.4 Data Trace PC Value packet
F1.2.5 Event Counter packet
F1.2.6 Exception Trace packet
F1.2.7 Extension packet
F1.2.8 Global Timestamp 1 packet
F1.2.9 Global Timestamp 2 packet
F1.2.10 Instrumentation packet
F1.2.11 Local Timestamp 1 packet
F1.2.12 Local Timestamp 2 packet
F1.2.13 Overflow packet
F1.2.14 Periodic PC Sample packet
F1.2.15 Synchronization packet
Glossary
ARM®v8-M Architecture
Reference Manual
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Contents
ARMv8-M Architecture Reference Manual
Preface
About this book .......................................................................................................... xii
Using this book .......................................................................................................... xiii
Conventions .............................................................................................................. xv
Additional reading .................................................................................................... xvii
Feedback ................................................................................................................ xviii
ARMv8-M Architecture Introduction and Overview
Introduction
A1.1
A1.2
A1.3
A1.4
Document layout and terminology ....................................................................... A1-22
About the ARMv8 architecture, and architecture profiles .................................... A1-24
The ARMv8-M architecture profile ...................................................................... A1-25
ARMv8-M variants ............................................................................................... A1-27
ARMv8-M Architecture Rules
Resets
B1.1
Resets, Cold reset, and Warm reset ................................................................... B1-32
Power Management
B2.1
Power management ............................................................................................ B2-34
Programmers’ Model
B3.1
B3.2
PE modes, Thread mode and Handler mode ...................................................... B3-39
Privileged and unprivileged execution ................................................................. B3-40
Part A
Chapter A1
Part B
Chapter B1
Chapter B2
Chapter B3
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Contents
Chapter B4
Chapter B5
Registers ............................................................................................................. B3-41
B3.3
XPSR, APSR, IPSR, and EPSR ......................................................................... B3-43
B3.4
Security states, Secure state, and Non-secure state .......................................... B3-46
B3.5
Security states, register banking between them ................................................. B3-47
B3.6
Stack pointer ....................................................................................................... B3-48
B3.7
Exception numbers and exception priority numbers ........................................... B3-49
B3.8
B3.9
Exception enable, pending, and active bits ......................................................... B3-52
B3.10 Security states, exception banking ...................................................................... B3-53
B3.11
Faults .................................................................................................................. B3-55
B3.12 Priority model ...................................................................................................... B3-59
B3.13 Secure address protection .................................................................................. B3-63
B3.14 Security state transitions ..................................................................................... B3-64
Function calls from Secure state to Non-secure state ........................................ B3-65
B3.15
B3.16
Function returns from Non-secure state .............................................................. B3-66
B3.17 Exception handling .............................................................................................. B3-67
B3.18 Exception entry, context stacking ........................................................................ B3-69
B3.19 Exception entry, register clearing after context stacking ..................................... B3-74
B3.20 Stack limit checks ................................................................................................ B3-75
B3.21 Exception return .................................................................................................. B3-78
B3.22
Integrity signature ................................................................................................ B3-81
B3.23 Exceptions during exception entry ...................................................................... B3-82
B3.24 Exceptions during exception return ..................................................................... B3-83
B3.25
Tail-chaining ........................................................................................................ B3-84
B3.26 Exceptions, instruction resume, or instruction restart ......................................... B3-86
B3.27 Vector tables ....................................................................................................... B3-88
B3.28 Hardware-controlled priority escalation to HardFault .......................................... B3-90
B3.29 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK, for
software-controlled priority boosting ................................................................... B3-91
B3.30
Lockup ................................................................................................................. B3-93
B3.31 Exception during a singleword load operation .................................................... B3-98
B3.32 Special-purpose CONTROL register ................................................................... B3-99
B3.33 Saving context on process switch ..................................................................... B3-100
B3.34 Context Synchronization Event ......................................................................... B3-101
B3.35 Coprocessor support ......................................................................................... B3-102
Floating-point Support
B4.1
B4.2
B4.3
B4.4
B4.5
B4.6
The optional Floating-point Extension, FPv5 .................................................... B4-104
About the Floating-point Status and Control Register (FPSCR) ....................... B4-105
Registers for floating-point data processing, S0-S31, or D0-D15 ..................... B4-106
Floating-point standards and terminology ......................................................... B4-107
Floating-point data representable ..................................................................... B4-108
Floating-point encoding formats, half-precision, single-precision, and double-precision
B4-109
B4.7
The IEEE 754 floating-point exceptions ............................................................ B4-111
B4.8
The Flush-to-zero mode .................................................................................... B4-112
B4.9
The Default NaN mode, and NaN handling ....................................................... B4-113
B4.10
The Default NaN ............................................................................................... B4-114
B4.11 Combinations of floating-point exceptions ........................................................ B4-115
B4.12 Priority of floating-point exceptions relative to other floating-point exceptions .. B4-116
Memory Model
B5.1
B5.2
B5.3
B5.4
B5.5
B5.6
B5.7
B5.8
Memory accesses ............................................................................................. B5-119
Address space .................................................................................................. B5-120
Endianness ....................................................................................................... B5-121
Alignment behavior ........................................................................................... B5-123
Atomicity ............................................................................................................ B5-124
Concurrent modification and execution of instructions ...................................... B5-125
Access rights ..................................................................................................... B5-126
Observability of memory accesses ................................................................... B5-127
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B5.9
Completion of memory accesses ...................................................................... B5-128
B5.10 Ordering requirements for memory accesses ................................................... B5-129
B5.11 Ordering of implicit memory accesses .............................................................. B5-130
B5.12 Ordering of explicit memory accesses .............................................................. B5-131
B5.13 Memory barriers ................................................................................................ B5-132
B5.14 Normal memory ................................................................................................. B5-135
B5.15 Cacheability attributes ....................................................................................... B5-136
B5.16 Device memory ................................................................................................. B5-137
B5.17 Device memory attributes ................................................................................. B5-138
B5.18 Shareability domains ......................................................................................... B5-141
B5.19 Shareability attributes ........................................................................................ B5-142
B5.20 Memory access restrictions ............................................................................... B5-143
B5.21 Mismatched memory attributes ......................................................................... B5-144
Load-Exclusive and Store-Exclusive accesses to Normal memory .................. B5-146
B5.22
B5.23
Load-Acquire and Store-Release accesses to memory .................................... B5-147
B5.24 Caches .............................................................................................................. B5-149
B5.25 Cache identification ........................................................................................... B5-151
B5.26 Cache visibility .................................................................................................. B5-152
B5.27 Cache coherency .............................................................................................. B5-153
B5.28 Cache enabling and disabling ........................................................................... B5-154
B5.29 Cache behavior at reset .................................................................................... B5-155
B5.30 Behavior of Preload Data (PLD) and Preload Instruction (PLI) instructions with caches
B5-156
B5.31 Branch predictors .............................................................................................. B5-157
B5.32 Cache maintenance operations ........................................................................ B5-158
B5.33 Ordering of cache maintenance operations ...................................................... B5-161
B5.34 Branch predictor maintenance operations ........................................................ B5-162
Chapter B6
Chapter B7
Chapter B8
Chapter B9
Chapter B10
Chapter B11
The System Address Map
B6.1
B6.2
B6.3
System address map ........................................................................................ B6-164
The System region of the system address map ................................................ B6-165
The System Control Space (SCS) .................................................................... B6-166
Synchronization and Semaphores
B7.1
B7.2
B7.3
B7.4
B7.5
Exclusive access instructions ............................................................................ B7-168
The local monitors ............................................................................................. B7-169
The global monitor ............................................................................................ B7-170
Exclusive access instructions and the monitors ................................................ B7-173
Load-Exclusive and Store-Exclusive instruction constraints ............................. B7-174
The ARMv8-M Protected Memory System Architecture
B8.1
B8.2
B8.3
B8.4
Memory Protection Unit .................................................................................... B8-178
Security attribution ........................................................................................... B8-180
Security attribution unit (SAU) ........................................................................... B8-182
IMPLEMENTATION DEFINED Attribution Unit (IDAU) ..................................... B8-183
The System Timer, SysTick
B9.1
The system timer, SysTick ................................................................................ B9-186
Nested Vectored Interrupt Controller
B10.1 NVIC definition ................................................................................................ B10-188
B10.2 NVIC operation ................................................................................................ B10-189
Debug
B11.1 About debug .................................................................................................... B11-192
B11.2 Accessing debug features ............................................................................... B11-196
B11.3 Debug authentication interface ....................................................................... B11-199
B11.4 Debug event behavior ..................................................................................... B11-205
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Contents
Chapter B12
Part C
Chapter C1
Chapter C2
Part D
Chapter D1
Part E
Chapter E1
B11.5 Exiting Debug state ......................................................................................... B11-214
B11.6 Multiprocessor support .................................................................................... B11-215
Debug and Trace Components
B12.1
Instrumentation Trace Macrocell ..................................................................... B12-218
B12.2 Data Watchpoint and Trace unit ...................................................................... B12-224
B12.3 Embedded Trace Macrocell ............................................................................ B12-238
Trace Port Interface Unit ................................................................................. B12-239
B12.4
B12.5
Flash Patch and Breakpoint unit ..................................................................... B12-240
ARMv8-M Instruction Set
Instruction Set Overview
Instruction set .................................................................................................... C1-248
C1.1
Format of instruction descriptions ..................................................................... C1-249
C1.2
Pseudocode for instruction descriptions ........................................................... C1-252
C1.3
Unified Assembler Language ............................................................................ C1-254
C1.4
Standard assembler syntax fields ..................................................................... C1-256
C1.5
Conditional execution ........................................................................................ C1-257
C1.6
Instruction set encoding information ................................................................. C1-261
C1.7
Modified immediate constants ........................................................................... C1-264
C1.8
NOP-compatible hint instructions ...................................................................... C1-265
C1.9
Instruction set, interworking support ................................................................. C1-266
C1.10
C1.11
Instruction set, interstating support ................................................................... C1-267
C1.12 SBZ or SBO fields in instructions ...................................................................... C1-268
Instruction Specification
C2.1
C2.2
C2.3
C2.4
Top level T32 instruction set encoding .............................................................. C2-270
16-bit T32 instruction encoding ......................................................................... C2-271
32-bit T32 instruction encoding ......................................................................... C2-282
Alphabetical list of instructions .......................................................................... C2-321
ARMv8-M Registers
Register Specification
D1.1
D1.2
Register index ................................................................................................... D1-830
Alphabetical list of registers .............................................................................. D1-846
ARMv8-M Pseudocode
ARM Pseudocode Definition
E1.1
E1.2
E1.3
E1.4
E1.5
E1.6
About the ARM pseudocode ........................................................................... E1-1160
Data types ....................................................................................................... E1-1161
Operators ........................................................................................................ E1-1166
Statements and control structures .................................................................. E1-1172
Built-in functions .............................................................................................. E1-1178
ARM pseudocode definition index ................................................................... E1-1181
Chapter E2
Pseudocode Specification
E2.1
Alphabetical Pseudocode List ......................................................................... E2-1186
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