DFT Compiler Scan User Guide Version E-2010.12-SP2, March 2011.pdf

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Preface

Key Design-for-Test Flows and Methodologies

Design-for-Test Flows in the Logical Domain

Unmapped Design Flow

Synthesizing Your Design

Postprocessing Your Design

Building Scan Chains

Mapped Design Flow

Reading In Your Design

Performing Scan Replacement and Building Scan Chains

Mapped Designs With Existing Scan Flow

Reading In Your Design

Checking Test Design Rules

Designing Block by Block

Controlling Scan Replacement During Scan Insertion

Hierarchical Scan Synthesis Flow

Introduction to Test Models

Linking Test Models to Library Cells

Checking If a Library Contains CTL Models

Scan Assembly Using Test Models

Saving Test Models for Subdesigns

Using Test Models

Reading Designs Into TetraMAX

Managing Test Models

Top-Level Integration

Hierarchical ScanEnable Integration

DFT Flows in Design Compiler Topographical Mode

Supported DFT Features

DFT Insertion Flow in Design Compiler Topographical Mode

Running DFT Insertion in Design Compiler Topographical Mode

Error Messages

Hierarchical Support in Design Compiler Topographical Mode

Top-Level Design Stitching Flow

Bottom-Up/Hierarchical Flow With Test Models

Scan Insertion Methodologies

Bottom-Up Scan Insertion

Top-Down Scan Insertion

DFT Compiler Default Scan Synthesis Approach

Scan Replacement

Scan Element Allocation

Test Signals

Pad Cells

Area and Timing Optimization

Getting the Best Results With Scan Design

DFT Compiler and Power Compiler Interoperability

Improving Testability in Clock Gating

Inserting Control Points in Control Clock Gating

Scan Enable Versus Test Mode

Inserting Observation Points to Control Clock Gating

Choosing a Depth for Observability Logic

Power Compiler/DFT Compiler Interoperability Flows

Using test_mode With Power Compiler

Using Scan Enables With Power Compiler

Connecting Test Pins to Clock-Gating Cells Using insert_dft

Design Requirements

Hookup Testport Connections

Design Rule Checking Changes

Specifying a Particular Signal as Test Pin When Automatically Connecting Test Ports to Clock-Gating Cells

Limitations

Running RTL Test Design Rule Checking

Understanding the Flow

Specifying Setup Variables

Generating a Test Protocol

Defining a Test Protocol

Reading in an Initialization Protocol in STIL Format

Setting the Scan Style

Design Examples

Test Protocol Example 1

Test Protocol Example 2

Running RTL Test DRC

Understanding the Violations

Violations That Prevent Scan Insertion

Uncontrollable Clocks

Latches Enabled at Beginning of Clock Cycle

Asynchronous Control Pins in Active State

Violations That Prevent Data Capture

Clock Used As Data

Black Box Feeds Into Clock or Asynchronous Control

Source Register Launch Before Destination Register Capture

Registered Clock-Gating Circuitry

Three-State Contention

Clock Feeding Multiple Register Inputs

Violations That Reduce Fault Coverage

Combinational Feedback Loops

Clocks That Interact With Register Input

Multiple Clocks That Feed Into Latches and Flip-Flops

Black Boxes

Limitations

Running Test DRC Debugger

Starting and Exiting the Graphical User Interface

Exploring the Graphical User Interface

Logic Hierarchy View

Console Window

Command Line

Viewing Man Pages

Menus

Checking Scan Test Design Rules

Examining DRC Violations

Viewing Test Protocols

Viewing Design Violations

Examining DRC Violations

Inspecting DRC Violations

Inspecting Static DRC Violations

Viewing a Violation

Viewing Multiple Violations

Viewing CTL Models

Inspecting Dynamic DRC Violations

Commands Specific to the DFT GUI

gui_inspect_violations

gui_wave_add_signal

gui_violation_schematic_add_objects

Performing Scan Replacement

Scan Replacement Flow

Preparing for Scan Replacement

Selecting a Scan Replacement Strategy

Identifying Barriers to Scan Replacement

Technology Library Does Not Contain Appropriate Scan Cells

Support for Different Types of Sequential Cells and Violations

Attributes That Prevent Scan Replacement

Invalid Clock Nets

Invalid Asynchronous Pins

Preventing Scan Replacement

Specifying a Scan Style

Types of Scan Styles

Multiplexed Flip-Flop Scan Style

Clocked Scan Style

LSSD Scan Style

Scan Style Considerations

Setting the Scan Style

Verifying Scan Equivalents in the Technology Library

Checking the Technology Library for Scan Cells

Checking for Scan Equivalents

Scan Cell Replacement Strategies

Specifying Scan Cells

Restricting the List of Available Scan Cells

Sample Scan Cell Replacement Strategies

Mapping Sequential Gates in Scan Replacement

Multibit Components

What Are Multibit Components?

How DFT Compiler Assimilates Multibit Components

Controlling Multibit Test Synthesis

Performing Multibit Component Scan Replacement

Disabling Multibit Component Support

Test-Ready Compilation

What Is Test-Ready Compile?

The Test-Ready Compile Flow

Preparing for Test-Ready Compile

Performing Test-Ready Compile in the Logical Domain

Controlling Test-Ready Compile

Comparing Default Compile and Test-Ready Compile

Complex Compile Strategies

Validating Your Netlist

Running the link Command

Running the check_design Command

Performing Constraint-Optimized Scan Insertion

Supported Scan States

Locating Scan Equivalents

Preparing for Constraint-Optimized Scan Insertion

Scan Insertion

Specification Phase

Preview

Synthesis

Pre-Scan Test Design Rule Checking

Test DRC Basics

Test DRC Flow

Preparing Your Design

Creating the Test Protocol

Assigning a Known Logic State

Performing Test Design Rule Checking

Analyzing and Debugging Violations

Summary of Violations

Enhanced Reporting Capability

Test Design Rule Checking Messages

Test Design Rule Checking Message Generation

Understanding Test Design Rule Checking Messages

Effects of Violations on Scan Replacement

Viewing the Sequential Cell Summary

Classifying Sequential Cells

Sequential Cells With Violations

Cells With Scan Shift Violations

Black-Box Cells

Constant Value Cells

Sequential Cells Without Violations

Checking for Modeling Violations

Black-Box Cells

Correcting Black Box Cells

Unsupported Cells

Generic Cells

Scan Cell Equivalents

Scan Cell Equivalents and the dont_touch Attribute

Latches

Nonscan Latches

Setting Timing Attributes

Protocols for Common Design Timing Requirements

Strobe-Before-Clock Protocol

Strobe-After-Clock Protocol

Setting Timing Attributes

test_default_period Attribute

test_default_delay Variable

test_default_bidir_delay Attribute

test_default_strobe Variable

test_default_strobe_width Variable

The Effect of Timing Attributes on Vector Formatting

Creating Test Protocols

Design Characteristics for Test Protocols

scan_style Attribute

signal_type Attributes

Clock Ports

Asynchronous Control Ports

Bidirectional Ports

STIL Test Protocol File Syntax

Defining the test_setup Macro

Defining Basic Signal Timing

Defining the load_unload Procedure

Defining the Shift Procedure

Defining an Initialization Protocol

Scan Shift and Parallel Cycles

Multiplexed Flip-Flop Scan Style

Clocked-Scan Scan Style

LSSD Scan Style

Examining a Test Protocol File

Updating a Protocol in a Scan Chain Inference Flow

Masking DRC Violations

Setting the Severity of DRC Violations

Resetting the Severity of DRC Violations

Reporting the Severity of DRC Violations

Architecting Your Test Design

Configuring Your DFT Architecture

Defining Your Scan Architecture

Setting Design Constraints

Defining Constant Input Ports During Scan

Specifying Test Ports

Specifying Individual Scan Paths

Previewing Your Scan Design

Using preview_dft Versus report_scan_path

Architecting Scan Chains

Specifying a Scan Chain for the Current Design

Controlling the Scan Chain Length

Specifying Limits for Individual Scan Chain Length

Specifying the Global Scan Chain Exact Length

Specifying the Global Scan Chain Length Limit

Determining the Scan Chain Count

Balancing Scan Chains

Multiple Clock Domains

Multibit Components and Scan Chains

Controlling the Routing Order

Routing Scan Chains and Global Signals

Rerouting Scan Chains

Stitching Scan Chains Without Optimization

Specifying a Stitch-Only Design

Mapping the Replacement of Nonscan Cells to Scan Cells

Conditions Under Which Scan Cells Are Excluded or Nonscan Cells Become Scan Cells

Using Existing Subdesign Scan Chains

Uniquifying Your Design

Reporting Scan Path Information on the Current Design

Architecting Scan Signals

Specifying Scan Signals for the Current Design

Selecting Test Ports

Sharing Scan-In Pins With Multiple Scan Chains

Sharing a Scan Input With a Functional Port

Sharing a Scan Output With a Functional Port

Associating Scan Enable Ports With Multiple Scan Chains

Defining a Dedicated Scan Enable Signal for Connecting Only to Scan Cells

Connecting the Scan Enable Signal in Hierarchical Flows

Using Dedicated Scan Output Ports

Suppressing Replacement of Sequential Cells

In Logical Scan Synthesis

Changing the Scan State of a Design

Removing Scan Specifications

Keeping Specifications Consistent

Synthesizing Three-State Disabling Logic

Configuring Three-State Buses

Configuring External Three-State Buses

Configuring Internal Three-State Buses

Overriding Global Three-State Bus Configuration Settings

Disabling Three-State Buses and Bidirectional Ports

Handling Bidirectional Ports

Setting Individual Bidirectional Port Behavior

Fixed Direction Bidirectional Ports

Using Scan Lock-Up Elements

Assigning Test Port Attributes

Architecting Test Clocks

Setting Test Clocks

Specifying Clock Timing Attributes

The Waveform Section

Specifying the Clock Period

Multiplexed Flip-Flop Design Example

Handling Multiple Clock Designs

Internal Clocks

Assigning Scan Chains to Specific Clocks

Requirements for Valid Scan Chain Ordering

Using Multiple Master Clocks in LSSD Designs

Dedicated Test Clocks for Each Clock Domain

Controlling LSSD Slave Clock Routing

Modifying Your Scan Architecture

Post-Scan Test Design Rule Checking

Preparing for Test Design Rule Checking After Scan Insertion

Checking for Topological Violations

Checking for Scan Connectivity Violations

Scan Chain Extraction

Causes of Common Violations

Ability to Load Data Into Scan Cells

Incomplete Test Configuration

Invalid Clock Logic

Incorrect Clock Timing Relationship

Nonscan Sequential Cells

Ability to Capture Data Into Scan Cells

Clock Driving Data

Untestable Functional Path

Uncontrollable Asynchronous Pins

Advanced DFT Architecture Methodologies

Performing Scan Extraction

Inserting Observe Test Points

Understanding Observe Points

Reading In Your Netlist and Configuring for Scan

Configuring for Observe Points

Enabling Observe Point Analysis

Defining an Observe Clock

Defining a Test Mode

Selecting and Implementing Observe Test Logic

Previewing Scan and Observe Test Point Logic

Inserting Observe Test Logic With Scan Chains

Using AutoFix

Understanding the Flow

When to Use AutoFix

Configuring AutoFix

Enabling Test Point Utilities

Specifying Test Point Signals

Specifying AutoFix Behavior

Previewing and Inserting Scan Chains and Test Points

AutoFix Script Example

Top-Down and Bottom-Up Design Flows

Top-Down Example

Bottom-Up Example

Implementing User-Defined Test Points

Types of User-Defined Test Points

Force Test Points

Control Test Points

Observe Test Points

Test Point Options

User-Defined Test Points Example

Pipelining Scan Enable Architecture

Pipelining Scan Enable Architecture in Hierarchical Flows

Using Multimode Scan Architecture

Reconfiguring Scan Chains

Defining a Test Mode

Defining the Name of a Test Mode

Defining the Usage of a Test Mode

Defining the Encoding of a Test Mode

Defining the Encoding for All Specified Test Modes

Examining the Encoding in the Preview Report

Assigning Scan Specifications to a Test Mode

Assigning Common Scan Specifications to All Test Modes

Assigning Common Scan Specifications to a Specific Test Mode

Multimode Scan Insertion Script Examples

Multivoltage Support

Configuring Scan Insertion for Multivoltages

Conflicting Voltage Mixing Specifications

Configuring Scan Insertion for Multiple Power Domains

Conflicting Power Domain Mixing Specifications

Mixture of Multivoltages and Multiple Power Domain Specifications

Reusing a Multivoltage Cell

Level Shifter as Part of Scan Path

Isolation Cell as Part of Scan Path

Strategy For Isolation Cell and Level Shifter Insertion During DFT Insertion

DFT Considerations for Low-Power Design Flows

Previewing a Multivoltage Scan Chain

Scan Extraction Flows in the Presence of Isolation Cells

Limitations

Power-Aware Functional Output Gating

Connecting to the Test Pins of Clock-Gating Cells Without Scan Insertion or Stitching

Excluding Some Clock-Gating Cells From Test-Pin Connection

Connecting User-Instantiated Clock-Gating Cells

Example Script

Limitations

Internal Pins Flow

Understanding the Architecture

DFT Commands

Enabling the Internal Pins Flow

Specifying Hookup Pins

Scan Insertion Flow

Mixing Ports and Internal Pins

Specifying Equivalency Between External Clock Ports and Internal Pins

Limitations to the Internal Pins Flow

Creating Scan Groups

Configuring Scan Grouping

Creating Scan Groups

Removing Scan Groups

Integrating an Existing Scan Chain Into a Scan Group

Reporting Scan Groups

Scan Group Flows

Known Limitations

Support for Implicit Scan Chain Elements

Command Usage

Usage Scenario

Example Script

Example Protocol

Limitations

Identification of Shift Registers

Wrapping Cores

Core Wrapping Commands

Wrapper Cells

Test Wrapper Operation

Test Wrapper Control Interface

Test Wrapper Cell Interface

Delay Test Wrapper Insertion

Separate Input and Output Wrapper Chains and Control

Wrapping Three-State and Bidirectional Ports

Specifying Multiple Wrapper Modes

Test Wrapper Exceptions

Specifying Wrapper Chains

Maximizing Register Reuse During Core Wrapping

Dedicated and Shared Wrapper Cells

Using Scan-Enable Ports

Pipelined Scan-Enable Structures

Identification of Ports With No Wrapper Cells

Dedicated Wrapper Cell Identification

Shared Wrapper Cell Identification

Input Shared Register Cell Identification

Output Shared Register Cell Identification

Overriding the Reuse Threshold

Multiple Voltage Domains

Low Power

Hierarchical Wrapping

DRC Rule Checks

Reporting the Wrapper Cells

SCANDEF Generation

Limitations When Using -maximize_reuse

Core Wrapping Flows

Scan-Stitched Core Flow

Core Creation Flow

Core Wrapping Scripts

Core Wrapping With a Dedicated Wrapper

Core Wrapping With a Shared Wrapper

Core Wrapping With Dedicated Delay Wrapper

Core Wrapping With Shared Delay Wrapper

On-Chip Clocking Support

Background

Supported Flows

Definitions

Capabilities

Limitations

Design Flows

Logical Representation of an OCC Controller

Basic Processes

Setting Up Your Environment

Enabling On-Chip Clocking Support

OCC Supported Flows

OCC and Clock Chain Synthesis Insertion Flow

Defining Clocks

Defining Global Signals

Configuring the OCC Controller

Specifying Scan Configuration

Sample Script

User-Defined Instantiated Clock Controller and Clock Chain Insertion Flow

Defining Clocks

Defining Global Signals

Specifying Clock Chains

Specifying Scan Configuration

Sample Script

Hierarchical On-Chip Clocking Flow

Reporting Clock Controller Information

OCC and Clock Chain Synthesis Insertion Flow

User-Defined Clock Controller and Clock Chain Insertion Flow

DRC Support

Enabling the OCC Controller Bypass Configuration

Example Configurations on a Design

Example 1

Example 2

Example 3

Waveform and Capture Cycle Example

Exporting to Other Tools

Verifying DFT Inserted Designs for Functionality

SVF File Generation

Test Information Passed to the SVF File

Sample Script

Formality Tool Limitations

Exporting a Design to TetraMAX ATPG

Before Exporting Your Design

Support for DFT Compiler Commands in TetraMAX ATPG

Creating Generic Capture Procedures

Exporting Your Design to TetraMAX ATPG

SCANDEF-Based Reordering Flow

Overview

Generation of a SCANDEF File

Reading and Compiling the Design

Specifying the Scan Configuration

Writing Out the SCANDEF File

Generating a SCANDEF File for Typical Flows

Generating SCANDEF Files for Hierarchical Flows

Hierarchical SCANDEF Flow Support

DFT Commands

Hierarchical SCANDEF Flows

Impact of DFT Configuration Specification on SCANDEF File Generation

Support for Other DFT Features

Limitations With SCANDEF Generation

Exporting SCANDEF Files to Third-Party Tools

Index

Numerics

DFT Compiler Scan User Guide Version E-2010.12-SP2, March 2011

Copyright Notice and Proprietary Information Copyright © 2011 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.” Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CODE V, CoMET, Confirma, Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, the Synplicity logo, UMRBus, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc. Trademarks (™) AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC plus Prototyping System, HSIM , i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks of Synopsys, Inc. Service Marks (SM) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners. DFT Compiler Scan User Guide, version E-2010.12-SP2 ii

Contents What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. Key Design-for-Test Flows and Methodologies Design-for-Test Flows in the Logical Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unmapped Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Postprocessing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Building Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapped Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading In Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Scan Replacement and Building Scan Chains. . . . . . . . . . . . . Mapped Designs With Existing Scan Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading In Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Test Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing Block by Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlling Scan Replacement During Scan Insertion . . . . . . . . . . . . . . . . . . . Hierarchical Scan Synthesis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking Test Models to Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking If a Library Contains CTL Models . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Assembly Using Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Test Models for Subdesigns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx xx xxii 1-2 1-2 1-4 1-5 1-6 1-8 1-10 1-11 1-13 1-15 1-16 1-17 1-17 1-18 1-19 1-23 1-23 1-23 1-24 1-25 iii

DFT Compiler Scan User Guide DFT Compiler Scan User Guide E-2010.12-SP2 Version E-2010.12-SP2 Reading Designs Into TetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing Test Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Level Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchical ScanEnable Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFT Flows in Design Compiler Topographical Mode . . . . . . . . . . . . . . . . . . . . . . . . Supported DFT Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFT Insertion Flow in Design Compiler Topographical Mode . . . . . . . . . . . . . . Running DFT Insertion in Design Compiler Topographical Mode . . . . . . . . . . . Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchical Support in Design Compiler Topographical Mode . . . . . . . . . . . . Top-Level Design Stitching Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom-Up/Hierarchical Flow With Test Models . . . . . . . . . . . . . . . . . . . . . Scan Insertion Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom-Up Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Down Scan Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFT Compiler Default Scan Synthesis Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Element Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Area and Timing Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting the Best Results With Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFT Compiler and Power Compiler Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . Improving Testability in Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inserting Control Points in Control Clock Gating . . . . . . . . . . . . . . . . . . . . Scan Enable Versus Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inserting Observation Points to Control Clock Gating . . . . . . . . . . . . . . . . Choosing a Depth for Observability Logic . . . . . . . . . . . . . . . . . . . . . . . . . Power Compiler/DFT Compiler Interoperability Flows . . . . . . . . . . . . . . . . . . . Using test_mode With Power Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Scan Enables With Power Compiler. . . . . . . . . . . . . . . . . . . . . . . . . Connecting Test Pins to Clock-Gating Cells Using insert_dft . . . . . . . . . . . . . . Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hookup Testport Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Rule Checking Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 1-27 1-27 1-30 1-32 1-33 1-34 1-35 1-35 1-35 1-36 1-36 1-38 1-42 1-42 1-44 1-45 1-46 1-46 1-46 1-47 1-47 1-48 1-49 1-49 1-50 1-51 1-53 1-55 1-55 1-55 1-56 1-59 1-60 1-61 1-61 iv

DFT Compiler Scan User Guide Version E-2010.12-SP2 Specifying a Particular Signal as Test Pin When Automatically Connecting Test Ports to Clock-Gating Cells . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 1-64 2. Running RTL Test Design Rule Checking Understanding the Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Setup Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating a Test Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining a Test Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading in an Initialization Protocol in STIL Format. . . . . . . . . . . . . . . . . . Setting the Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Protocol Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Protocol Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running RTL Test DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Understanding the Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violations That Prevent Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncontrollable Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches Enabled at Beginning of Clock Cycle . . . . . . . . . . . . . . . . . . . . . . Asynchronous Control Pins in Active State . . . . . . . . . . . . . . . . . . . . . . . . Violations That Prevent Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Used As Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Black Box Feeds Into Clock or Asynchronous Control . . . . . . . . . . . . . . . . Source Register Launch Before Destination Register Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registered Clock-Gating Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Feeding Multiple Register Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Violations That Reduce Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational Feedback Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks That Interact With Register Input . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Clocks That Feed Into Latches and Flip-Flops . . . . . . . . . . . . . . . Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-3 2-3 2-4 2-7 2-8 2-8 2-9 2-12 2-13 2-13 2-13 2-14 2-14 2-15 2-15 2-16 2-16 2-17 2-18 2-19 2-19 2-19 2-20 2-21 2-22 2-23 3. Running Test DRC Debugger Starting and Exiting the Graphical User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Chapter 1: Contents Contents 1-v v

DFT Compiler Scan User Guide DFT Compiler Scan User Guide E-2010.12-SP2 Version E-2010.12-SP2 Exploring the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Hierarchy View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Console Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Scan Test Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Test Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Design Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining DRC Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting Static DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing a Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Multiple Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing CTL Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting Dynamic DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands Specific to the DFT GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_inspect_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_wave_add_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_violation_schematic_add_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Performing Scan Replacement Scan Replacement Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing for Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting a Scan Replacement Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying Barriers to Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Library Does Not Contain Appropriate Scan Cells . . . . . . . . . Support for Different Types of Sequential Cells and Violations . . . . . . . . . Attributes That Prevent Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . Invalid Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invalid Asynchronous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preventing Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying a Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of Scan Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Flip-Flop Scan Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocked Scan Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 3-2 3-4 3-4 3-4 3-5 3-5 3-5 3-6 3-6 3-6 3-7 3-8 3-8 3-9 3-12 3-13 3-15 3-17 3-17 3-18 3-19 4-3 4-4 4-4 4-5 4-6 4-7 4-8 4-9 4-11 4-12 4-12 4-12 4-13 4-13 vi

DFT Compiler Scan User Guide Version E-2010.12-SP2 LSSD Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Style Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying Scan Equivalents in the Technology Library . . . . . . . . . . . . . . . . . . . . . . . Checking the Technology Library for Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . Checking for Scan Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Cell Replacement Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restricting the List of Available Scan Cells. . . . . . . . . . . . . . . . . . . . . . . . . Sample Scan Cell Replacement Strategies . . . . . . . . . . . . . . . . . . . . . . . . Mapping Sequential Gates in Scan Replacement . . . . . . . . . . . . . . . . . . . Multibit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Are Multibit Components? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How DFT Compiler Assimilates Multibit Components . . . . . . . . . . . . . . . . Controlling Multibit Test Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Multibit Component Scan Replacement . . . . . . . . . . . . . . . . . . Disabling Multibit Component Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test-Ready Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Is Test-Ready Compile? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Test-Ready Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing for Test-Ready Compile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Test-Ready Compile in the Logical Domain . . . . . . . . . . . . . . . Controlling Test-Ready Compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparing Default Compile and Test-Ready Compile . . . . . . . . . . . . . . . . . . . Complex Compile Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validating Your Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running the link Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running the check_design Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Constraint-Optimized Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Scan States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locating Scan Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing for Constraint-Optimized Scan Insertion . . . . . . . . . . . . . . . . . . . . . . Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specification Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Contents Contents 4-13 4-14 4-15 4-15 4-16 4-17 4-17 4-18 4-18 4-18 4-19 4-20 4-21 4-21 4-22 4-22 4-22 4-23 4-23 4-24 4-25 4-26 4-26 4-27 4-30 4-31 4-31 4-32 4-32 4-32 4-33 4-35 4-35 4-37 4-39 4-39 1-vii vii

DFT Compiler Scan User Guide DFT Compiler Scan User Guide E-2010.12-SP2 Version E-2010.12-SP2 5. Pre-Scan Test Design Rule Checking Test DRC Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test DRC Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the Test Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning a Known Logic State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Test Design Rule Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing and Debugging Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Reporting Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Design Rule Checking Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Design Rule Checking Message Generation . . . . . . . . . . . . . . . . . . . Understanding Test Design Rule Checking Messages. . . . . . . . . . . . . . . . Effects of Violations on Scan Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing the Sequential Cell Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classifying Sequential Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequential Cells With Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cells With Scan Shift Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Black-Box Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Value Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequential Cells Without Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking for Modeling Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Black-Box Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correcting Black Box Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unsupported Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Cell Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Cell Equivalents and the dont_touch Attribute. . . . . . . . . . . . . . . . . . Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonscan Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Timing Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocols for Common Design Timing Requirements . . . . . . . . . . . . . . . . . . . . Strobe-Before-Clock Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strobe-After-Clock Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Timing Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test_default_period Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test_default_delay Variable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test_default_bidir_delay Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 5-2 5-2 5-4 5-4 5-5 5-5 5-5 5-6 5-7 5-8 5-9 5-9 5-9 5-10 5-11 5-11 5-11 5-12 5-12 5-12 5-12 5-13 5-13 5-14 5-16 5-16 5-17 5-17 5-18 5-18 5-18 5-19 5-19 5-19 5-20 5-20 5-20 viii

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