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Micron DDR3 datasheet.pdf
4Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J1G4 – 128 Meg x 4 x 8 banks
MT41J512M8 – 64 Meg x 8 x 8 banks
MT41J256M16 – 32 Meg x 16 x 8 banks
Features
• VDD = VDDQ = 1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• Posted CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL) based on
tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
• Self refresh temperature (SRT)
• Write leveling
• Multipurpose register
• Output driver calibration
Table 1: Key Timing Parameters
Options1
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (10.5mm x 12mm) Rev. D
– 78-ball (9mm x 10.5mm) Rev. E, J
• FBGA package (Pb-free) – x16
– 96-ball (10mm x 14mm) Rev. D
– 96-ball (9mm x 14mm) Rev. E
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C)
– Industrial (–40°C ≤ TC ≤ +95°C)
• Revision
Marking
1G4
512M8
256M16
RA
RH
RE
HA
-093
-107
-125
-15E
-187E
None
IT
:D/:E/:J
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
tRCD (ns)
tRP (ns)
-0931, 2, 3, 4
-1071, 2, 3
-1251, 2,
-15E1,
-187E
2133
1866
1600
1333
1066
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
13.09
13.91
13.75
13.5
13.1
13.09
13.91
13.75
13.5
13.1
CL (ns)
13.09
13.91
13.75
13.5
13.1
Notes:
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
4. Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
Products and specifications discussed herein are subject to change by Micron without notice.
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Page size
1 Gig x 4
512 Meg x 8
256 Meg x 16
128 Meg x 4 x 8 banks
64 Meg x 8 x 8 banks
32 Meg x 16 x 8 banks
8K
64K (A[15:0])
8 (BA[2:0])
2K (A[11, 9:0])
1KB
8K
64K (A[15:0])
8 (BA[2:0])
1K (A[9:0])
1KB
8K
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3 Part Numbers
Example Part Number: MT41J512M8RH-125:E
MT41J
Configuration
Package
Speed
Revision
-
:
Configuration
1 Gig x 4
512 Meg x 8
256 Meg x 16
1G4
512M8
256M16
:D/:E/:J
Revision
Temperatu re
Commercial
Industrial temperature
None
IT
Package
78-ball 10.5mm x 12mm FBGA
78-ball 9mm x 10.5mm FBGA
96-ball 10.0mm x 14mm FBGA
96-ball 9mm x 14mm FBGA
Rev.
Mark
D
E, J
D
E
RA
RH
RE
HA
Speed Grade
tCK = 0.938ns, CL = 14
tCK = 1.071ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = E
-093
-107
-125
-15E
-187E
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 17
Package Dimensions ....................................................................................................................................... 23
Electrical Specifications .................................................................................................................................. 27
Absolute Ratings ......................................................................................................................................... 27
Input/Output Capacitance .......................................................................................................................... 28
Thermal Characteristics .................................................................................................................................. 29
Electrical Specifications – IDD Specifications and Conditions ............................................................................ 31
Electrical Characteristics – IDD Specifications .................................................................................................. 42
Electrical Specifications – DC and AC .............................................................................................................. 46
DC Operating Conditions ........................................................................................................................... 46
Input Operating Conditions ........................................................................................................................ 46
AC Overshoot/Undershoot Specification ..................................................................................................... 49
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 53
Slew Rate Definitions for Differential Input Signals ...................................................................................... 55
ODT Characteristics ....................................................................................................................................... 56
ODT Resistors ............................................................................................................................................ 57
ODT Sensitivity .......................................................................................................................................... 58
ODT Timing Definitions ............................................................................................................................. 58
Output Driver Impedance ............................................................................................................................... 62
34 Ohm Output Driver Impedance .............................................................................................................. 63
34 Ohm Driver ............................................................................................................................................ 64
34 Ohm Output Driver Sensitivity ................................................................................................................ 65
Alternative 40 Ohm Driver .......................................................................................................................... 66
40 Ohm Output Driver Sensitivity ................................................................................................................ 66
Output Characteristics and Operating Conditions ............................................................................................ 68
Reference Output Load ............................................................................................................................... 70
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 71
Slew Rate Definitions for Differential Output Signals .................................................................................... 72
Speed Bin Tables ............................................................................................................................................ 73
Electrical Characteristics and AC Operating Conditions ................................................................................... 78
Command and Address Setup, Hold, and Derating ........................................................................................... 98
Data Setup, Hold, and Derating ...................................................................................................................... 106
Commands – Truth Tables ............................................................................................................................. 115
Commands ................................................................................................................................................... 118
DESELECT ................................................................................................................................................ 118
NO OPERATION ........................................................................................................................................ 118
ZQ CALIBRATION LONG ........................................................................................................................... 118
ZQ CALIBRATION SHORT .......................................................................................................................... 118
ACTIVATE ................................................................................................................................................. 118
READ ........................................................................................................................................................ 118
WRITE ...................................................................................................................................................... 119
PRECHARGE ............................................................................................................................................. 120
REFRESH .................................................................................................................................................. 120
SELF REFRESH .......................................................................................................................................... 121
DLL Disable Mode ..................................................................................................................................... 122
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
Input Clock Frequency Change ...................................................................................................................... 126
Write Leveling ............................................................................................................................................... 128
Write Leveling Procedure ........................................................................................................................... 130
Write Leveling Mode Exit Procedure ........................................................................................................... 132
Initialization ................................................................................................................................................. 133
Mode Registers .............................................................................................................................................. 135
Mode Register 0 (MR0) ................................................................................................................................... 136
Burst Length ............................................................................................................................................. 136
Burst Type ................................................................................................................................................. 137
DLL RESET ................................................................................................................................................ 138
Write Recovery .......................................................................................................................................... 138
Precharge Power-Down (Precharge PD) ...................................................................................................... 139
CAS Latency (CL) ....................................................................................................................................... 139
Mode Register 1 (MR1) ................................................................................................................................... 140
DLL Enable/DLL Disable ........................................................................................................................... 140
Output Drive Strength ............................................................................................................................... 141
OUTPUT ENABLE/DISABLE ...................................................................................................................... 141
TDQS Enable ............................................................................................................................................. 141
On-Die Termination .................................................................................................................................. 142
WRITE LEVELING ..................................................................................................................................... 142
POSTED CAS ADDITIVE Latency ................................................................................................................ 142
Mode Register 2 (MR2) ................................................................................................................................... 143
CAS Write Latency (CWL) ........................................................................................................................... 144
AUTO SELF REFRESH (ASR) ....................................................................................................................... 144
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 145
SRT vs. ASR ............................................................................................................................................... 145
DYNAMIC ODT ......................................................................................................................................... 145
Mode Register 3 (MR3) ................................................................................................................................... 146
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146
MPR Functional Description ...................................................................................................................... 147
MPR Register Address Definitions and Bursting Order ................................................................................. 148
MPR Read Predefined Pattern .................................................................................................................... 154
MODE REGISTER SET (MRS) Command ........................................................................................................ 154
ZQ CALIBRATION Operation ......................................................................................................................... 155
ACTIVATE Operation ..................................................................................................................................... 156
READ Operation ............................................................................................................................................ 158
WRITE Operation .......................................................................................................................................... 169
DQ Input Timing ....................................................................................................................................... 177
PRECHARGE Operation ................................................................................................................................. 179
SELF REFRESH Operation .............................................................................................................................. 179
Extended Temperature Usage ........................................................................................................................ 181
Power-Down Mode ........................................................................................................................................ 182
RESET Operation ........................................................................................................................................... 190
On-Die Termination (ODT) ............................................................................................................................ 192
Functional Representation of ODT ............................................................................................................. 192
Nominal ODT ............................................................................................................................................ 192
Dynamic ODT ............................................................................................................................................... 194
Dynamic ODT Special Use Case ................................................................................................................. 194
Functional Description .............................................................................................................................. 194
Synchronous ODT Mode ................................................................................................................................ 200
ODT Latency and Posted ODT .................................................................................................................... 200
Timing Parameters .................................................................................................................................... 200
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
ODT Off During READs .............................................................................................................................. 203
Asynchronous ODT Mode .............................................................................................................................. 205
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 207
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 209
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 211
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
List of Figures
Figure 1: DDR3 Part Numbers .......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 1 Gig x 4 Functional Block Diagram .................................................................................................. 14
Figure 4: 512 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 256 Meg x 16 Functional Block Diagram ........................................................................................... 16
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17
Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18
Figure 8: 78-Ball FBGA – x4, x8 (RA) ................................................................................................................ 23
Figure 9: 78-Ball FBGA – x4, x8 (RH) ............................................................................................................... 24
Figure 10: 96-Ball FBGA – x16 (RE) ................................................................................................................. 25
Figure 11: 96-Ball FBGA – x16 (HA) ................................................................................................................. 26
Figure 12: Thermal Measurement Point ......................................................................................................... 30
Figure 13: Input Signal .................................................................................................................................. 48
Figure 14: Overshoot ..................................................................................................................................... 49
Figure 15: Undershoot ................................................................................................................................... 49
Figure 16: VIX for Differential Signals .............................................................................................................. 51
Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 51
Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 52
Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 54
Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 55
Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 56
Figure 22: ODT Timing Reference Load .......................................................................................................... 59
Figure 23: tAON and tAOF Definitions ............................................................................................................ 60
Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 60
Figure 25: tADC Definition ............................................................................................................................. 61
Figure 26: Output Driver ................................................................................................................................ 62
Figure 27: DQ Output Signal .......................................................................................................................... 69
Figure 28: Differential Output Signal .............................................................................................................. 70
Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 70
Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 71
Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 72
Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 102
Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 103
Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 104
Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 105
Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 111
Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 112
Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 113
Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 114
Figure 40: Refresh Mode ............................................................................................................................... 121
Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 123
Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 124
Figure 43: DLL Disable tDQSCK .................................................................................................................... 125
Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 127
Figure 45: Write Leveling Concept ................................................................................................................. 128
Figure 46: Write Leveling Sequence ............................................................................................................... 131
Figure 47: Write Leveling Exit Procedure ....................................................................................................... 132
Figure 48: Initialization Sequence ................................................................................................................. 134
Figure 49: MRS to MRS Command Timing (tMRD) ......................................................................................... 135
Figure 50: MRS to nonMRS Command Timing (tMOD) .................................................................................. 136
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 51: Mode Register 0 (MR0) Definitions ................................................................................................ 137
Figure 52: READ Latency .............................................................................................................................. 139
Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 140
Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 143
Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 144
Figure 56: CAS Write Latency ........................................................................................................................ 144
Figure 57: Mode Register 3 (MR3) Definition ................................................................................................. 146
Figure 58: Multipurpose Register (MPR) Block Diagram ................................................................................. 147
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 150
Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 151
Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 152
Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 153
Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 155
Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 156
Figure 65: Example: tFAW ............................................................................................................................. 157
Figure 66: READ Latency .............................................................................................................................. 158
Figure 67: Consecutive READ Bursts (BL8) .................................................................................................... 160
Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 160
Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 161
Figure 70: READ (BL8) to WRITE (BL8) .......................................................................................................... 161
Figure 71: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 162
Figure 72: READ to PRECHARGE (BL8) .......................................................................................................... 162
Figure 73: READ to PRECHARGE (BC4) ......................................................................................................... 163
Figure 74: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 163
Figure 75: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 163
Figure 76: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 165
Figure 77: Data Strobe Timing – READs ......................................................................................................... 166
Figure 78: Method for Calculating tLZ and tHZ ............................................................................................... 167
Figure 79: tRPRE Timing ............................................................................................................................... 167
Figure 80: tRPST Timing ............................................................................................................................... 168
Figure 81: tWPRE Timing .............................................................................................................................. 170
Figure 82: tWPST Timing .............................................................................................................................. 170
Figure 83: WRITE Burst ................................................................................................................................ 171
Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 172
Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 172
Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 173
Figure 87: WRITE (BL8) to READ (BL8) .......................................................................................................... 173
Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 174
Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 175
Figure 90: WRITE (BL8) to PRECHARGE ........................................................................................................ 176
Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 176
Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 177
Figure 93: Data Input Timing ........................................................................................................................ 178
Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 180
Figure 95: Active Power-Down Entry and Exit ................................................................................................ 184
Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 185
Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 185
Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 186
Figure 99: Power-Down Entry After WRITE .................................................................................................... 186
Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 187
Figure 101: REFRESH to Power-Down Entry .................................................................................................. 187
Figure 102: ACTIVATE to Power-Down Entry ................................................................................................. 188
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 188
Figure 104: MRS Command to Power-Down Entry ......................................................................................... 189
Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 189
Figure 106: RESET Sequence ......................................................................................................................... 191
Figure 107: On-Die Termination ................................................................................................................... 192
Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 197
Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 197
Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 198
Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 199
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 199
Figure 113: Synchronous ODT ...................................................................................................................... 201
Figure 114: Synchronous ODT (BC4) ............................................................................................................. 202
Figure 115: ODT During READs .................................................................................................................... 204
Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 206
Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 208
Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 210
Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 212
Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 212
PDF: 09005aef8417277b
4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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